技术领域technical field
本发明涉及一种高压元件及其制造方法，特别是指一种增强崩溃防护电压的高压元件及其制造方法。The invention relates to a high-voltage component and a manufacturing method thereof, in particular to a high-voltage component with enhanced breakdown protection voltage and a manufacturing method thereof.
背景技术Background technique
图1显示现有技术的横向双扩散金属氧化物半导体(lateral doublediffused metal oxide semiconductor，LDMOS)元件剖视图。如图1所示，P型基板11中具有多个绝缘区12，以定义元件区100，绝缘区12例如为浅沟槽绝缘(shallow trench isolation，STI)结构或如图所示的区域氧化(local oxidation of silicon，LOCOS)结构；P型基板11还包含N型埋层14。LDMOS元件形成于元件区100中，除N型埋层14外，还包含栅极13、漏极15、源极16、P型井区17、以及N型井区18。其中，N型埋层14、漏极15、源极16、以及N型井区18由微影技术或以部分或全部的栅极13、绝缘区12为屏蔽，以定义各区域，并分别以离子植入技术，将N型杂质，以加速离子的形式，植入定义的区域内所形成；而P型井区17则是由微影技术，定义该区域，并以离子植入技术，将P型杂质，以加速离子的形式，植入定义的区域内所形成。其中，漏极15与源极16分别位于栅极13两侧下方。而且LDMOS元件中，栅极13有一部分位于场氧化区22上。FIG. 1 shows a cross-sectional view of a lateral doublediffused metal oxide semiconductor (LDMOS) device in the prior art. As shown in FIG. 1, there are a plurality of insulating regions 12 in the P-type substrate 11 to define the element region 100. The insulating regions 12 are, for example, shallow trench isolation (shallow trench isolation, STI) structures or regional oxidation as shown ( local oxidation of silicon, LOCOS) structure; the P-type substrate 11 also includes an N-type buried layer 14. The LDMOS device is formed in the device region 100 , which includes a gate 13 , a drain 15 , a source 16 , a P-well 17 , and an N-type well 18 in addition to the N-type buried layer 14 . Wherein, the N-type buried layer 14, the drain electrode 15, the source electrode 16, and the N-type well region 18 are shielded by lithography technology or with part or all of the gate electrode 13 and the insulating region 12 to define each region, and respectively use Ion implantation technology is formed by implanting N-type impurities into a defined area in the form of accelerated ions; while the P-type well region 17 is defined by lithography technology, and ion implantation technology is used to place P-type impurities, in the form of accelerated ions, are implanted into defined regions. Wherein, the drain 15 and the source 16 are respectively located under two sides of the gate 13 . Moreover, in the LDMOS device, a part of the gate 13 is located on the field oxide region 22 .
图2显示现有技术的双扩散漏极金属氧化物半导体(doublediffused drain metal oxide semiconductor，DDDMOS)元件剖视图。与前述LDMOS元件不同的是，DDDMOS元件的栅极13a并非有一部分位于场氧化区22上，而是完全位于P型基板11表面上。FIG. 2 shows a cross-sectional view of a double diffused drain metal oxide semiconductor (DDDMOS) device in the prior art. Different from the aforementioned LDMOS element, the gate 13 a of the DDDMOS element is not partly located on the field oxide region 22 , but completely located on the surface of the P-type substrate 11 .
LDMOS与DDDMOS元件为高压元件，亦即其是设计供应用于较高的操作电压，但当高压元件需要与一般较低操作电压的元件整合于同一基板上时，为配合较低操作电压的元件制程，需要以相同的离子植入参数来制作高压元件和低压元件，使得高压元件的离子植入参数受到限制，因而降低了高压元件崩溃防护电压，限制了元件的应用范围。若不牺牲高压元件崩溃防护电压，则必须增加制程步骤，另行以不同离子植入参数的步骤来制作高压元件，但如此一来将提高制造成本，才能达到所欲的崩溃防护电压。LDMOS and DDDMOS components are high-voltage components, that is, they are designed to supply higher operating voltages, but when high-voltage components need to be integrated on the same substrate with generally lower operating voltage components, in order to cooperate with lower operating voltage components The manufacturing process needs to use the same ion implantation parameters to manufacture high-voltage components and low-voltage components, so that the ion implantation parameters of high-voltage components are limited, thereby reducing the breakdown protection voltage of high-voltage components and limiting the application range of components. If the breakdown protection voltage of the high-voltage components is not sacrificed, it is necessary to increase the process steps and manufacture the high-voltage components with steps of different ion implantation parameters, but this will increase the manufacturing cost to achieve the desired breakdown protection voltage.
有鉴于此，本发明即针对上述现有技术的不足，提出一种高压元件及其制造方法，在不增加制程步骤的情况下，提高元件操作的崩溃防护电压，增加元件的应用范围，并可整合于低压元件的制程。In view of this, the present invention aims at the deficiencies of the above-mentioned prior art, and proposes a high-voltage element and a manufacturing method thereof, which can improve the breakdown protection voltage of the element operation without increasing the process steps, increase the application range of the element, and can Integrate in the process of low-voltage components.
发明内容Contents of the invention
本发明的目的在于克服现有技术的不足与缺陷，提出一种高压元件及其制造方法。The purpose of the present invention is to overcome the deficiencies and defects of the prior art, and propose a high-voltage component and a manufacturing method thereof.
为达上述目的，本发明提供一种高压元件，形成于一第一导电型基板中，该第一导电型基板具有一基板上表面，该高压元件包含：一第二导电型埋层，形成于该第一导电型基板中；一第一导电型井区，形成于该基板上表面下方，且由剖视图视之，该第一导电型井区介于该基板上表面与该第二导电型埋层之间；以及一第二导电型井区，形成于该基板上表面下方，且该第二导电型井区与该第一导电型井区在水平方向上位于不同位置并相邻接，其中，该第二导电型井区包括一井区下表面，且该井区下表面具有第一部分与第二部分，该第一部分位于该第二导电型埋层上方，并与该第二导电型埋层电性耦接，且该第二部分不在该第二导电型埋层上方，并与该第一导电型基板形成PN接面。To achieve the above object, the present invention provides a high-voltage element formed in a substrate of a first conductivity type, the substrate of the first conductivity type has an upper surface of the substrate, and the high-voltage element includes: a buried layer of a second conductivity type formed in In the substrate of the first conductivity type; a well region of the first conductivity type is formed below the upper surface of the substrate, and viewed from a cross-sectional view, the well region of the first conductivity type is between the upper surface of the substrate and the second conductivity type buried between the layers; and a second conductivity type well area formed below the upper surface of the substrate, and the second conductivity type well area and the first conductivity type well area are located at different positions in the horizontal direction and adjacent to each other, wherein , the well region of the second conductivity type includes a lower surface of the well region, and the lower surface of the well region has a first portion and a second portion, the first portion is located above the buried layer of the second conductivity type, and is connected to the buried layer of the second conductivity type layers are electrically coupled, and the second portion is not above the buried layer of the second conductivity type, and forms a PN junction with the substrate of the first conductivity type.
就另一观点，本发明也提供了一种高压元件制造方法，包含：提供一第一导电型基板，其具有一基板上表面；形成一第二导电型埋层于该第一导电型基板中；形成一第一导电型井区于该基板上表面下方，且由剖视图视之，该第一导电型井区介于该基板上表面与该第二导电型埋层之间；以及形成一第二导电型井区于该基板上表面下方，且该第二导电型井区与该第一导电型井区在水平方向上位于不同位置并相邻接，其中，该第二导电型井区包括一井区下表面，且该井区下表面具有第一部分与第二部分，该第一部分位于该第二导电型埋层上方，并与该第二导电型埋层电性耦接，且该第二部分不在该第二导电型埋层上方，并与该第一导电型基板形成PN接面。From another point of view, the present invention also provides a method for manufacturing a high-voltage element, including: providing a substrate of a first conductivity type having an upper surface of the substrate; forming a buried layer of a second conductivity type in the substrate of the first conductivity type ; forming a well region of the first conductivity type below the upper surface of the substrate, and viewed from a cross-sectional view, the well region of the first conductivity type is between the upper surface of the substrate and the buried layer of the second conductivity type; and forming a first conductivity type well region The well of the second conductivity type is located below the upper surface of the substrate, and the well of the second conductivity type is located at different positions in the horizontal direction and adjacent to the well of the first conductivity type, wherein the well of the second conductivity type includes A lower surface of the well area, and the lower surface of the well area has a first part and a second part, the first part is located above the buried layer of the second conductivity type, and is electrically coupled with the buried layer of the second conductivity type, and the first part is located above the buried layer of the second conductive type, and the second conductive type buried layer The second part is not above the buried layer of the second conductive type, and forms a PN junction with the substrate of the first conductive type.
其中一种较佳的实施例中，该第二导电型井区宜于该高压元件操作于一不导通状态时，大致空乏。In one preferred embodiment, the well region of the second conductivity type is suitable to be substantially depleted when the high voltage element operates in a non-conducting state.
另一种较佳实施例中，该高压元件宜更包含一第二导电型漂移区，位于该第二导电型井区中，且在水平方向上定义于该第一导电型井区与一漏极之间，其中当该高压元件操作于一不导通状态时，该第二导电型漂移区完全空乏。In another preferred embodiment, the high voltage element preferably further includes a drift region of the second conductivity type, located in the well region of the second conductivity type, and defined between the well region of the first conductivity type and a drain in the horizontal direction. Between poles, wherein when the high voltage element operates in a non-conducting state, the drift region of the second conductivity type is completely depleted.
又一种较佳实施例中，该高压元件为一横向双扩散金属氧化物半导体(lateral double diffused metal oxide semiconductor，LDMOS)元件或双扩散漏极金属氧化物半导体(double diffused drain metal oxidesemiconductor，DDDMOS)元件。In yet another preferred embodiment, the high voltage element is a lateral double diffused metal oxide semiconductor (LDMOS) element or a double diffused drain metal oxide semiconductor (DDDMOS) element.
再又一种较佳实施例中，该第一导电型基板宜包括一第一导电型裸基板、一第一导电型埋层、或一第一导电型磊晶层；其中该第一导电型埋层由离子植入制程步骤植入第一导电型杂质所形成，且该第一导电型磊晶层由磊晶技术所形成。In yet another preferred embodiment, the substrate of the first conductivity type preferably includes a bare substrate of the first conductivity type, a buried layer of the first conductivity type, or an epitaxial layer of the first conductivity type; wherein the first conductivity type The buried layer is formed by implanting impurities of the first conductivity type in the ion implantation process step, and the epitaxial layer of the first conductivity type is formed by epitaxial technology.
下面通过具体实施例详加说明，当更容易了解本发明的目的、技术内容、特点及其所达成的功效。The following will be described in detail through specific embodiments, so that it is easier to understand the purpose, technical content, characteristics and effects of the present invention.
附图说明Description of drawings
图1显示现有技术的LDMOS元件剖视图；FIG. 1 shows a cross-sectional view of an LDMOS element in the prior art;
图2显示现有技术的DDDMOS元件剖视图；FIG. 2 shows a sectional view of a prior art DDDMOS element;
图3显示本发明的第一个实施例；Figure 3 shows a first embodiment of the present invention;
图4显示本发明的第二个实施例；Figure 4 shows a second embodiment of the present invention;
图5A与图5B显示现有技术与本发明第一个实施例中LDMOS元件不导通(OFF)状态时的电场模拟图的比较；5A and 5B show the comparison of the electric field simulation diagrams of the LDMOS element in the non-conducting (OFF) state between the prior art and the first embodiment of the present invention;
图6A-6D举例说明利用本发明的高压元件的制造方法。6A-6D illustrate a method of manufacturing a high voltage component utilizing the present invention.
图中符号说明Explanation of symbols in the figure
11 基板11 Substrate
12 绝缘区12 insulation area
13，13a栅极13, 13a grid
14 N型埋层14 N-type buried layer
14a 光阻14a photoresist
15 漏极15 drain
16 源极16 source
17 P型井区17 P-type well area
18 N型井区18 N-type well area
18a 第一部分18a Part 1
18b 第二部分18b Part II
18c 漂移区18c drift zone
22 场氧化区22 field oxidation zone
100 元件区100 component area
具体实施方式Detailed ways
本发明中的图式均属示意，主要意在表示制程步骤以及各层之间的上下次序关系，至于形状、厚度与宽度则并未依照比例绘制。The drawings in the present invention are all schematic, mainly intended to represent the manufacturing process steps and the upper and lower sequence relationship between each layer, as for the shape, thickness and width, they are not drawn to scale.
请参阅图3，显示本发明的第一个实施例，本实施例显示本发明应用于LDMOS元件的剖视示意图。于基板11中，形成绝缘区12以定义元件区100，其中基板11例如为P型但不限于为P型(在其它实施型态中亦可以为N型)；绝缘区12例如为STI结构或如图所示的区域氧化LOCOS结构，并且，基板11中，包含导电型与基板11不相同的N型(在其它实施型态中亦可以为P型)埋层14。此外，如图3所示，于基板11中，形成P型(在其它实施型态中亦可以为N型)井区17与N型(在其它实施型态中亦可以为P型)井区18。其中，P型井区17介于基板11上表面与N型埋层14之间；N型井区18形成于基板11上表面下方，且N型井区与P型井区在水平方向上位于不同位置并相邻接。于基板11表面，元件区100中，以氧化技术于该基板11表面上形成场氧化区22，其例如为STI结构或区域氧化LOCOS结构；并且，场氧化区22可利用但不限于与绝缘区12相同制程步骤形成。接着于元件区100中，形成栅极13、漏极15、与源极16；其中，漏极15与源极16例如为N型但不限于为N型(在其它实施型态中亦可以为P型)，分别位于元件区100中的栅极13两侧，且由俯视图(未示出)视之，漏极15与源极16由栅极13与场氧化区22隔开。Please refer to FIG. 3 , which shows a first embodiment of the present invention. This embodiment shows a schematic cross-sectional view of the present invention applied to an LDMOS device. In the substrate 11, an insulating region 12 is formed to define the element region 100, wherein the substrate 11 is, for example, P-type but not limited to P-type (it may also be N-type in other implementation forms); the insulating region 12 is, for example, an STI structure or The region oxidizes the LOCOS structure as shown in the figure, and the substrate 11 includes an N-type (or P-type in other implementations) buried layer 14 whose conductivity type is different from that of the substrate 11 . In addition, as shown in FIG. 3, in the substrate 11, a P-type (or N-type in other embodiments) well region 17 and an N-type (or P-type in other embodiments) well region are formed. 18. Wherein, the P-type well region 17 is located between the upper surface of the substrate 11 and the N-type buried layer 14; the N-type well region 18 is formed below the upper surface of the substrate 11, and the N-type well region and the P-type well region are located in the horizontal direction. different locations and adjacent to each other. On the surface of the substrate 11, in the element region 100, a field oxidation region 22 is formed on the surface of the substrate 11 by oxidation technology, such as an STI structure or a region oxidation LOCOS structure; and, the field oxidation region 22 can be used but not limited to an insulating region 12 same process steps are formed. Next, in the element region 100, a gate 13, a drain 15, and a source 16 are formed; wherein, the drain 15 and the source 16 are, for example, N-type but not limited to N-type (in other implementation forms, they can also be N-type P-type), respectively located on both sides of the gate 13 in the element region 100 , and viewed from a top view (not shown), the drain 15 and the source 16 are separated by the gate 13 and the field oxide region 22 .
与现有技术不同的是，在本实施例中，N型井区18的下表面具有第一部分18a与第二部分18b，由椭圆形虚线所示意，其中第一部分18a位于N型埋层14上方，并与N型埋层电性耦接，且第二部分18b不在N型埋层14上方，并与P型基板11形成PN接面。Different from the prior art, in this embodiment, the lower surface of the N-type well region 18 has a first part 18a and a second part 18b, which are indicated by oval dotted lines, wherein the first part 18a is located above the N-type buried layer 14 , and is electrically coupled to the N-type buried layer, and the second portion 18 b is not above the N-type buried layer 14 , and forms a PN junction with the P-type substrate 11 .
此种安排方式的优点包括：在元件规格上，可提高高压元件的崩溃防护电压，其原因将详述于后；在制程上，可以但不限于利用形成N型埋层14的制程与光罩，于离子植入制程步骤时，将第二部分18b下方以光阻或其它屏蔽遮住，阻挡加速离子植入第二部分18b下方，而不需要另外新增光罩或制程步骤，故可降低制造成本。The advantages of this arrangement include: In terms of component specifications, the breakdown protection voltage of high-voltage components can be improved, the reasons for which will be described in detail later; in terms of manufacturing process, the process and photomask for forming the N-type buried layer 14 can be used, but not limited to , during the ion implantation process steps, the lower part of the second part 18b is covered with a photoresist or other shields to block the acceleration of ion implantation under the second part 18b, without additional additional photomasks or process steps, so it can reduce manufacturing cost.
图4显示本发明的第二个实施例。与第一个实施例不同的是，本实施例应用本发明于DDDMOS元件而非LDMOS元件。DDDMOS元件的栅极13a并非有一部分位于场氧化区22上，而是完全位于P型基板11表面上。Fig. 4 shows a second embodiment of the present invention. Different from the first embodiment, this embodiment applies the present invention to DDDMOS devices instead of LDMOS devices. The gate 13 a of the DDDMOS element is not partly located on the field oxide region 22 , but completely located on the surface of the P-type substrate 11 .
图5A与图5B显示现有技术与本发明第一个实施例中LDMOS元件不导通(OFF)状态时的电场模拟图的比较。并进而说明如何利用本发明增强高压元件的崩溃防护电压。请参阅电场模拟图图5A，显示现有技术的LDMOS元件不导通状态时的电场模拟图。以N型LDMOS元件为例，操作于不导通状态时，栅极13电压例如为零电位，而P型井区17与N型埋层14间、P型井区17与N型井区18间、以及N型井区18与P型基板11间的PN接面皆为逆向偏压，因而存在宽度不同的空乏区，如图5A中的电场线所示意，而无电场线分布的区域，则代表其为零电位。FIG. 5A and FIG. 5B show a comparison of electric field simulation diagrams of the LDMOS device in the OFF state in the prior art and the first embodiment of the present invention. And further explain how to use the present invention to enhance the breakdown protection voltage of high-voltage components. Please refer to FIG. 5A , which shows the simulation diagram of the electric field when the LDMOS device in the prior art is in the off state. Taking an N-type LDMOS element as an example, when operating in a non-conducting state, the voltage of the gate 13 is, for example, zero potential, and between the P-type well region 17 and the N-type buried layer 14, between the P-type well region 17 and the N-type well region 18 The PN junction between the N-type well region 18 and the P-type substrate 11 is reverse biased, so there are depletion regions with different widths, as shown by the electric field lines in FIG. It means that it has zero potential.
请继续参阅图5B，显示本发明第一个实施例中LDMOS元件不导通(OFF)状态时的电场模拟图。与图5A所示的现有技术不同的是，由于N型井区18下表面具有第一部分18a与N型埋层14耦接，以及第二部分18b与P型基板11耦接，此第二部分18b与P型基板11间，于LDMOS元件不导通时，形成逆向偏压状态的PN接面。由图中电场线的分布状况可以推知，N型井区18大致上因三个PN接面(P型井区17与N型井区18间、以及N型井区18的侧表面和下表面中的第二部分18b与P型基板11间)的逆向偏压状态而完全空乏。Please continue to refer to FIG. 5B , which shows a simulation diagram of the electric field of the LDMOS element in the OFF state in the first embodiment of the present invention. Different from the prior art shown in FIG. 5A, since the lower surface of the N-type well region 18 has a first part 18a coupled with the N-type buried layer 14, and a second part 18b coupled with the P-type substrate 11, the second Between the portion 18b and the P-type substrate 11, when the LDMOS element is not conducting, a PN junction in a reverse bias state is formed. From the distribution of the electric field lines in the figure, it can be inferred that the N-type well region 18 is roughly due to three PN junctions (between the P-type well region 17 and the N-type well region 18, and the side surface and the lower surface of the N-type well region 18). The reverse bias state between the second portion 18b and the P-type substrate 11 is completely depleted.
比较图5A与5B，可以看出利用本发明的图5B相较于现有技术图5A，于高压元件不导通时，其N型井区18大致上完全空乏。因此，其可承受的操作电压较高，也就是其崩溃防护电压较高。这举例说明了本发明可提高高压元件的崩溃防护电压的优点。其中，图5B中，矩形虚线标示出N型漂移区18c，其位于N型井区18中，可以但不限于由形成N型井区18相同的制程步骤完成，且在水平方向上定义于P井区17与漏极15之间，其中当高压元件操作于不导通状态时，N型漂移区18c完全空乏，以加强高压元件的崩溃防护电压。需说明的是，N型漂移区18c为高压元件于导通(ON)状态时电流所经过的区域，且紧接漏极15所耦接的高电压的操作电压，因此，是最容易发生崩溃的区域。Comparing FIGS. 5A and 5B , it can be seen that in FIG. 5B using the present invention, compared with FIG. 5A in the prior art, when the high-voltage element is not conducting, its N-type well region 18 is substantially completely depleted. Therefore, its withstand operating voltage is higher, that is, its crash protection voltage is higher. This illustrates the advantage of the present invention to increase the breakdown protection voltage of high voltage components. Wherein, in FIG. 5B, the rectangular dotted line marks the N-type drift region 18c, which is located in the N-type well region 18, which can be completed by but not limited to the same process steps as the N-type well region 18 is formed, and is defined in the horizontal direction at P Between the well region 17 and the drain 15, the N-type drift region 18c is completely depleted when the high-voltage element operates in a non-conducting state, so as to enhance the breakdown protection voltage of the high-voltage element. It should be noted that the N-type drift region 18c is the region through which the current passes when the high-voltage element is in the ON state, and it is close to the operating voltage of the high voltage coupled to the drain 15, so it is the most prone to collapse Area.
图6A-6D举例说明利用本发明的高压元件的制造方法。如图6A所示，首先提供例如但不限于P型基板11(在其它实施型态中亦可以为N型)，其具有基板上表面；接着于P型基板11中，如图所示利用光阻14a或其它屏蔽遮住，阻挡如虚线箭头所示意的N型杂质加速离子植入P型基板11中，以形成N型埋层14。6A-6D illustrate a method of manufacturing a high voltage component utilizing the present invention. As shown in FIG. 6A , first provide, for example but not limited to, a P-type substrate 11 (in other implementations, it may also be N-type), which has an upper surface of the substrate; then in the P-type substrate 11, use light as shown in the figure The barrier 14a or other shields block the N-type impurity accelerated ion implantation into the P-type substrate 11 as indicated by the dotted arrow, so as to form the N-type buried layer 14 .
接下来，如图6B所示，分别利用光阻或其它屏蔽定义P型井区17与N型井区18，并分别以P型与N型杂质的加速离子，形成P型井区17与N型井区18。其中，由剖视图图6B视之，P型井区17介于基板11上表面与N型埋层14之间，且N型井区18于基板11上表面下方，且N型井区18与P型井区17在水平方向上位于不同位置并相邻接。Next, as shown in FIG. 6B, use photoresist or other shielding to define P-type well region 17 and N-type well region 18 respectively, and form P-type well region 17 and N-type well region 18 with accelerated ions of P-type and N-type impurities respectively. Type well area 18. 6B, the P-type well region 17 is between the upper surface of the substrate 11 and the N-type buried layer 14, and the N-type well region 18 is below the upper surface of the substrate 11, and the N-type well region 18 is connected to the P-type well region. The type well areas 17 are located at different positions in the horizontal direction and are adjacent to each other.
再接下来，如图6C所示，于基板11中，形成绝缘区12以定义元件区100，并例如但不限于利用同样的制程步骤，形成场氧化区22。其中，N井区18包括井区下表面，且该井区下表面具有第一部分18a与第二部分18b，第一部分18a位于N型埋层14上方，并与N型埋层14电性耦接，且第二部分18b不在N型埋层14上方，并与P型基板11形成PN接面。Next, as shown in FIG. 6C , in the substrate 11 , an insulating region 12 is formed to define the device region 100 , and, for example but not limited to, the same process steps are used to form a field oxide region 22 . Wherein, the N well region 18 includes the lower surface of the well region, and the lower surface of the well region has a first part 18a and a second part 18b, the first part 18a is located above the N-type buried layer 14, and is electrically coupled with the N-type buried layer 14 , and the second portion 18 b is not above the N-type buried layer 14 , and forms a PN junction with the P-type substrate 11 .
最后请参阅图6D，于元件区100中，形成栅极13、漏极15、与源极16；其中，漏极15与源极16例如为N型但不限于为N型(在其它实施型态中亦可以为P型)，分别位于元件区100中的栅极13两侧，且由俯视图(未示出)视之，漏极15与源极16由栅极13与场氧化区22隔开。Finally, please refer to FIG. 6D, in the element region 100, a gate 13, a drain 15, and a source 16 are formed; wherein, the drain 15 and the source 16 are, for example, N-type but not limited to N-type (in other implementation types It can also be P-type in the state), respectively located on both sides of the gate 13 in the element region 100, and viewed from a top view (not shown), the drain 15 and the source 16 are separated by the gate 13 and the field oxide region 22 open.
需说明的是，P型基板11例如可为P型裸基板，也就是直接利用P型晶圆作为P型基板11；P型基板11亦可以为P型埋层，例如但不限于以离子植入技术来形成；或是，P型基板11亦可以为P型磊晶层，由磊晶技术所形成。It should be noted that the P-type substrate 11 can be, for example, a P-type bare substrate, that is, a P-type wafer is directly used as the P-type substrate 11; the P-type substrate 11 can also be a P-type buried layer, such as but not limited to ion implantation or, the P-type substrate 11 can also be a P-type epitaxial layer formed by epitaxial technology.
以上已针对较佳实施例来说明本发明，只是以上所述，仅为使本领域技术人员易于了解本发明的内容，并非用来限定本发明的权利范围。在本发明的相同精神下，本领域技术人员可以思及各种等效变化。例如，在不影响元件主要的特性下，可加入其它制程步骤或结构，如深井区等；又如，微影技术并不限于光罩技术，亦可包含电子束微影技术；再如，所示的电场模拟图为其中一种实施例的模拟结果，亦可以不需将N型井区完全空乏而仅有部分空乏，只要相较于现有技术，具有增强的崩溃防护电压即可。本发明的范围应涵盖上述及其它所有等效变化。The present invention has been described above with reference to preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, without affecting the main characteristics of the device, other process steps or structures can be added, such as deep well regions, etc.; as another example, lithography technology is not limited to photomask technology, and can also include electron beam lithography technology; The electric field simulation diagram shown is the simulation result of one of the embodiments, and it is not necessary to completely deplete the N-type well region but only partially deplete it, as long as it has an enhanced breakdown protection voltage compared with the prior art. The scope of the present invention is intended to cover the above and all other equivalent variations.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110219850.7ACN102903752B (en) | 2011-07-27 | 2011-07-27 | High voltage component and manufacturing method thereof |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110219850.7ACN102903752B (en) | 2011-07-27 | 2011-07-27 | High voltage component and manufacturing method thereof |
| Publication Number | Publication Date |
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| CN102903752A CN102903752A (en) | 2013-01-30 |
| CN102903752Btrue CN102903752B (en) | 2015-03-25 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201110219850.7AActiveCN102903752B (en) | 2011-07-27 | 2011-07-27 | High voltage component and manufacturing method thereof |
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| TWI613712B (en)* | 2016-12-23 | 2018-02-01 | 新唐科技股份有限公司 | Semiconductor device and method of manufacturing same |
| CN109473427B (en)* | 2017-09-08 | 2020-06-30 | 立锜科技股份有限公司 | High voltage component and method of making the same |
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| US20030038316A1 (en)* | 2001-08-23 | 2003-02-27 | Hideaki Tsuchiko | LDMOS field effect transistor with improved ruggedness in narrow curved areas |
| US6879003B1 (en)* | 2004-06-18 | 2005-04-12 | United Microelectronics Corp. | Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof |
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| US7768071B2 (en)* | 2008-07-09 | 2010-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stabilizing breakdown voltages by forming tunnels for ultra-high voltage devices |
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| US20030038316A1 (en)* | 2001-08-23 | 2003-02-27 | Hideaki Tsuchiko | LDMOS field effect transistor with improved ruggedness in narrow curved areas |
| US6879003B1 (en)* | 2004-06-18 | 2005-04-12 | United Microelectronics Corp. | Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof |
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| CN102903752A (en) | 2013-01-30 |
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