CN102891177B - Semiconductor device and manufacture method thereof - Google Patents

Abstract

The present invention relates to semiconductor device and manufacture method thereof.Described semiconductor device comprises: the laminated construction be patterned formed on a semiconductor substrate, and described laminated construction comprises Ge semiconductor layer, gate dielectric layer and grid layer from bottom to up successively; In the epitaxial semiconductor layer be doped of the both sides selective epitaxial growth of described Ge semiconductor layer, wherein, described epitaxial semiconductor layer forms the source and drain extension area of raising, and described Ge semiconductor layer is used as channel region.According to the present invention, the junction depth of source and drain extension area shallow (or thickness is little) advantageously can be made and doping content is high.Above-mentioned semiconductor device advantageously can improve carrier mobility.

Description

Semiconductor device and manufacture method thereof

Technical field

The present invention relates to semiconductor device and manufacture method thereof.The invention particularly relates to semiconductor device and the manufacture method thereof of the source and drain extension area with extension.

Background technology

Current, millions of semiconductor device is integrated to form very lagre scale integrated circuit (VLSIC).

Fig. 1 illustrates the sectional view of conventional semiconductor device (transistor).Transistor generally comprises the gate dielectric layer 140 in Semiconductor substrate (for the sake of clarity, not shown) and the grid layer 150 on gate dielectric layer 140 herein.The sidewall of gate dielectric layer 140 and grid layer 150 is formed with sidewall spacer 160 and 165.Transistor generally also comprises a pair source-drain area 110 of grid layer both sides 150.In addition, a pair source and drain extension area 120 is formed in the surf zone of Semiconductor substrate, and extends under gate dielectric layer 140 and grid layer 150.Channel region 130 is formed in the Semiconductor substrate between a pair source and drain extension area 120, under gate dielectric layer 140.

Along with the characteristic size of transistor constantly reduces, wish that the junction depth of source and drain extension area 120 shallow (or thickness is little) is to reduce junction capacitance (C_junc), and wish that the activation concentration of dopant of source and drain extension area 120 is high to reduce accumulation resistance (R_acc), thus increase the drive current of transistor.

In order to above-mentioned purpose, usually annealed in the source and drain extension area formed by ion implantation, the especially molten annealing in laser fusion/Asia.

But the present inventor, to this has been further investigation, finds that the junction depth of the source and drain extension area formed by the molten annealing of ion implantation and laser fusion/Asia and activation concentration of dopant need further to be improved.Incidentally, although usually use SIMS (secondary ion mass spectrometry) to measure laser fusion/Asia melt the dopant distribution after annealing, SIMS can not distinguish whether dopant is activated.

Therefore, the present inventor recognizes, needs a kind of junction depth of source and drain extension area shallow (or thickness is little) and activates the high semiconductor device of concentration of dopant and manufacture method thereof.

Summary of the invention

In view of above problem proposes the present invention.

An object of the present invention is to provide a kind of junction depth shallow (or thickness is little) of source and drain extension area and activate the high semiconductor device of concentration of dopant and manufacture method thereof.

According to a first aspect of the invention, a kind of semiconductor device is provided, it is characterized in that, described semiconductor device comprises: the laminated construction be patterned formed on a semiconductor substrate, and described laminated construction comprises Ge semiconductor layer, gate dielectric layer and grid layer from bottom to up successively; In the epitaxial semiconductor layer be doped of the both sides selective epitaxial growth of described Ge semiconductor layer, wherein, described epitaxial semiconductor layer forms the source and drain extension area of raising, and described Ge semiconductor layer is used as channel region.

Preferably, the doping content of described epitaxial semiconductor layer is 5.0 × 10¹⁹~ 5.0 × 10²¹cm^-3.

Preferably, the thickness of described epitaxial semiconductor layer is 5 ~ 50nm.

Preferably, described semiconductor device is PMOS transistor.

Preferably, described epitaxial semiconductor layer is Ge layer.

Preferably, described Ge semiconductor layer is relative to described gate dielectric layer by undercutting, and described Ge semiconductor layer is 10 ~ 20% of grid length by the length that undercutting is fallen.

Preferably, described gate dielectric layer and described grid layer are replaced by high-K gate dielectric layer and metal gate layers.

Preferably, described high-K gate dielectric layer is U-shaped, and described metal gate layers is surrounded by described high-K gate dielectric layer.

According to a second aspect of the invention, a kind of manufacture method of semiconductor device is provided, it is characterized in that, described manufacture method comprises the steps: to form the laminated construction be patterned on a semiconductor substrate, and described laminated construction comprises Ge semiconductor layer, gate dielectric layer and grid layer from bottom to up successively; In the epitaxial semiconductor layer that the both sides selective epitaxial growth of described Ge semiconductor layer is doped, to form the source and drain extension area of raising; And described gate dielectric layer and described grid layer are replaced with high-K gate dielectric layer and metal gate layers, and leave described Ge semiconductor layer as channel region.

Preferably, the doping content of described epitaxial semiconductor layer is 5.0 × 10¹⁹~ 5.0 × 10²¹cm^-3.

Preferably, the thickness of described epitaxial semiconductor layer is 5 ~ 50nm.

Preferably, described Ge semiconductor layer is SiGe layer, and the concentration of Ge is 30 ~ 40 atom %.

Preferably, described semiconductor device is PMOS transistor.

Preferably, described epitaxial semiconductor layer is Si layer.

Preferably, the condition of described selective epitaxial growth is as follows: H₂the flow of flow to be the flow in 10 ~ 50slm, Si source be 100 ~ 300sccm, HCl be 50 ~ 300sccm, AsH₃1%/H₂, B₂h₆1%/H₂or PH₃1%/H₂flow be 100 ~ 500sccm, temperature is 620 ~ 800 DEG C, and pressure be 0.1 ~ 1.0 holder.

Preferably, described manufacture method comprises the steps: further after forming described laminated construction and before the source and drain extension area of raising described in being formed, described Ge semiconductor layer is etched, with relative to Ge semiconductor layer described in described gate dielectric layer undercutting, wherein, described Ge semiconductor layer is 10 ~ 20% of grid length by the length that undercutting is fallen.

Preferably, described Ge semiconductor layer is SiGe layer, and the concentration of Ge is 30 ~ 40 atom %; And carry out described etching by HCl vapor phase etchant, wherein, use HCl and H₂mist, the dividing potential drop of HCl is 0.1 ~ 0.9 holder, and stagnation pressure is less than 80 holders, and temperature is 500 ~ 700 DEG C.

Preferably, described high-K gate dielectric layer is U-shaped, and described metal gate layers is surrounded by described high-K gate dielectric layer.

Preferably, described manufacture method comprises the steps:, after the source and drain extension area of raising described in being formed and before described gate dielectric layer and described grid layer are replaced with high-K gate dielectric layer and metal gate layers, to form source-drain area further.

According to the present invention, a kind of junction depth of source and drain extension area shallow (or thickness is little) can be provided and activate the high semiconductor device of concentration of dopant and manufacture method thereof.

Accompanying drawing explanation

To be contained in specification and the accompanying drawing forming its part illustrates embodiments of the invention, and together with the description for explaining principle of the present invention.

It should be noted that in the accompanying drawings, for convenience of description, the size of various piece may not be draw according to the proportionate relationship of reality.

Fig. 1 schematically shows the sectional view of conventional semiconductor device.

Fig. 2 schematically shows the flow chart of an embodiment of the manufacture method of semiconductor device according to the invention.

Fig. 3 A ~ 3F schematically shows the sectional view of each step in a described embodiment of the manufacture method of semiconductor device according to the invention.

From reference accompanying drawing to the following detailed description of exemplary embodiment, object of the present invention, feature and advantage will become obvious.

Embodiment

Describe exemplary embodiment of the present invention with reference to the accompanying drawings in detail.It should be noted that following being described in is only exemplary in essence.Unless stated otherwise, otherwise the parts of setting forth in an embodiment, step, numerical value etc. do not limit the scope of the invention.In addition, technology well known by persons skilled in the art, method and apparatus may not be discussed in detail, but are intended to the part becoming specification in appropriate circumstances.

Below will present invention is described for transistor.After having read the present invention, those skilled in the art can apply the present invention to any this place can be used to instruct the spirit of technical scheme and the occasion of essence in.

An embodiment of the manufacture method of semiconductor device of the present invention is described in detail below with reference to Fig. 2 and Fig. 3 A ~ 3F.Wherein, Fig. 2 schematically shows the flow chart of a described embodiment.Fig. 3 A ~ 3F schematically shows the sectional view of each step in a described embodiment.It should be noted that each step in Fig. 2 might not be all required, but according to circumstances can omit some step wherein.

First, in the step 210 of Fig. 2, Semiconductor substrate 300 forms the laminated construction be patterned, described laminated construction comprises Ge semiconductor layer 305, gate dielectric layer 340 and grid layer 350 (see Fig. 3 A) from bottom to up successively.

Semiconductor substrate 300 can be the substrate of any type known in the art, such as body silicon substrate, silicon-on-insulator (SOI) substrate etc.In addition, in Semiconductor substrate 300, such as can be formed with multiple area of isolation, such as shallow trench isolation is from (STI) region (not shown).

The thickness of Ge semiconductor layer 305 can be such as 5 ~ 50nm.In some embodiments of the invention, the thickness of Ge semiconductor layer 305 is less than 20nm, is even less than 10nm.

The material of gate dielectric layer 340 is not particularly limited, and it can be such as Si oxide or silicon nitride etc.

The material of grid layer 350 is not particularly limited, and it can be such as polysilicon etc.

Methods known in the art can be utilized to form described laminated construction by deposition, patterning and etching etc.

Next, in the step 220 of Fig. 2, Ge semiconductor layer 305 is etched, with the two ends (see Fig. 3 B) relative to gate dielectric layer 340 undercutting Ge semiconductor layer 305.

The object at the two ends of undercutting Ge semiconductor layer 305 makes the epitaxial semiconductor layer of formation and grid structure to be overlapped mutually below.Such as, the length at the two ends that Ge semiconductor layer 305 is fallen by undercutting can be identical, such as, be 5 ~ 10% of grid length.In other words, the total length at two ends that Ge semiconductor layer 305 is fallen by undercutting can be 10 ~ 20% of grid length.

Etching Ge semiconductor layer 305 can carry out under following process conditions: wherein, can use mol ratio be 3: 97 H₂o₂and H₂the mixture of O at room temperature etches, " DissolutionofGermaniuminAqueousHydrogenPeroxideSolution " that the details more specifically etched Ge semiconductor layer 305 can be delivered on JournaloftheElectrochemicalSociety see N.Cerniglia and P.Wang, vol.109, No.6 (1962) pp508-512; And " CharacterisationofThinSurfaceFilmsonGermaniuminVariousSo lventsbyEllipsometry " that the people such as M.F.EHMAN delivers on JournalofMaterialsScience, 6 (1971), pp969-973.

It should be noted that in some embodiments of the invention, also etching step 220 can not be performed.

Then, in the step 230 of Fig. 2, in the epitaxial semiconductor layer 320 that the both sides selective epitaxial growth of Ge semiconductor layer 305 is doped, to form the source and drain extension area (see Fig. 3 C) of raising.

Described selective epitaxial growth step is only carried out in the position that there is the germanium atom being used as " seed crystal ".Therefore, the epitaxial semiconductor layer 320 that is doped at the both sides selective epitaxial growth of Ge semiconductor layer 305 of described selective epitaxial growth step.The described epitaxial semiconductor layer 320 be doped will form the source and drain extension area of raising.In addition, described selective epitaxial growth step also simultaneously formation epitaxial semiconductor layer 325 (epitaxial semiconductor layer 325 can be removed in subsequent step) around grid layer 350.

In one embodiment, the material of epitaxial semiconductor layer 320 is heavily doped germanium.Following condition such as can be adopted to carry out selective epitaxial growth: quick hot CVD instrument can be used to carry out described selective epitaxial growth, wherein, H₂flow be 10 ~ 50SLM, be preferably 30SLM, as the GeH in Ge source₄flow be 100 ~ 300SCCM, alternatively, can also introduce HCl, its flow is such as 50 ~ 300SCCM, and mol ratio is the AsH of 1: 99₃and H₂mixture, mol ratio is the B of 1: 99₂h₆and H₂mixture or mol ratio be the PH of 1: 99₃and H₂mixture, flow is such as about 90SCCM, and temperature is about 400-600 DEG C, such as, be 500 DEG C, and pressure is about 0.05-1.0 holds in the palm, such as, be 0.07 holder.In one embodiment, B can be adopted₂h₆as dopant, doping content can be such as 5.0 × 10¹⁹~ 5.0 × 10²¹cm^-3.

Incidentally, in epitaxial growth steps 230, preferably the pre-heat treatment is not carried out.This is because the pre-heat treatment uses the temperature of hydrogen and more than 800 DEG C usually, even and the low-temperature prewarming process of 800 DEG C also introduces crystal defect by interface (such as near the STI) place such as between Si oxide and substrate.

Incidentally, due to the growth of native oxide, therefore the queuing time (queuetime) (time interval namely between etching step 220 and epitaxial growth steps 230) between etching step 220 and epitaxial growth steps 230 is preferably less than 2 hours, is more preferably less than 1 hour.

According to above process, define a kind of semiconductor device (see Fig. 3 C).Described semiconductor device comprises: the laminated construction be patterned formed in Semiconductor substrate 300, and described laminated construction comprises Ge semiconductor layer 305, gate dielectric layer 340 and grid layer 350 from bottom to up successively; And the epitaxial semiconductor layer 320 be doped of both sides selective epitaxial growth at Ge semiconductor layer 305.Wherein, as will be described below, epitaxial semiconductor layer 320 forms the source and drain extension area of raising, and Ge semiconductor layer 305 is used as channel region.

It should be noted that, compare with the prior art annealing to be formed source and drain extension area with by ion implantation, in the present invention, owing to being formed the epitaxial semiconductor layer 320 thus formation source and drain extension area that are doped by extension, therefore, the doping content of epitaxial semiconductor layer 320 (i.e. source and drain extension area) can higher (i.e. heavy doping), and such as, it can be 5.0 × 10¹⁹~ 5.0 × 10²¹cm^-3; Further, dopant can be activated largely, thus crystal defect is less.This can advantageously reduce to accumulate resistance, thus increases the drive current of transistor.

And, compare with the prior art annealing to be formed source and drain extension area with by ion implantation, in the present invention, owing to being formed the epitaxial semiconductor layer 320 thus formation source and drain extension area that are doped by extension, therefore, the thickness of epitaxial semiconductor layer 320 (i.e. source and drain extension area) can be less, and such as, it can be 5 ~ 50nm.In some embodiments of the invention, the thickness of epitaxial semiconductor layer 320 is less than 20nm, is even less than 10nm.This advantageously can reduce junction capacitance, thus improves the performance of transistor.

In addition, the molten annealing in laser fusion/Asia needs complicated technique adjustment, and the high temperature (such as, can reach more than 1300 DEG C) of the molten annealing in laser fusion/Asia may introduce defect at channel region place.By contrast, formed in the present invention of source and drain extension area by extension, due to the temperature of extension lower (such as, 620 ~ 800 DEG C), therefore less to the damage of channel region.

In addition, in the present invention, the source and drain extension area formed is positioned on the surface of Semiconductor substrate 300, and therefore formed source and drain extension area is the source and drain extension area of raising.The structure of this source and drain extension area of raising can reduce junction capacitance further, thus improves the performance of transistor further.

Incidentally, formed in the prior art of source and drain extension area by ion implantation and annealing, the dopant of injection not only can spread in the vertical, but also can adversely spread in the horizontal.By contrast, in the present invention, owing to can be controlled the length of source and drain extension area preferably by the undercutting amount of Ge semiconductor layer 305, be therefore conducive to reducing junction capacitance further.

After forming the source and drain extension area of raising, see Fig. 3 D, the sidewall spacer 360 and 365 of laminated construction, interlevel dielectric layer 370 and source-drain area (not shown) can be formed.

Material and the formation method of sidewall spacer 360,365 and interlevel dielectric layer 370 are not particularly limited.Such as, sidewall spacer 360,365 can be respectively silicon nitride and Si oxide, and, can by spreadability the good and ald that temperature is low (ALD) and being formed.Being formed after sidewall spacer 360,365 by depositing and etching, carrying out the deposition of interlevel dielectric layer 370, then carrying out chemico-mechanical polishing (CMP), to obtain the structure as Fig. 3 D.

Further, such as, can after formation sidewall spacer 360,365 and before formation interlevel dielectric layer 370, formation source-drain area (not shown).Source-drain area can be formed by the ion implantation of routine and annealing in process, also can form the source-drain area of other type of the source-drain area such as raised.

Next, in the step 240 of Fig. 2, gate dielectric layer 340 and grid layer 350 are replaced with high-K gate dielectric layer 344 and metal gate layers 355, and leave Ge semiconductor layer 305 as channel region (see Fig. 3 E ~ 3F).

First, remove grid layer 350 and gate dielectric layer 340 successively and leave Ge semiconductor layer 305, to form groove 375 (see Fig. 3 E).

The method removing grid layer 350 and gate dielectric layer 340 is not particularly limited.Such as, the various methods comprising dry ecthing and wet etching can be adopted optionally to etch away grid layer 350 and gate dielectric layer 340, thus form groove 375.In addition, the epitaxial semiconductor layer 325 formed around grid layer 350 is also etched.

Then, in groove 375, form high-K gate dielectric layer 344 and metal gate layers 355 (see Fig. 3 F) successively.

The material of high-K gate dielectric layer 344 is not particularly limited, and it can be such as HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, BST, BaTiO, SrTiO, YO, AlO, PbScTaO, PbZnNb etc.The thickness of high-K gate dielectric layer 344 is such as less thanas illustrated in Figure 3 F, the bottom of the high-K gate dielectric layer 344 formed not only covering groove 375, but also the sidewall of covering groove 375, that is, high-K gate dielectric layer 344 is essentially U-shaped.

Form the high-K gate dielectric layer 344 as backing layer (lininglayer) in groove 375 after, in groove 375, carry out deposition and planarization and form metal gate layers 355, thus the high-K gate dielectric layer 344 obtained as illustrated in Figure 3 F is U-shaped and metal gate layers 355 structure of being surrounded by high-K gate dielectric layer 344.The material of metal gate layers 355 is not particularly limited.Such as, for N-shaped metal gate layers 355, can use Hf, Zr, Ti, Ta, Al, HfC, ZrC, TiC, TaC, AlC etc., its work function is about 3.9 ~ 4.2eV, and its thickness is such asfor p-type metal gate layers 355, can use Ru, Pa, Pt, Co, Ni, RuO etc., its work function is about 4.9 ~ 5.2eV, and its thickness is such as

According to above process, define a kind of semiconductor device (see Fig. 3 F).In described semiconductor device, compared to the semiconductor device shown in Fig. 3 C and Fig. 3 D, gate dielectric layer 340 and grid layer 350 are replaced with high-K gate dielectric layer 344 and metal gate layers 355.

In the technique of rear high-k dielectrics post tensioned unbonded prestressed concrete of the present invention, after forming the epitaxial semiconductor layer 320 being used as source and drain extension area, gate dielectric layer 340 is replaced with high-K gate dielectric layer 344, thus avoid the deterioration of the high-K gate dielectric layer caused due to reducibility gas during epitaxial growth.By contrast, in the technique of the first grid of first high-k dielectrics, when utilizing epitaxy method to form source and drain extension area, due to the reproducibility reaction of the high-K gate dielectric layer that reducibility gas during epitaxial growth causes, therefore high-K gate dielectric layer is deteriorated.

It should be noted that in some embodiments of the invention, also replacement step 240 can not be performed.

So far, semiconductor device of the present invention and manufacture method thereof has been described in detail.In order to avoid covering design of the present invention, details more well known in the art are not described.Those skilled in the art, according to description above, can easily understand how to implement technical scheme disclosed herein.

Although describe the present invention with reference to exemplary embodiment, should be understood that and the invention is not restricted to disclosed exemplary embodiment.To those skilled in the art it is apparent that above exemplary embodiment can be revised under the condition not deviating from scope and spirit of the present invention.The scope of appended claim should be endowed the widest explanation, to comprise all such amendments and equivalent 26S Proteasome Structure and Function.

Claims (14)

1. a semiconductor device, is characterized in that, described semiconductor device comprises:

The laminated construction be patterned formed on a semiconductor substrate, described laminated construction comprises Ge semiconductor layer, gate dielectric layer and grid layer from bottom to up successively;

Utilize described Ge semiconductor layer as the epitaxial semiconductor layer that be doped of seed crystal at the both sides selective epitaxial growth of described Ge semiconductor layer, described in the epitaxial semiconductor layer that is doped be heavily doped Ge semiconductor layer;

Wherein, described epitaxial semiconductor layer forms the source and drain extension area of raising, and described Ge semiconductor layer is used as channel region;

Wherein, the two ends of described Ge semiconductor layer are relative to described gate dielectric layer by undercutting, and described Ge semiconductor layer is 10 ~ 20% of grid length by the total length that undercutting is fallen.

2. semiconductor device as claimed in claim 1, it is characterized in that, the doping content of described epitaxial semiconductor layer is 5.0 × 10¹⁹~ 5.0 × 10²¹cm^-3.

3. semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described epitaxial semiconductor layer is 5 ~ 50nm.

4. semiconductor device as claimed in claim 1, it is characterized in that, described semiconductor device is PMOS transistor.

5. as the semiconductor device in claim 1-4 as described in any one, it is characterized in that, described gate dielectric layer and described grid layer are replaced by high-K gate dielectric layer and metal gate layers.

6. semiconductor device as claimed in claim 5, it is characterized in that, described high-K gate dielectric layer is essentially U-shaped, and described metal gate layers is surrounded by described high-K gate dielectric layer.

7. a manufacture method for semiconductor device, is characterized in that, described manufacture method comprises the steps:

Form the laminated construction be patterned on a semiconductor substrate, described laminated construction comprises Ge semiconductor layer, gate dielectric layer and grid layer from bottom to up successively;

Etch described Ge semiconductor layer, with the two ends relative to Ge semiconductor layer described in described gate dielectric layer undercutting, wherein, described Ge semiconductor layer is 10 ~ 20% of grid length by the total length that undercutting is fallen;

Utilize described Ge semiconductor layer as seed crystal in the both sides of described Ge semiconductor layer the simultaneously epitaxial semiconductor layer that is doped of selective epitaxial growth, described in the epitaxial semiconductor layer that is doped be heavily doped Ge semiconductor layer, to form the source and drain extension area of raising; And

Described gate dielectric layer and described grid layer are replaced with high-K gate dielectric layer and metal gate layers, and leaves described Ge semiconductor layer as channel region.

8. manufacture method as claimed in claim 7, it is characterized in that, the doping content of described epitaxial semiconductor layer is 5.0 × 10¹⁹~ 5.0 × 10²¹cm^-3.

9. manufacture method as claimed in claim 7, it is characterized in that, the thickness of described epitaxial semiconductor layer is 5 ~ 50nm.

10. manufacture method as claimed in claim 7, it is characterized in that, described semiconductor device is PMOS transistor.

11. manufacture methods as claimed in claim 10, it is characterized in that, the condition of described selective epitaxial growth is as follows: H₂flow be 10 ~ 50SLM, GeH₄flow be 100 ~ 300SCCM, and mol ratio is the AsH of 1:99₃and H₂mixture, mol ratio is the B of 1:99₂h₆and H₂or mol ratio is the PH of 1:99₃and H₂the flow of mixture be about 90SCCM, temperature is about 500 DEG C, and pressure is about 0.07 holder.

12. manufacture methods as claimed in claim 7, is characterized in that,

Be the H of 3:97 by mol ratio₂o₂and H₂the mixture of O at room temperature etches described Ge semiconductor layer.

13., as the manufacture method in claim 7-12 as described in any one, is characterized in that, the step that described gate dielectric layer and described grid layer replace with high-K gate dielectric layer and metal gate layers are comprised the steps:

Form the sidewall spacer of described laminated construction;

Remove described grid layer and described gate dielectric layer, to form groove between described sidewall spacer;

Formed and cover the bottom of described groove and the high-K gate dielectric layer of sidewall; And

Form the metal gate layers of being surrounded by described high-K gate dielectric layer.

14. manufacture methods as claimed in claim 13, is characterized in that, described manufacture method comprises the steps: to form source-drain area immediately preceding after the described sidewall spacer of formation further.