CN102832209A - Capacitor array substrate - Google Patents

Abstract

A capacitor array substrate comprises a substrate, a plurality of first wires, a plurality of second wires, a plurality of capacitors, a plurality of connecting wires and a plurality of signal wires. The substrate has a first side, a second side and a third side. The first side is connected with the second side. The first side is connected with the third side. The first wirings are arranged on the substrate in parallel. Each first wire is not perpendicular or parallel to the first side. The second wirings are arranged on the substrate in parallel. The capacitor is arranged on the substrate, is positioned at the intersection of the first wire and the second wire, and is connected with the first wire and the second wire. The connecting lines are arranged on the second side and the third side of the substrate, and each connecting line is connected with one first wire and one second wire. The signal line is disposed on the substrate. Each signal line is connected with one first wire or one second wire and transmits signals from the first side.

Description

Translated fromChinese

电容阵列基板Capacitor Array Substrate

技术领域technical field

本发明涉及一种基板，尤其涉及一种电容阵列基板。The invention relates to a substrate, in particular to a capacitance array substrate.

背景技术Background technique

图1是一种现有电容阵列基板的示意图。请参照图1，在现有电容阵列基板100中，排成阵列的电容110是由水平方向的走线120与垂直方向的走线130连接。由于走线120与走线130分别平行于电容阵列基板100的两个侧边，若要在同一侧进行所有的信号传输，则需在电容阵列基板100的侧边布设用于走线120的信号线140。如此一来，就大幅增加了电容阵列基板100的侧边的宽度，不仅增加电容阵列基板100的成本，过长的信号线140也容易导致信号品质下降。FIG. 1 is a schematic diagram of a conventional capacitor array substrate. Referring to FIG. 1 , in a conventionalcapacitor array substrate 100 ,capacitors 110 arranged in an array are connected byhorizontal traces 120 andvertical traces 130 . Since thewiring 120 and thewiring 130 are respectively parallel to the two sides of thecapacitor array substrate 100, if all signal transmission is to be performed on the same side, the signal for thewiring 120 needs to be arranged on the side of thecapacitor array substrate 100.Line 140. In this way, the width of the side of thecapacitor array substrate 100 is greatly increased, which not only increases the cost of thecapacitor array substrate 100 , but also easily leads to signal quality degradation due to toolong signal lines 140 .

发明内容Contents of the invention

本发明提供一种电容阵列基板，具有精简的尺寸。The invention provides a capacitor array substrate with compact size.

本发明的电容阵列基板包括一基板、多条第一走线、多条第二走线、多个电容器、多条连接线以及多条信号线。基板具有一第一侧、一第二侧与一第三侧。第一侧连接第二侧。第一侧连接第三侧。第一走线互相平行地配置于基板。各第一走线不垂直也不平行第一侧。第二走线互相平行地配置于基板。电容器配置于基板，位于第一走线与第二走线的交会处，且连接第一走线与第二走线。连接线配置于基板的第二侧与第三侧，每条连接线连接一条第一走线与一条第二走线。信号线配置于基板。每条信号线连接一条第一走线或一条第二走线，并从第一侧传输信号。The capacitor array substrate of the present invention includes a substrate, a plurality of first wirings, a plurality of second wirings, a plurality of capacitors, a plurality of connection lines and a plurality of signal lines. The substrate has a first side, a second side and a third side. The first side connects to the second side. The first side connects to the third side. The first traces are arranged on the substrate parallel to each other. Each first trace is neither perpendicular nor parallel to the first side. The second wires are arranged parallel to each other on the substrate. The capacitor is arranged on the substrate, located at the intersection of the first wiring and the second wiring, and connected to the first wiring and the second wiring. The connecting wires are arranged on the second side and the third side of the substrate, and each connecting wire connects a first routing and a second routing. The signal line is configured on the substrate. Each signal line is connected to a first trace or a second trace, and transmits signals from the first side.

在本发明的一实施例中，第一走线垂直第二走线。In an embodiment of the present invention, the first trace is perpendicular to the second trace.

在本发明的一实施例中，第一走线与第一侧的夹角为45度。In an embodiment of the present invention, the angle between the first trace and the first side is 45 degrees.

在本发明的一实施例中，连接线未交会。In an embodiment of the invention, the connecting lines do not intersect.

在本发明的一实施例中，连接线相交会。In an embodiment of the present invention, the connecting lines intersect.

在本发明的一实施例中，第一侧垂直第二侧。In an embodiment of the invention, the first side is perpendicular to the second side.

基于上述，在本发明的电容阵列基板中，连接电容器的走线都倾斜于基板的侧边，再搭配连接线，即可缩小布线所需面积。Based on the above, in the capacitor array substrate of the present invention, the traces connecting the capacitors are all inclined to the side of the substrate, and the connecting wires are combined to reduce the area required for the wiring.

为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

附图说明Description of drawings

图1是一种现有电容阵列基板的示意图。FIG. 1 is a schematic diagram of a conventional capacitor array substrate.

图2是本发明一实施例的电容阵列基板的示意图。FIG. 2 is a schematic diagram of a capacitor array substrate according to an embodiment of the present invention.

图3是本发明另一实施例的电容阵列基板的示意图。FIG. 3 is a schematic diagram of a capacitor array substrate according to another embodiment of the present invention.

图4是本发明另一实施例的电容阵列基板的示意图。FIG. 4 is a schematic diagram of a capacitor array substrate according to another embodiment of the present invention.

图5是本发明另一实施例的电容阵列基板的示意图。FIG. 5 is a schematic diagram of a capacitor array substrate according to another embodiment of the present invention.

图6是本发明另一实施例的电容阵列基板的示意图。FIG. 6 is a schematic diagram of a capacitor array substrate according to another embodiment of the present invention.

附图标记：Reference signs:

100：电容阵列基板100: capacitor array substrate

110：电容110: capacitance

120、130：走线120, 130: wiring

140：信号线140: signal line

200、300、400、500、600：电容阵列基板200, 300, 400, 500, 600: capacitor array substrate

210、610：基板210, 610: Substrate

212、412、512、612：第一侧212, 412, 512, 612: first side

214、414、514：第二侧214, 414, 514: second side

216、416、516、616：第三侧216, 416, 516, 616: third side

220、320、620：第一走线220, 320, 620: the first routing

230、330、630：第二走线230, 330, 630: the second routing

240：电容器240: Capacitor

250、350、550：连接线250, 350, 550: connection line

260、360、660：信号线260, 360, 660: signal line

具体实施方式Detailed ways

图2是本发明一实施例的电容阵列基板的示意图。请参照图2，本实施例的电容阵列基板200包括一基板210、多条第一走线220、多条第二走线230、多个电容器240、多条连接线250以及多条信号线260。基板210具有一第一侧212、一第二侧214与一第三侧216。第一侧212连接第二侧214，而第一侧212也可垂直第二侧214。第一侧212连接第三侧216，但第一侧212可垂直或不垂直第三侧216。基板210通常呈矩形，但不限于此。各条第一走线220互相平行地配置于基板210，且各条第一走线220不垂直也不平行第一侧212。换言之，若第一侧212的边缘为水平的，则第一走线220不会呈垂直或水平状态。各条第二走线230互相平行地配置于基板210。FIG. 2 is a schematic diagram of a capacitor array substrate according to an embodiment of the present invention. Please refer to FIG. 2, thecapacitor array substrate 200 of this embodiment includes asubstrate 210, a plurality of first traces 220, a plurality ofsecond traces 230, a plurality ofcapacitors 240, a plurality ofconnection lines 250 and a plurality ofsignal lines 260 . Thesubstrate 210 has afirst side 212 , asecond side 214 and athird side 216 . Thefirst side 212 is connected to thesecond side 214 , and thefirst side 212 can also be perpendicular to thesecond side 214 . Thefirst side 212 is connected to thethird side 216 , but thefirst side 212 may or may not be perpendicular to thethird side 216 . Thesubstrate 210 is generally rectangular, but not limited thereto. The first traces 220 are arranged parallel to each other on thesubstrate 210 , and the first traces 220 are neither perpendicular nor parallel to thefirst side 212 . In other words, if the edge of thefirst side 212 is horizontal, the first trace 220 will not be vertical or horizontal. Thesecond traces 230 are arranged on thesubstrate 210 parallel to each other.

在此，“垂直”与“平行”都是指概略的状态，并不局限需非常精准，可容许因制程误差或刻意变化而造成的近似垂直与近似平行。Here, "perpendicular" and "parallel" both refer to a rough state, and are not limited to be very precise, and approximately vertical and approximately parallel due to process errors or deliberate changes can be tolerated.

电容器240配置于基板210。每个电容器240位于一条第一走线220与一条第二走线230的交会处，且连接一条第一走线220与一条第二走线230。连接线250配置于基板210的第二侧214与第三侧216。每条连接线250连接一条第一走线220与一条第二走线230。信号线260配置于基板210。每条信号线260连接一条第一走线220或一条第二走线230，并从第一侧212传输信号。Thecapacitor 240 is disposed on thesubstrate 210 . Eachcapacitor 240 is located at the intersection of a first wire 220 and asecond wire 230 , and connects a first wire 220 and asecond wire 230 . Theconnection wires 250 are disposed on thesecond side 214 and thethird side 216 of thesubstrate 210 . Eachconnection line 250 connects a first wiring 220 and asecond wiring 230 . Thesignal line 260 is disposed on thesubstrate 210 . Eachsignal line 260 is connected to a first wiring 220 or asecond wiring 230 and transmits signals from thefirst side 212 .

依据此配置方式，每个电容器240都可经由两条信号线260而被控制，每个电容器240的电容值变化也可由两条信号线260而被感知。而且，基板210的第二侧214与第三侧216只要保留少许空间就可供配置连接线250。因此，本实施例的电容阵列基板200在精简的尺寸下，就可达成单侧传输信号的目的，大幅降低了整体成本。另外，信号线260与连接线250的长度也可被控制在较短的状态，以提升信号的传输品质。According to this configuration, eachcapacitor 240 can be controlled via twosignal lines 260 , and the capacitance change of eachcapacitor 240 can also be sensed by twosignal lines 260 . Moreover, thesecond side 214 and thethird side 216 of thesubstrate 210 can be used for disposing the connectingwire 250 as long as a small space is reserved. Therefore, thecapacitive array substrate 200 of this embodiment can achieve the purpose of one-sided signal transmission with a reduced size, greatly reducing the overall cost. In addition, the lengths of thesignal wire 260 and theconnection wire 250 can also be controlled to be relatively short to improve signal transmission quality.

本实施例的第一走线220垂直第二走线230。此外，本实施例的第一走线220与第一侧212的夹角为45度。另外，本实施例的各条连接线250之间未交会，亦即各条连接线250是连接最靠近自己的第一走线220与第二走线230。The first wiring 220 in this embodiment is perpendicular to thesecond wiring 230 . In addition, the included angle between the first trace 220 and thefirst side 212 in this embodiment is 45 degrees. In addition, theconnection lines 250 in this embodiment do not intersect each other, that is, eachconnection line 250 is connected to the first routing 220 and thesecond routing 230 closest to itself.

图3是本发明另一实施例的电容阵列基板的示意图。请参照图3，本实施例的电容阵列基板300与图2的电容阵列基板200相似，差异在于本实施例的连接线350与其他连接线350相交会，甚至连接线350也可能与信号线360相交会。换言之，连接线350并非连接最靠近自己的第一走线320与第二走线330。这种设计方式可优化电容器阵列的电位分布，进而提升电容阵列基板300的效能。FIG. 3 is a schematic diagram of a capacitor array substrate according to another embodiment of the present invention. Please refer to FIG. 3, thecapacitance array substrate 300 of this embodiment is similar to thecapacitance array substrate 200 of FIG. Rendezvous. In other words, theconnection wire 350 is not connected to thefirst wire 320 and thesecond wire 330 closest to it. This design method can optimize the potential distribution of the capacitor array, thereby improving the performance of thecapacitor array substrate 300 .

图4是本发明另一实施例的电容阵列基板的示意图。请参照图4，本实施例的电容阵列基板400与图2的电容阵列基板200相似，差异在于本实施例的电容阵列基板400的第一侧412的长度大于第二侧414与第三侧416的长度。由本实施例可知，本发明也可应用在呈长方形的电容阵列基板400。FIG. 4 is a schematic diagram of a capacitor array substrate according to another embodiment of the present invention. Please refer to FIG. 4, thecapacitance array substrate 400 of this embodiment is similar to thecapacitance array substrate 200 of FIG. length. It can be seen from this embodiment that the present invention can also be applied to a rectangularcapacitor array substrate 400 .

图5是本发明另一实施例的电容阵列基板的示意图。请参照图5，本实施例的电容阵列基板500与图2的电容阵列基板200相似，差异在于本实施例的电容阵列基板500的第一侧512的长度小于第二侧514与第三侧516的长度。由本实施例可知，本发明也可应用在呈长方形且以短边为信号传输侧的电容阵列基板500。另外，在电容阵列基板500的第二侧514或第三侧516，也可取消部分靠近第一侧512的连接线550而取代为直接连接信号侧的信号线。FIG. 5 is a schematic diagram of a capacitor array substrate according to another embodiment of the present invention. Please refer to FIG. 5, thecapacitance array substrate 500 of this embodiment is similar to thecapacitance array substrate 200 of FIG. length. It can be known from this embodiment that the present invention can also be applied to acapacitor array substrate 500 that is rectangular and whose short side is the signal transmission side. In addition, on thesecond side 514 or thethird side 516 of thecapacitor array substrate 500 , part of theconnection wires 550 close to thefirst side 512 may also be eliminated and replaced with signal wires directly connected to the signal side.

图6是本发明另一实施例的电容阵列基板的示意图。请参照图6，本实施例的电容阵列基板600与图5的电容阵列基板500相似，差异在于本实施例的信号线660并不是仅连接最靠近第一侧612的第一走线620与第二走线630，位于第三侧616的部分信号线660会朝基板610内部延伸而连接基板610内部的第一走线620或第二走线630。FIG. 6 is a schematic diagram of a capacitor array substrate according to another embodiment of the present invention. Please refer to FIG. 6, thecapacitor array substrate 600 of this embodiment is similar to thecapacitor array substrate 500 of FIG. For thesecond trace 630 , a part of thesignal trace 660 located on thethird side 616 extends toward the inside of thesubstrate 610 to connect to thefirst trace 620 or thesecond trace 630 inside thesubstrate 610 .

综上所述，在本发明的电容阵列基板中，连接电容器的走线都倾斜于基板的侧边，易于由同一侧进行信号的传输。另外，再搭配连接线，即可在保有大尺寸的可工作面积下缩小布线所占面积，进而降低成本。To sum up, in the capacitor array substrate of the present invention, the wires connecting the capacitors are all inclined to the side of the substrate, and it is easy to transmit signals from the same side. In addition, with connecting wires, the area occupied by wiring can be reduced while maintaining a large workable area, thereby reducing costs.

虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域的普通技术人员，当可作些许更动与润饰，而不脱离本发明的精神和范围。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention, and any person of ordinary skill in the art may make some changes and modifications without departing from the spirit and scope of the present invention.

Claims (6)

1. capacitor array substrate comprises:

One substrate has one first side, one second side and one the 3rd side, and wherein this first side connects this second side, and this first side connects the 3rd side;

Many first cablings are disposed at this substrate parallel to each other, wherein also not parallel this first side of this first cabling out of plumb respectively;

Many second cablings are disposed at this substrate parallel to each other;

A plurality of capacitors are disposed at this substrate, are positioned at the confluce of those first cablings and those second cablings, and connect those first cablings and those second cablings;

Many connecting lines are disposed at this second side and the 3rd side of this substrate, connect one first cabling and one second cabling respectively; And

Many signal line are disposed at this substrate, connect one first cabling or one second cabling respectively, and from this first side transmission signals.

2. capacitor array substrate according to claim 1, wherein vertical those second cablings of those first cablings.

3. capacitor array substrate according to claim 1, wherein the angle of those first cablings and this first side is 45 degree.

4. capacitor array substrate according to claim 1, wherein not intersection of those connecting lines.

5. capacitor array substrate according to claim 1, wherein those connecting line phase intersections.

6. capacitor array substrate according to claim 1, wherein vertical this second side of this first side.

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