CN102780485B - Configurable D latch for chaos computing - Google Patents

Abstract

Translated fromChinese

本发明公开了一种可用于混沌计算的可配置D锁存器，包括二选一数据选通器，可配置逻辑门。二选一数据选通器：输入信号分别为第一输入信号、反馈信号，控制信号为选通信号，输出信号为选通后信号；可配置逻辑门：输入信号分别为选通后信号、第二输入信号，控制信号分别为控制信号Ctra、控制信号Ctrb,输出信号分别为输出信号Vout、输出信号NVout；可配置逻辑门的输出信号Vout为二选一数据选通器的输入信号即反馈信号。通过配置可配置逻辑门的两个控制信号及另一个输入信号，可以使这个D锁存器实现不同的功能，从而实现动态运算。

The invention discloses a configurable D latch which can be used for chaotic calculation, which includes a two-to-one data selector and a configurable logic gate. One-of-two data strobe: the input signal is the first input signal and the feedback signal respectively, the control signal is the strobe signal, and the output signal is the signal after strobe; configurable logic gate: the input signals are respectively the signal after strobe, the second signal after strobe Two input signals, the control signals are the control signal Ctra and the control signal Ctrb, and the output signals are the output signal Vout and the output signal NVout respectively; the output signal Vout of the configurable logic gate is the input signal of the two-choice data strobe, that is, the feedback signal . By configuring two control signals and another input signal of the configurable logic gate, the D latch can realize different functions, thereby realizing dynamic operation.

Description

Translated fromChinese

一种用于混沌计算的可配置D锁存器A Configurable D-Latch for Chaotic Computing

技术领域technical field

本发明涉及电子技术及动态运算领域，特别涉及一种用于混沌计算的可配置D锁存器。The invention relates to the field of electronic technology and dynamic calculation, in particular to a configurable D latch used for chaotic calculation.

背景技术Background technique

锁存器是一种对脉冲电平敏感的存储单元电路，它可以在特定的输入脉冲电平作用下改变状态。通常，脉冲电平只有高和低两个状态。当脉冲电平是高有效时，如果输入的脉冲电平是高，那么锁存器的输出就会跟随锁存器的输入而变化，如果输入的脉冲电平是低，那么锁存器的输出就会保持不变。相反，当脉冲电平是低有效时，如果输入的脉冲电平是低，那么锁存器的输出就会跟随锁存器的输入而变化，如果输入的脉冲电平是高，那么锁存器的输出就会保持不变。A latch is a memory cell circuit sensitive to pulse levels, which can change state under the action of a specific input pulse level. Usually, the pulse level has only two states, high and low. When the pulse level is high and effective, if the input pulse level is high, then the output of the latch will follow the input of the latch, if the input pulse level is low, then the output of the latch will remain unchanged. On the contrary, when the pulse level is low effective, if the input pulse level is low, then the output of the latch will follow the input of the latch and change, if the input pulse level is high, then the latch The output will remain unchanged.

锁存器是微处理器中运算器部分的主要模块，而D锁存器是其典型的逻辑电路。然而，传统的D锁存器本质上是静态的，它在运算过程中是不可以重新连线或者配置的。例如，8位D型锁存器这样的硬件元件，一旦制造成功，由于其电路结构无法重新连线或者配置，使其功能也无法改变。The latch is the main module of the arithmetic unit in the microprocessor, and the D latch is its typical logic circuit. However, traditional D-Latches are static in nature and cannot be rewired or configured during operation. For example, once a hardware component such as an 8-bit D-type latch is manufactured successfully, its function cannot be changed because its circuit structure cannot be rewired or configured.

随着电子技术及计算机技术的发展，现在的电子设计已经开始向动态运算领域发展。关于可重构的动态逻辑计算的研究是目前物理、通信、控制以及集成电路领域一个比较新的研究方向。With the development of electronic technology and computer technology, the current electronic design has begun to develop into the field of dynamic computing. Research on reconfigurable dynamic logic computing is a relatively new research direction in the fields of physics, communication, control and integrated circuits.

发明内容Contents of the invention

本发明为了克服现有技术存在的缺点，提供一种用于混沌计算的可配置D锁存器。本发明在不改变电路结构的条件下，通过对信号的不同配置，实现动态运算。In order to overcome the shortcomings of the prior art, the present invention provides a configurable D latch for chaotic calculation. The present invention realizes dynamic operation through different configurations of signals without changing the circuit structure.

本发明所采用的技术方案：The technical scheme adopted in the present invention:

一种用于混沌运算的可配置D锁存器，包括二选一数据选通器，可配置逻辑门；A configurable D-latch for chaotic operation, including a data selector for selecting one of two, and a configurable logic gate;

所述二选一数据选通器：输入信号分别为第一输入信号、反馈信号，控制信号为选通信号，输出信号为选通后信号；Said one-of-two data strobe: the input signal is respectively the first input signal and the feedback signal, the control signal is the strobe signal, and the output signal is the gated signal;

所述可配置逻辑门：输入信号分别为选通后信号、第二输入信号，控制信号分别为控制信号Ctra、控制信号Ctrb,输出信号分别为输出信号Vout、输出信号NVout；The configurable logic gate: the input signals are the gated signal and the second input signal respectively, the control signals are the control signal Ctra and the control signal Ctrb respectively, and the output signals are the output signal Vout and the output signal NVout respectively;

所述可配置逻辑门的输出信号Vout为二选一数据选通器的输入信号即反馈信号。The output signal Vout of the configurable logic gate is the input signal of the one-of-two data gate, that is, the feedback signal.

所述二选一数据选通器包括两个传输门和一个CMOS非门。The one-of-two data gate includes two transmission gates and a CMOS NOT gate.

所述可配置逻辑门包括一个CMOS与非门、一个CMOS或非门、三个CMOS非门、一个CMOS异或门、一个伪NMOS与或非门、一个伪NMOS与非门；The configurable logic gates include a CMOS NAND gate, a CMOS NOR gate, three CMOS NOT gates, a CMOS XOR gate, a pseudo NMOS NAND gate, and a pseudo NMOS NAND gate;

所述选通后信号、第二输入信号同时输入到CMOS与非门、CMOS或非门产生输出信号分别为输出信号Vnand、输出信号Vnor；The gated signal and the second input signal are simultaneously input to the CMOS NAND gate and the CMOS NOR gate to generate output signals respectively output signal Vnand and output signal Vnor;

控制信号Ctra、Ctrb分别经过CMOS非门产生输出信号NCtra、NCtrb；The control signals Ctra and Ctrb generate output signals NCtra and NCtrb respectively through the CMOS NOT gate;

将输出信号Vnand、Vnor、NCtrb和控制信号Ctra、Ctrb作为伪NMOS与或非门的输入信号，产生输出信号NX1；The output signal Vnand, Vnor, NCtrb and the control signal Ctra, Ctrb are used as the input signal of the pseudo-NMOS NOR gate to generate the output signal NX1;

将输出信号Vnor、NCtra和控制信号Ctrb作为伪NMOS与非门的输入信号，产生输出信号NX2；The output signal Vnor, NCtra and the control signal Ctrb are used as the input signal of the pseudo-NMOS NAND gate to generate the output signal NX2;

所述输出信号NX1、NX2经过CMOS异或门产生输出信号Vout,将输出信号Vout经过CMOS非门产生输出信号NVout。The output signals NX1 and NX2 pass through a CMOS XOR gate to generate an output signal Vout, and pass the output signal Vout through a CMOS NOT gate to generate an output signal NVout.

本发明的有益效果：在同一个硬件电路上，通过控制信号的不同组合，可以实现不同的逻辑功能，从而实现可动态配置的D锁存器，用于混沌计算等动态运算领域。Beneficial effects of the present invention: On the same hardware circuit, different logic functions can be realized through different combinations of control signals, thereby realizing a dynamically configurable D latch, which is used in dynamic computing fields such as chaotic computing.

附图说明Description of drawings

图1所示为一种用于混沌计算的可配置D锁存器；Figure 1 shows a configurable D-latch for chaotic computation;

图2所示为图1中可配置逻辑门的结构图；FIG. 2 is a structural diagram of the configurable logic gate in FIG. 1;

图3所示为图1中二选一数据选择器的结构图。FIG. 3 is a structural diagram of the one-of-two data selector in FIG. 1 .

具体实施方式Detailed ways

下面结合实施例及附图，对本发明作进一步地详细说明，但本发明的实施方式不限于此。The present invention will be described in further detail below in conjunction with the embodiments and the accompanying drawings, but the embodiments of the present invention are not limited thereto.

实施例Example

如图1所示为一种用于混沌计算的可配置D锁存器包括二选一数据选通器、可配置逻辑门；As shown in Figure 1, a configurable D-latch used for chaotic calculation includes a data selector and a configurable logic gate;

所述二选一数据选通器：输入信号分别为第一输入信号、反馈信号，控制信号为选通信号，输出信号为选通后信号；Said one-of-two data strobe: the input signal is respectively the first input signal and the feedback signal, the control signal is the strobe signal, and the output signal is the gated signal;

所述可配置逻辑门：输入信号分别为选通后信号、第二输入信号，控制信号分别为控制信号Ctra、控制信号Ctrb,输出信号分别为输出信号Vout、输出信号NVout；The configurable logic gate: the input signals are the gated signal and the second input signal respectively, the control signals are the control signal Ctra and the control signal Ctrb respectively, and the output signals are the output signal Vout and the output signal NVout respectively;

所述输出信号Vout为二选一数据选通器的输入信号即反馈信号。The output signal Vout is the input signal of the one-of-two data gate, that is, the feedback signal.

如图2所示为可配置逻辑门的结构图，Figure 2 is a structural diagram of a configurable logic gate,

所述可配置逻辑门包括一个CMOS与非门、一个CMOS或非门、三个CMOS非门、一个CMOS异或门、一个伪NMOS与或非门、一个伪NMOS与非门。The configurable logic gates include a CMOS NAND gate, a CMOS NOR gate, three CMOS NOT gates, a CMOS XOR gate, a pseudo NMOS NOR gate, and a pseudo NMOS NAND gate.

所述选通后信号、第二输入信号同时输入到CMOS与非门、CMOS或非门产生输出信号分别为输出信号Vnand、输出信号Vnor。The gated signal and the second input signal are simultaneously input to the CMOS NAND gate and the CMOS NOR gate to generate output signals respectively output signal Vnand and output signal Vnor.

控制信号Ctra、Ctrb分别经过CMOS非门产生输出信号NCtra、NCtrb。The control signals Ctra and Ctrb respectively pass through CMOS NOT gates to generate output signals NCtra and NCtrb.

将输出信号Vnand、Vnor、NCtrb和控制信号Ctra、Ctrb作为伪NMOS与或非门的输入信号，产生输出信号NX1。The output signals Vnand, Vnor, NCtrb and the control signals Ctra, Ctrb are used as input signals of the pseudo-NMOS NOR gate to generate the output signal NX1.

其中，$\mathrm{NX}1=\stackrel{\‾}{\mathrm{Ctrb}\·\mathrm{Vnand}+\mathrm{Ctra}\·\mathrm{Vnor}\·\mathrm{NCtrb}}$in,$\mathrm{NX}1=\stackrel{\‾}{\mathrm{Ctrl}\&Center\; Dot;\mathrm{Vnand}+\mathrm{Ctra}\&Center\; Dot;\mathrm{Vnor}\&Center\; Dot;\mathrm{NCtrb}}$

将输出信号Vnor、NCtra和控制信号Ctrb作为伪NMOS与非门的输入信号，产生输出信号NX2。The output signal Vnor, NCtra and the control signal Ctrb are used as input signals of the pseudo-NMOS NAND gate to generate the output signal NX2.

$\mathrm{<span><span>NX</span>NX</span>}\mathrm{<span><span>2</span>2</span>}<span><span>=</span>=</span>\stackrel{<span><span>\&OverBar;</span>\&OverBar;</span>}{\mathrm{<span><span>NCtra</span>NCtra</span>}<span><span>\&CenterDot;</span>\&Center\; Dot;</span>\mathrm{<span><span>Ctrb</span>Ctrl</span>}<span><span>\&CenterDot;</span>\&Center\; Dot;</span>\mathrm{<span><span>Vnor</span>Vnor</span>}}$

所述输出信号NX1、NX2经过CMOS异或门产生输出信号Vout,将输出信号Vout经过CMOS非门产生输出信号NVout。The output signals NX1 and NX2 pass through a CMOS XOR gate to generate an output signal Vout, and pass the output signal Vout through a CMOS NOT gate to generate an output signal NVout.

所述通过可配置逻辑门的两个控制信号的不同配置组合，使可配置逻辑门实现与、与非、或、或非、异或、同或、全高、全低等逻辑功能。The combination of different configurations of the two control signals of the configurable logic gate enables the configurable logic gate to realize logic functions such as AND, NAND, OR, NOR, exclusive OR, exclusive OR, all high, all low.

具体如下：details as follows:

当控制信号Ctra、Ctrb分别是逻辑低电压、逻辑低电压时，无论可配置逻辑门的输入信号如何，输出信号Vout为逻辑低电压，输出信号NVout为逻辑高电压；When the control signals Ctra and Ctrb are logic low voltage and logic low voltage respectively, regardless of the input signal of the configurable logic gate, the output signal Vout is a logic low voltage, and the output signal NVout is a logic high voltage;

当控制信号Ctra、Ctrb分别是逻辑低电压、逻辑高电压时，可配置逻辑门实现异或和同或功能，即When the control signals Ctra and Ctrb are logic low voltage and logic high voltage respectively, the logic gates can be configured to realize XOR and XOR functions, namely

当控制信号Ctra、Ctrb分别是逻辑高电压、逻辑低电压时，可配置逻辑门实现或非、或的功能，即When the control signals Ctra and Ctrb are logic high voltage and logic low voltage respectively, the logic gate can be configured to realize the function of NOR or OR, namely

NVout=选通后信号+第二输入信号NVout = signal after gating + second input signal

当控制信号Ctra、Ctrb分别是逻辑高电压、逻辑高电压时，可配置逻辑门实现与非、与的功能，即When the control signals Ctra and Ctrb are logic high voltage and logic high voltage respectively, the logic gate can be configured to realize the functions of NAND and AND, namely

NVout=选通后信号·第二输入信号NVout = signal after strobe second input signal

可配置逻辑门中起异或作用的CMOS异或体现了非线性特性，因为当异或门的两个输入信号分别是逻辑低电压、逻辑低电压或者逻辑高电压、逻辑高电压时，异或后结果是逻辑低电压，当异或门的两个输入分别是逻辑低电压、逻辑高电压或逻辑高电压、逻辑低电压，异或后结果是逻辑高电压，异或门输入信号和输出信号的关系就体现了非线性特性。The CMOS XOR that acts as an XOR in the configurable logic gate embodies nonlinear characteristics, because when the two input signals of the XOR gate are logic low voltage, logic low voltage or logic high voltage, logic high voltage, the XOR The final result is a logic low voltage. When the two inputs of the XOR gate are logic low voltage, logic high voltage or logic high voltage, logic low voltage, the XOR result is a logic high voltage, and the XOR gate input signal and output signal The relationship reflects the non-linear characteristics.

如图3所示为二选一数据选通器的结构图，二选一数据选通器包括两个传输门和一个CMOS非门。选通信号经过CMOS非门产生输出信号NSel。将反馈信号、选通信号、NSel信号作为传输门1的输入信号，同时将第一输入信号、选通信号、NSel信号作为传输门2的输入信号，产生选通后信号。FIG. 3 is a structural diagram of the one-of-two data strobe. The one-two data strobe includes two transmission gates and a CMOS NOT gate. The strobe signal passes through the CMOS NOT gate to generate the output signal NSel. The feedback signal, the strobe signal, and the NSel signal are used as the input signal of the transmission gate 1, and the first input signal, the strobe signal, and the NSel signal are used as the input signal of the transmission gate 2 to generate a gated signal.

当二选一数据选通器的选通信号为逻辑高电压时，二选一数据选通器输出第一输入信号，当选通信号为逻辑低电压时，二选一数据选通器输出反馈信号。When the strobe signal of the one-to-two data strobe is a logic high voltage, the one-to-two data strobe outputs the first input signal, and when the strobe signal is a logic low voltage, the one-to-two data strobe outputs a feedback signal .

当可配置逻辑门的控制信号Ctra、Ctrb分别设置为逻辑高电压、逻辑低电压时，可配置逻辑门实现或非、或的功能，此时将第二输入信号设置逻辑低电压，则本发明实现D锁存器的功能。When the control signals Ctra and Ctrb of the configurable logic gate are respectively set to a logic high voltage and a logic low voltage, the logic gate can be configured to realize the function of NOR and OR, and at this time, the second input signal is set to a logic low voltage, then the present invention Realize the function of D latch.

实现D锁存器的功能，所述当选通信号为逻辑高电压，D锁存器允许第一输入信号经过锁存器传到输出端；当选通信号为逻辑低电压，D锁存器阻止第一输入信号的传输。Realize the function of the D latch, when the strobe signal is a logic high voltage, the D latch allows the first input signal to pass through the latch to the output terminal; when the strobe signal is a logic low voltage, the D latch prevents the first input signal from Transmission of an input signal.

所述保持电路中第二输入信号为逻辑低电压且控制信号Ctra为逻辑高电压，当控制信号Ctrb由逻辑低电压变化为逻辑高电压时，电路对于NVout输出端实现清零功能，而对于Vout输出端实现置1功能。The second input signal in the holding circuit is a logic low voltage and the control signal Ctra is a logic high voltage. When the control signal Ctrb changes from a logic low voltage to a logic high voltage, the circuit realizes a clearing function for the NVout output terminal, and for Vout The output terminal realizes the function of setting to 1.

所述保持电路中控制信号Ctrb为逻辑低电压，将控制信号Ctra由逻辑高电压变化为逻辑低电压；或者保持电路中控制信号Ctra、Ctrb分别为逻辑高电压、逻辑低电压，将第二输入信号由逻辑低电压变化为逻辑高电压；均可实现电路对于NVout输出端实现置1功能，而对于Vout输出端实现清零功能。The control signal Ctrb in the holding circuit is a logic low voltage, and the control signal Ctra is changed from a logic high voltage to a logic low voltage; or the control signals Ctra and Ctrb in the holding circuit are respectively a logic high voltage and a logic low voltage, and the second input The signal changes from a logic low voltage to a logic high voltage; both of which can realize the function of setting the circuit to 1 for the NVout output terminal, and realize the clearing function for the Vout output terminal.

当可配置逻辑门的两个控制信号Ctra、Ctrb分别设置为逻辑高电压、逻辑高电压时，可配置逻辑门实现与非、与的功能，此时将第二输入信号设置为逻辑高电压时，则本发明实现D锁存器功能。When the two control signals Ctra and Ctrb of the configurable logic gate are set to logic high voltage and logic high voltage respectively, the configurable logic gate can realize the functions of NAND and AND. At this time, when the second input signal is set to logic high voltage , then the present invention realizes the D latch function.

实现D锁存器的功能，所述当选通信号为逻辑高电压时，D锁存器允许第一输入信号经过锁存器传到输出端，当选通信号为逻辑低电压时，D锁存器阻止第一输入信号的传输。Realize the function of the D latch. When the gate signal is a logic high voltage, the D latch allows the first input signal to pass through the latch to the output terminal. When the gate signal is a logic low voltage, the D latch Transmission of the first input signal is blocked.

所述保持电路中控制信号Ctra、Ctrb分别为逻辑高电压、逻辑高电压，将第二输入信号由逻辑高电压变化为逻辑低电压，电路对于NVout输出端实现清零功能，而对于Vout输出端实现置1功能。The control signals Ctra and Ctrb in the holding circuit are logic high voltage and logic high voltage respectively, and the second input signal is changed from logic high voltage to logic low voltage, and the circuit realizes the clearing function for the NVout output terminal, and for the Vout output terminal Realize set 1 function.

所述将控制信号Ctra、Ctrb同时由逻辑高电压变化为逻辑低电压；或者保持电路中控制信号Ctra为逻辑高电压且第二输入信号为逻辑高电压，将控制信号Ctrb由逻辑高电压变化为逻辑低电压；均可实现电路对于NVout输出端实现置1功能，而对于Vout输出端实现清零功能。The control signals Ctra and Ctrb are changed from a logic high voltage to a logic low voltage at the same time; or the control signal Ctra in the circuit is kept at a logic high voltage and the second input signal is a logic high voltage, and the control signal Ctrb is changed from a logic high voltage to Logical low voltage; both can realize the circuit to realize the setting function for the NVout output terminal, and realize the clearing function for the Vout output terminal.

上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受所述实施例的限制，其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the embodiment, and any other changes, modifications, substitutions and combinations made without departing from the spirit and principle of the present invention , simplification, all should be equivalent replacement methods, and are all included in the protection scope of the present invention.

Claims (2)

Translated fromChinese

1.一种用于混沌运算的可配置D锁存器，其特征在于，包括二选一数据选通器，可配置逻辑门；1. a kind of configurable D latch for chaotic operation, is characterized in that, comprises two to choose one data selector, configurable logic gate;所述二选一数据选通器：输入信号分别为第一输入信号、反馈信号，控制信号为选通信号，输出信号为选通后信号；Said one-of-two data strobe: the input signal is respectively the first input signal and the feedback signal, the control signal is the strobe signal, and the output signal is the gated signal;所述可配置逻辑门：输入信号分别为选通后信号、第二输入信号，控制信号分别为控制信号Ctra、控制信号Ctrb,输出信号分别为输出信号Vout、输出信号NVout；The configurable logic gate: the input signals are the gated signal and the second input signal respectively, the control signals are the control signal Ctra and the control signal Ctrb respectively, and the output signals are the output signal Vout and the output signal NVout respectively;所述可配置逻辑门的输出信号Vout为二选一数据选通器的输入信号即反馈信号；The output signal Vout of the configurable logic gate is the input signal of the one-of-two data strobe, that is, the feedback signal;所述可配置逻辑门包括一个CMOS与非门、一个CMOS或非门、三个CMOS非门、一个CMOS异或门、一个伪NMOS与或非门、一个伪NMOS与非门；The configurable logic gates include a CMOS NAND gate, a CMOS NOR gate, three CMOS NOT gates, a CMOS XOR gate, a pseudo NMOS NAND gate, and a pseudo NMOS NAND gate;所述选通后信号、第二输入信号同时输入到CMOS与非门、CMOS或非门产生输出信号分别为输出信号Vnand、输出信号Vnor；The gated signal and the second input signal are simultaneously input to the CMOS NAND gate and the CMOS NOR gate to generate output signals respectively output signal Vnand and output signal Vnor;控制信号Ctra、Ctrb分别经过CMOS非门产生输出信号NCtra、NCtrb；The control signals Ctra and Ctrb generate output signals NCtra and NCtrb respectively through the CMOS NOT gate;将输出信号Vnand、Vnor、NCtrb和控制信号Ctra、Ctrb作为伪NMOS与或非门的输入信号，产生输出信号NX1；The output signal Vnand, Vnor, NCtrb and the control signal Ctra, Ctrb are used as the input signal of the pseudo-NMOS NOR gate to generate the output signal NX1;将输出信号Vnor、NCtra和控制信号Ctrb作为伪NMOS与非门的输入信号，产生输出信号NX2；The output signal Vnor, NCtra and the control signal Ctrb are used as the input signal of the pseudo-NMOS NAND gate to generate the output signal NX2;所述输出信号NX1、NX2经过CMOS异或门产生输出信号Vout,将输出信号Vout经过CMOS非门产生输出信号NVout。The output signals NX1 and NX2 pass through a CMOS XOR gate to generate an output signal Vout, and pass the output signal Vout through a CMOS NOT gate to generate an output signal NVout.2.根据权利要求1所述的一种用于混沌运算的可配置D锁存器，其特征在于，所述二选一数据选通器包括两个传输门和一个CMOS非门。2. A kind of configurable D latch for chaotic operation according to claim 1, characterized in that, said one-of-two data gating device comprises two transmission gates and a CMOS NOT gate.