CN102779751A - Method for manufacturing semiconductor device - Google Patents

Abstract

Translated fromChinese

本申请公开了一种半导体器件的制造方法，包括：提供半导体衬底；在所述半导体衬底上形成栅堆叠，所述栅堆叠包括栅介质层和牺牲栅电极层，其中，所述栅介质层位于所述半导体衬底上，所述牺牲栅电极层位于所述栅介质层上；环绕所述栅堆叠形成侧墙；在所述栅堆叠两侧且嵌入所述半导体衬底形成源/漏区；在所述半导体衬底上形成SiO₂层，在所述SiO₂层上旋涂旋转涂布玻璃(SOG)，并进行平坦化至所述牺牲栅电极层露出；去除所述牺牲栅电极层以在所述侧墙内形成开口；在所述开口内形成替代栅电极。

The present application discloses a method for manufacturing a semiconductor device, including: providing a semiconductor substrate; forming a gate stack on the semiconductor substrate, the gate stack including a gate dielectric layer and a sacrificial gate electrode layer, wherein the gate dielectric layer is located on the semiconductor substrate, the sacrificial gate electrode layer is located on the gate dielectric layer; spacers are formed around the gate stack; sources/drains are formed on both sides of the gate stack and embedded in the semiconductor substrate region; form a_SiO2 layer on the semiconductor substrate, spin-coat spin-on-glass (SOG) on the_SiO2 layer, and planarize until the sacrificial gate electrode layer is exposed; remove the sacrificial gate electrode layer to form an opening in the spacer; and a replacement gate electrode in the opening.

Description

A kind of manufacturing approach of semiconductor device

Technical field

The present invention relates to the sub-micro technical field of semiconductor device; Relate in particular to the alternative gate preparation method of a kind of high-k gate dielectric/metal-gate structures semiconductor device; This method adopts sacrifices polygate electrodes as false gate electrode; Behind flatening process, remove and sacrifice the false gate electrode of polysilicon, form metal gate electrode.

Background technology

Over more than 40 year, integrated circuit technique is by the sustainable development of mole law, and characteristic size is constantly dwindled, and integrated level improves constantly, and function is more and more stronger.At present, the characteristic size of mos field effect transistor (MOSFET) has got into inferior 50 nanometers.Follow constantly reducing of device feature size; If still adopt traditional polysilicon gate, the depletion of polysilicon effect will be more and more serious, and polysilicon resistance also will increase thereupon; The boron punch through of PMOS can be more remarkable, and these obstacles are with the further raising of serious limiting device performance.In order to overcome above difficulty, industrial quarters begins to adopt high-k (high k) gate dielectric/metal gate structure to replace traditional silica/polysilicon grating structure.

In the preparation of high-k gate dielectric/metal gate semiconductor device; If still adopt the preparation technology similar with the standard CMOS process flow process; Preparation source/leakage behind i.e. elder generation's preparation metal gate electrode; Though technology is simple, compatible mutually with standard CMOS process, and some technologies commonly used formerly also can adopt in the grid technique in the standard CMOS process; Help saving cost, but there are some shortcomings that are difficult to overcome in this method: at first be that the ion penetration that metal gate electrode is injected into source/leakage easily influences electric properties of devices; Next is that the high-temperature technology of activation of source/leakage impurity has very big influence to the work function of metal gate, and most of metal gate material its work function after The high temperature anneal can cause the degeneration of device performance to the forbidden band central mobile.

Summary of the invention

Main purpose of the present invention is to provide a kind of manufacturing approach of semiconductor device, and this method comprises: Semiconductor substrate is provided; On said Semiconductor substrate, form grid and pile up, said grid pile up and comprise gate dielectric layer and sacrificial gate dielectric layer, and wherein, said gate dielectric layer is positioned on the said Semiconductor substrate, and said sacrificial gate dielectric layer is positioned on the said gate dielectric layer; Pile up the formation side wall around said grid; Pile up both sides and embed said Semiconductor substrate formation source/drain region at said grid; On said Semiconductor substrate, form SiO₂Layer is at said SiO₂Spin coating SOG on the layer (Spin On Glass, rotary coating glass medium layer), and be planarized to said sacrificial gate dielectric layer and expose; Remove said sacrificial gate dielectric layer in said side wall, to form opening; In said opening, form the alternative gate electrode.

Manufacturing approach according to this semiconductor device provided by the invention; Form high-k gate dielectric/false gate electrode structure earlier; Behind completion source/leakage injection and activation technology, remove false gate electrode through planarization, form the grid groove; Again depositing metal grid are accomplished the preparation of high-k gate dielectric/metal gate semiconductor device then.The advantage of this back grid technique is that metal gate electrode forms after source/leakage activation heat annealing process; Avoided the influence of high-temperature technology to the metal gate characteristic; Make device obtain very high stability and consistency, help forming high performance high-k gate dielectric/metal gate semiconductor device and circuit.

According to embodiments of the invention, adopt SiO₂+ SOG technology realizes planarization.For example, at first, adopt LTO technology to form SiO₂Dielectric layer can be realized preliminary planarization, reduce that grid pile up and source/leakage between difference in height; Then, adopt SOG further to carry out planarization.Liquid SOG has good planarization effect, can effectively fill and reduce grid pile up and source/leakage between difference in height, reach desirable planarization effect.After solidifying, SOG annealing can form SiO₂Dielectric layer is with the SiO of LTO formation₂Dielectric layer is compatible mutually, helps later stage employing dry etch process and obtains desirable planarization effect.

Based on embodiments of the invention, adopt TMAH to remove the false gate process of polysilicon.For example, at first, adopt HF acid to remove the oxide layer at the false gate electrode of polysilicon top; Then, adopt the TMAH wet corrosion technique to remove the remaining polysilicon gate electrode.

Description of drawings

With reference to the description of accompanying drawing to the embodiment of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be more clear through following, in the accompanying drawings:

Fig. 1-10 shows the sectional view of the device architecture that obtains according to each step in the flow process of embodiment of the invention manufacturing semiconductor device;

Figure 11 and 12 shows the electrology characteristic according to the HfSiON/TaN/W high-k gate dielectric layer/work function layer/metal gate conductor structure nMOSFET of embodiment of the invention preparation;

Figure 13 and 14 shows the HfSiAlON/AlN according to embodiment of the invention preparation_xThe electrology characteristic of the pMOSFET of/Mo high-k gate dielectric layer/work function layer/metal gate conductor structure.

Description of reference numerals:

1000 Semiconductor substrate;

1001 channel regions;

1002 high-k gate dielectric layers;

1004 sacrificial gate dielectric layer;

1006 hard mask layer (SiO₂);

1,008 first side wall (Si₃N₄);

1009 source drain extension regions;

1,010 second side wall (SiO₂);

1012 sources/drain region;

1014 metal silicides;

1016SiO₂Dielectric layer;

1018 rotary coating glass (SOG);

1022 workfunction metal gate electrode layers;

1024 metal gate conductor layers;

1026 isolate (LOCOS).

Embodiment

Below, through the specific embodiment shown in the accompanying drawing the present invention is described.But should be appreciated that these descriptions are exemplary, and do not really want to limit scope of the present invention.In addition, in the following description, omitted description, to avoid unnecessarily obscuring notion of the present invention to known features and technology.

Layer structural representation according to the embodiment of the invention shown in the drawings.These figure draw in proportion, wherein for purpose clearly, have amplified some details, and possibly omit some details.The shape of the various zones shown in the figure, layer and the relative size between them, position relation only are exemplary; Maybe be because manufacturing tolerance or technical limitations and deviation to some extent in the reality, and those skilled in the art according to reality required can design in addition have difformity, the regions/layers of size, relative position.

Fig. 1～10 show in detail the sectional view of making the device architecture that each step obtains in the semiconductor device flow process according to the embodiment of the invention.Below, will come each step based on the embodiment of the invention is described in detail with reference to these accompanying drawings.

At first, as shown in Figure 1,Semiconductor substrate 1000 is provided.Substrate 1000 can comprise any suitable semiconductor substrate materials, specifically can be but is not limited to silicon, germanium, SiGe, SOI (semiconductor-on-insulator), carborundum, GaAs or any III/V compound semiconductor etc.In addition,Semiconductor substrate 1000 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen the property.

OnSemiconductor substrate 1000, can be formed withisolation structure 1026, preferably adopt carrying out local oxide isolation (Local Oxidation of Silicon, LOCOS).Also can adopt other isolation structures in an embodiment of the present invention, isolation structure and purport of the present invention are irrelevant, repeat no more here.

Then, onSemiconductor substrate 1000, forming grid piles up.

For this reason, for example as shown in Figure 2, onSemiconductor substrate 1000, form high-k gate dielectric layer 1002.Particularly, canSemiconductor substrate 1000 be cleaned, for example adopt HF+IPA+H₂O removes natural oxidizing layer.Then, preferably, can adopt rapid thermal anneal processsubstrate surface form 5 to

SiO₂(this layer is very thin, therefore among the figure this SiO is not shown clearly for boundary layer₂And adopt magnetron sputtering technique boundary layer), at SiO₂Deposit high-k gate dielectric on the boundary layer.For example, for nMOSFET, can deposit HfSiON high-k gate dielectric; For pMOSFET, can deposit HfSiAlON high-k gate dielectric.Then, high-k gate dielectric is carried out quick thermal annealing process, annealing temperature is 700 ℃ to 900 ℃, thereby forms high-k gatedielectric layer 1002.

Then, on high-k gatedielectric layer 1002, forming sacrificial gatedielectric layer 1004, for example can be polysilicon layer.Particularly, can adopt LPCVD (Low-Pressure Chemical Vapor Deposition, low-pressure chemical vapor phase deposition) mode to form the sacrifice polysilicon layer, the thickness of sacrificing polysilicon layer can be 150nm to 190nm.

Then, on sacrificial gatedielectric layer 1004, continuing to formhard mask layer 1006, for example can be SiO₂Layer.Particularly, can adopt LTO (Low-temperature oxidation, low-temperature oxidation) mode to form SiO₂Hard mask layer, SiO₂Hard mask layer thickness can be 40-70nm.At this, the selection of thickness is decided according to the etching of back polysilicon gate and side wall, requires after the etching of piling up through grid with side wall SiO₂Hard mask layer thickness need remain 10-20nm, to prevent that sacrificing the polysilicon layer top forms silicide.

Then, as shown in Figure 3, the grid structure is carried out the patterning etching.Particularly, anti-etching dose of spin coating, the antagonism etching agent carries out patterning, is shelter etching SiO with anti-etching dose₂Hard mask layer 1006 is removed anti-etching dose, then with SiO₂Hard mask layer is shelteretching polysilicon layer 1004 and high-k gatedielectric layer 1002, piles up thereby form grid.

Then, shown in Figure 4 and 5, pile up both sides at grid and pile up the formation sidewall structure around grid.According to embodiments of the invention, can form double-deck sidewall structure or three layers of sidewall structure.

For example, at first as shown in Figure 4, pile up both sides at grid and pile up formationfirst side wall 1008, the for example Si around grid₃N₄Side wall.Particularly, can adopt PECVD (Plasma-Enhanced Chemical Vapor Deposition, plasma-reinforced chemical vapor deposition) mode to form one deck Si₃N₄Layer, thickness can be 50-90nm, adopts dry etch process then, for example is the Si of RIE (Reactive-Ion Etching, reactive ion etching) to deposit₃N₄Layer carries out etching, only keeps it and is positioned at grid and piles up the part on the sidewall, to form Si₃N₄Side wall.After formingfirst side wall 1008, can adopt ion to inject formation source/drain extension region 1009.For example, for nMOSFET, can inject As or Sb; For pMOSFET, can inject BF₂Or In.

Then, as shown in Figure 5, formsecond side wall 1010, the for example SiO at first side wall, 1008 outer rings aroundfirst side wall 1008₂Side wall.Particularly, can adopt the LTO mode to form one deck SiO₂Layer, thickness can be 80-120nm, adopts the SiO of dry etch process to forming then₂Layer carries out etching, only keeps it and is positioned at the part on first side wall, 1008 sidewalls, to form SiO₂Side wall.After formingsecond side wall 1010, can adopt ion to inject and form source-drain area 1012.For example, for nMOSFET, can inject As or Sb; For pMOSFET, can inject BF₂Or In.

According to other embodiments of the invention, can also outsidesecond side wall 1010, further form the 3rd side wall, the material of the 3rd side wall preferably includes Si₃N₄The 3rd side wall is not shown among the figure.

Then, can on source-drain area, form silicide 1014.Based on embodiments of the invention, silicide can be selected the Ni silicide.

Then, as shown in Figure 6, be formed with formationdielectric layer 1016, for example SiO on the Semiconductor substrate of device architecture shown in Figure 5₂According to embodiments of the invention, can adopt the LTO mode to form SiO₂Dielectric layer, SiO₂Thickness of dielectric layers 600 to 800nm.

Then, spin coating rotary coating glass (SOG) 1018.Liquid state SOG can fill the sunk part of wafer surface, reaches the purpose of device surface planarization.Can solidify SOG annealing then, form SiO after making the solvent evaporates among the SOG₂Layer.

Then, as shown in Figure 7, to SiO₂Dielectric layer 1016 carries out further planarization with SOG layer 1018, to expose altered sacrificial gate electrode, handles so that carry out alternative gate subsequently.Particularly, for example can adopt dry etch process etching SOG 1018 to SOG and SiO₂Dielectric layer 1016 at the interface.Then, according to SOG and SiO₂The etch rate ratio is 1: 1.2 to 1: 2 dry etching SOG and SiO₂Dielectric layer to altered sacrificial gate electrode is exposed, at this moment, and at source-drain area residue SiO₂Thickness of dielectric layers is 50nm to 150nm.

Then, as shown in Figure 8, remove and sacrifice polygate electrodes.For example, can adopt diluted hydrofluoric acid (volume ratio HF: H₂O=1: 50～1: 10) solution corrosion is sacrificed the residual oxide layer at polygate electrodes top; Then, (Tetramethy ammoniumhydroxide, TMAH) solution corrosion is sacrificed polygate electrodes, in side wall, forms opening to adopt the tetramethyl aqua ammonia.Preferably, the concentration of TMAH solution is 5%-20% (volume ratio), and temperature is 50-80 ℃.

Then, as shown in Figure 9, in the side wall opening, form metal gate.Particularly, on high-k gate dielectric 1002, form workfunction metal gate electrode layer 1022.For example, for nMOSFET, can be the TaN metal gate electrode layer; For pMOSFET, can be AlN_xMetal gate electrode layer.Depositing metalgrid conductor layer 1024 on workfunction metal gate electrode layer 1022.For example, for nMOSFET, can be W metal gate conductor layer; For pMOSFET, can be Mo metal gate conductor layer.

Then, shown in figure 10, metalgate conductor layer 1024 and workfunction metal gate electrode layer 1022 are carried out patterning, to form final grid structure.Particularly, for example anti-etching dose of spin coating on metalgate conductor layer 1024, the antagonism etching agent carries out patterning, and using plasma dry etching metalgate conductor layer 1024 and workfunction metal gate electrode layer 1022 then are to form metal-gate structures.At this, preferably anti-etching dose of patterning will cover side wall open outer side 0.5 to 4 μ m, thereby forms T type metal gates structure.

In addition, for accomplishing entire device, formation electrically contacts with source/drain region.For example, photolithographic source/leakage through hole, to wherein filling the Ti/TiN/Al interconnect metallization lines, patterned etching forms source drain contact portion (not shown).

In above description, do not make detailed explanation for ins and outs such as the composition of each layer, etchings.Can be but it will be appreciated by those skilled in the art that through various means of the prior art, form layer, zone of required form etc.In addition, in order to form same structure, those skilled in the art can also design and the not identical method of the method for above description.

It shown in Figure 11 and 12 electrology characteristic that adopts the HfSiON/TaN/W high-k gate dielectric layer/work function layer/metal gate conductor structure nMOSFET of the present invention's preparation.The threshold voltage of this example device is 0.24V, and saturation current is 1.17 * 10^-4A/ μ m (| V_GS|=| V_DS|=1.5V).

Shown in Figure 13 and 14 the HfSiAlON/AlN that adopts the present invention's preparation_xThe electrology characteristic of the pMOSFET of/Mo high-k gate dielectric layer/work function layer/metal gate conductor structure.The threshold voltage of this example device is-1.29V that saturation current is 1.38 * 10^-4A/ μ m (| V_GS|=| V_DS|=2.5V).

The manufacturing approach of this semiconductor device provided by the invention adopts sacrifices polygate electrodes as false gate electrode, effectively avoids the influence of first grid technique high-temperature annealing process to high-k gate dielectric/metal-gate structures electrology characteristic.On concrete preparation technology, below can adopting in the multinomial technology one or multinomial, comprising to improve device performance:

-adopt double-deck sidewall structure (like Si₃N₄/ SiO₂) or three layers of sidewall structure (like Si₃N₄/ SiO₂/ Si₃N₄)

For example, adopting Si near metal gate one side₃N₄First side wall can prevent effectively that high-k gate dielectric and metal gate are oxidized, avoids the increase of high-k gate dielectric equivalent oxide thickness and the degeneration of metal gate characteristic.

-employing SiO₂+ SOG flatening process

At first, form SiO₂Dielectric layer (for example, adopt LTO technology) can be realized preliminary planarization, reduce that grid pile up and source/leakage between difference in height; Then, adopt SOG further to carry out planarization.Liquid SOG has good planarization effect, can effectively fill and reduce grid pile up and source/leakage between difference in height, reach desirable planarization effect.After solidifying, SOG annealing can form SiO₂Dielectric layer is with the SiO of LTO formation₂Dielectric layer is compatible mutually, helps later stage employing dry etch process and obtains desirable planarization effect.

-adopt the TMAH wet corrosion technique to help improving the selection ratio of sacrifice polysilicon gate to high-k gate dielectric

Because TMAH has very high selection ratio for oxide layer and polysilicon; Extremely thin oxide layer promptly can stop the corrosion of TMAH to polysilicon; Therefore; Before the TMAH wet corrosion technique, adopt hydrofluoric acid solution to remove the residual oxide layer at sacrifice polysilicon gate top or the oxide layer that forms naturally, to reduce the influence of oxide layer to the TMAH wet corrosion technique.

Abovely the present invention has been given explanation with reference to embodiments of the invention.But these embodiment only are for illustrative purposes, and are not in order to limit scope of the present invention.Scope of the present invention is limited accompanying claims and equivalent thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.

Claims (13)

Translated fromChinese

1.一种半导体器件的制造方法，包括：1. A method of manufacturing a semiconductor device, comprising:提供半导体衬底；Provide semiconductor substrates;在所述半导体衬底上形成栅堆叠，所述栅堆叠包括栅介质层和牺牲栅电极层，其中，所述栅介质层位于所述半导体衬底上，所述牺牲栅电极层位于所述栅介质层上；A gate stack is formed on the semiconductor substrate, and the gate stack includes a gate dielectric layer and a sacrificial gate electrode layer, wherein the gate dielectric layer is located on the semiconductor substrate, and the sacrificial gate electrode layer is located on the gate on the medium layer;环绕所述栅堆叠形成侧墙；forming sidewalls around the gate stack;在所述栅堆叠两侧且嵌入所述半导体衬底形成源/漏区；forming source/drain regions on both sides of the gate stack and embedded in the semiconductor substrate;在所述半导体衬底上形成SiO₂层，在所述SiO₂层上旋涂旋转涂布玻璃SOG层，并进行平坦化至所述牺牲栅电极层露出；Forming a_SiO2 layer on the semiconductor substrate, spin-coating a spin-coated glass SOG layer on the_SiO2 layer, and performing planarization until the sacrificial gate electrode layer is exposed;去除所述牺牲栅电极层以在所述侧墙内形成开口；removing the sacrificial gate electrode layer to form openings in the sidewalls;在所述开口内形成替代栅电极。A replacement gate electrode is formed within the opening.2.根据权利要求1所述的方法，其中，在所述半导体衬底上形成栅堆叠的步骤包括：2. The method according to claim 1, wherein the step of forming a gate stack on the semiconductor substrate comprises:在所述半导体衬底上依次形成栅介质层、牺牲栅电极层和硬掩模层；sequentially forming a gate dielectric layer, a sacrificial gate electrode layer and a hard mask layer on the semiconductor substrate;对硬掩膜层进行图案化，形成栅图案；patterning the hard mask layer to form a gate pattern;以硬掩膜层为掩蔽对所述牺牲栅电极层和栅介质层进行刻蚀，以形成栅堆叠。The sacrificial gate electrode layer and the gate dielectric layer are etched using the hard mask layer as a mask to form a gate stack.3.根据权利要求1或2所述的方法，其中，所述栅介质层包括高k栅介质层。3. The method according to claim 1 or 2, wherein the gate dielectric layer comprises a high-k gate dielectric layer.4.根据权利要求1所述的方法，其中，所述牺牲栅电极层包括多晶硅栅电极层。4. The method of claim 1, wherein the sacrificial gate electrode layer comprises a polysilicon gate electrode layer.5.根据权利要求1所述的方法，其中，环绕所述栅堆叠形成侧墙的步骤包括：5. The method of claim 1, wherein forming a spacer around the gate stack comprises:环绕所述栅堆叠形成Si₃N₄侧墙。Si₃ N₄ spacers are formed around the gate stack.6.根据权利要求1所述的方法，其中，环绕所述栅堆叠形成侧墙的步骤包括：6. The method of claim 1, wherein forming spacers around the gate stack comprises:环绕所述栅堆叠形成第一侧墙，且环绕所述第一侧墙形成第二侧墙；forming a first sidewall around the gate stack, and forming a second sidewall around the first sidewall;其中所述第一侧墙由Si₃N₄形成，所述第二侧墙由SiO₂形成。Wherein the first sidewall is formed of Si₃ N₄ , and the second sidewall is formed of SiO₂ .7.根据权利要求6所述的方法，其中，环绕所述第一侧墙形成第二侧墙的步骤包括：7. The method of claim 6, wherein forming a second side wall around the first side wall comprises:在所述半导体衬底上采用低温氧化方式形成SiO₂层；Forming a_SiO2 layer on the semiconductor substrate by low-temperature oxidation;对所述SiO₂层图案化，以形成环绕第一侧墙的第二侧墙。The_SiO2 layer is patterned to form second sidewalls surrounding the first sidewalls.8.根据权利要求6所述的方法，其中，环绕所述栅堆叠形成侧墙的步骤进一步包括：8. The method of claim 6, wherein the step of forming spacers around the gate stack further comprises:环绕所述第二侧墙形成第三侧墙；forming a third side wall surrounding the second side wall;其中所述第三侧墙由Si₃N₄形成。Wherein the third side wall is formed of Si₃ N₄ .9.根据权利要求1所述的方法，其中，所述在所述半导体衬底上形成SiO₂层的步骤包括：9. The method according to claim 1, wherein the step of forming a_SiO2 layer on the semiconductor substrate comprises:采用低温氧化在所述半导体衬底上形成SiO₂层。A_SiO2 layer is formed on the semiconductor substrate using low temperature oxidation.10.根据权利要求1所述的方法，其中，在所述SiO₂层上旋涂SOG之后，所述方法进一步包括：10. The method of claim 1, wherein, after spin-coating SOG on the_SiO2 layer, the method further comprises:对SOG进行退火固化。The SOG is annealed and cured.11.根据权利要求4所述的方法，其中，所述去除牺牲栅电极层以在所述侧墙内形成开口的步骤包括：采用四甲基氢氧化氨TMAH湿法腐蚀牺牲栅电极层。11 . The method according to claim 4 , wherein the step of removing the sacrificial gate electrode layer to form an opening in the sidewall comprises: wet etching the sacrificial gate electrode layer with tetramethyl ammonium hydroxide (TMAH).12.根据权利要求11所述的方法，其中，所述采用TMAH湿法腐蚀牺牲栅电极层之前，所述方法进一步包括：采用氢氟酸湿法腐蚀去除牺牲栅电极层顶层的氧化层。12 . The method according to claim 11 , wherein before the wet etching of the sacrificial gate electrode layer using TMAH, the method further comprises: removing the oxide layer on the top layer of the sacrificial gate electrode layer by hydrofluoric acid wet etching. 13 .13.根据权利要求1所述的方法，其中，所述在所述开口内形成替代栅电极的步骤包括：在所述开口内形成金属栅电极。13. The method of claim 1, wherein the step of forming a replacement gate electrode in the opening comprises forming a metal gate electrode in the opening.

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