技术领域technical field
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.
背景技术Background technique
平板显示器是目前主流的显示器，其包括有源矩阵有机发光二极管显示器(AMOLED)、薄膜晶体管液晶显示器(TFT-LCD)等。TFT-LCD具有体积小、功耗低、无辐射等特点，在当前的平板显示器市场中占据了主导地位。根据驱动液晶的电场方向，TFT-LCD分为垂直电场型和水平电场型。而垂直电场型包括扭转向列(TN)TFT-LCD，水平电场型包括边缘场效应(FFS)TFT-LCD、共平面场效应(IPS)TFT-LCD。FFS型TFT-LCD具有宽视角、高开口率等优点，在液晶显示领域得到了广泛的应用。The flat panel display is currently a mainstream display, which includes an active matrix organic light emitting diode display (AMOLED), a thin film transistor liquid crystal display (TFT-LCD), and the like. TFT-LCD has the characteristics of small size, low power consumption, and no radiation, etc., and occupies a dominant position in the current flat panel display market. According to the direction of the electric field driving the liquid crystal, the TFT-LCD is divided into a vertical electric field type and a horizontal electric field type. The vertical electric field type includes twisted nematic (TN) TFT-LCD, and the horizontal electric field type includes fringe field effect (FFS) TFT-LCD and in-plane field effect (IPS) TFT-LCD. FFS-type TFT-LCD has the advantages of wide viewing angle and high aperture ratio, and has been widely used in the field of liquid crystal display.
在薄膜晶体管的制作工艺中，在一些情况下，为了防止在形成源漏电极时对有源层的过刻，需要在有源层上沉积一层刻蚀阻挡层，这需要一次额外的光刻工艺形成刻蚀阻挡层，例如，对于底栅型TFT，一般需要五次构图工艺完成制造，工艺复杂，制造时间较长，制造成本也较高。In the manufacturing process of thin film transistors, in some cases, in order to prevent over-etching of the active layer when forming the source and drain electrodes, it is necessary to deposit an etch stop layer on the active layer, which requires an additional photolithography process to form an etch barrier layer. For example, for bottom-gate TFTs, five patterning processes are generally required to complete the manufacture. The process is complicated, the manufacturing time is long, and the manufacturing cost is also high.
另外，液晶显示器的尺寸在不断增大，驱动电路的频率在不断提高，由于非晶硅薄膜晶体管的迁移率一般在0.5cm2/VS左右，而液晶显示器尺寸超过80in时，驱动频率超过120Hz，需要1cm2/VS以上的迁移率，现有的非晶硅薄膜晶体管迁移率很难满足需求。金属氧化物薄膜晶体管的迁移率高、均一性好、透明，可以更好地满足大尺寸液晶显示器和有源有机电致发光的需求，因此高性能金属氧化物薄膜晶体管备受人们的关注，已成为最近的研究热点。In addition, the size of the liquid crystal display is constantly increasing, and the frequency of the driving circuit is constantly increasing. Since the mobility of the amorphous silicon thin film transistor is generally around 0.5cm2 /VS, and when the size of the liquid crystal display exceeds 80in, the driving frequency exceeds 120Hz. A mobility of more than 1 cm2 /VS is required, and the mobility of existing amorphous silicon thin film transistors is difficult to meet the requirement. Metal oxide thin film transistors have high mobility, good uniformity, and transparency, which can better meet the needs of large-size liquid crystal displays and active organic electroluminescence. Therefore, high-performance metal oxide thin film transistors have attracted people's attention and have been become a recent research hotspot.
发明内容Contents of the invention
本发明的目的是提供一种阵列基板及其制造方法、显示装置，采用四次构图工艺实现阵列基板的制造，从而缩短生产时间，提高生产效率，降低生产成本。The object of the present invention is to provide an array substrate and its manufacturing method, and a display device, which realizes the manufacture of the array substrate by adopting four patterning techniques, thereby shortening the production time, improving the production efficiency and reducing the production cost.
为了实现上述目的，本发明提供一种阵列基板的制造方法，包括：In order to achieve the above object, the present invention provides a method for manufacturing an array substrate, comprising:
步骤1、形成第一层像素电极、栅线和栅电极的图形；Step 1, forming the pattern of the first layer of pixel electrodes, gate lines and gate electrodes;
步骤2、形成有源层的图形；Step 2, forming the pattern of the active layer;
步骤3、形成保护层和阻挡层的图形；Step 3, forming the graphics of the protective layer and the barrier layer;
步骤4、形成第二层像素电极、源漏电极和数据线的图形Step 4, forming the graphics of the second layer of pixel electrodes, source and drain electrodes and data lines
上述的制造方法，其中：The above-mentioned manufacturing method, wherein:
所述步骤1包括：在基板上形成透明导电薄膜和栅金属薄膜，通过构图工艺形成第一层像素电极、栅线和栅电极的图形；The step 1 includes: forming a transparent conductive film and a gate metal film on the substrate, and forming the pattern of the first layer of pixel electrodes, gate lines and gate electrodes through a patterning process;
所述步骤2包括：形成栅绝缘层和有源层，通过构图工艺形成有源层的图形；The step 2 includes: forming a gate insulating layer and an active layer, and forming a pattern of the active layer through a patterning process;
所述步骤3包括：形成绝缘层，通过构图工艺形成保护层和阻挡层的图形，所述阻挡层位于所述有源层的沟道区域上方；The step 3 includes: forming an insulating layer, forming patterns of a protective layer and a barrier layer through a patterning process, and the barrier layer is located above the channel region of the active layer;
所述步骤4包括：形成透明导电薄膜和源漏金属薄膜，通过构图工艺形成第二层像素电极、源漏电极和数据线的图形。The step 4 includes: forming a transparent conductive film and a source-drain metal film, and forming patterns of the second layer of pixel electrodes, source-drain electrodes and data lines through a patterning process.
上述的制造方法，其中，所述有源层的材料为金属氧化物。In the above manufacturing method, the material of the active layer is metal oxide.
为了实现上述目的，本发明还提供一种阵列基板，包括：In order to achieve the above object, the present invention also provides an array substrate, comprising:
形成在基板上的第一层像素电极、栅线和栅电极；A first layer of pixel electrodes, gate lines and gate electrodes formed on the substrate;
形成在第一层像素电极、栅线和栅电极上的栅绝缘层；A gate insulating layer formed on the first layer of pixel electrodes, gate lines and gate electrodes;
形成在栅绝缘层上的有源层和保护层，以及形成在有源层的沟道区域上方的阻挡层；an active layer and a protective layer formed on the gate insulating layer, and a barrier layer formed over a channel region of the active layer;
形成在有源层上方的源漏电极和数据线，以及形成在保护层上的第二层像素电极。A source-drain electrode and a data line are formed on the active layer, and a second-layer pixel electrode is formed on the protection layer.
上述的阵列基板，其中，所述有源层的材料为金属氧化物。In the above array substrate, the material of the active layer is metal oxide.
为了实现上述目的，本发明还提供一种显示装置，其中，包括上述的阵列基板。In order to achieve the above object, the present invention further provides a display device, which includes the above-mentioned array substrate.
从以上所述可以看出，本发明提供的上述技术方案，在制造FFS型TFT的过程中，将刻蚀阻挡层与保护层利用一次构图工艺完成，这样通过四次构图工艺就能实现阵列基板的制造，从而缩短了生产时间，提高了生产效率，降低了生产成本。It can be seen from the above that, in the technical solution provided by the present invention, in the process of manufacturing the FFS type TFT, the etching stopper layer and the protective layer are completed by one patterning process, so that the array substrate can be realized through four patterning processes. Manufacturing, thereby shortening the production time, improving production efficiency and reducing production costs.
附图说明Description of drawings
图1为本发明实施例的阵列基板的截面图；1 is a cross-sectional view of an array substrate according to an embodiment of the present invention;
图2为本发明实施例的阵列基板的制造方法流程图；2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
图3为本发明实施例在沉积透明导电薄膜和栅金属薄膜后的截面图；3 is a cross-sectional view of an embodiment of the present invention after depositing a transparent conductive film and a gate metal film;
图4为本发明实施例在第一次构图工艺中经过灰色调或半色调掩模板曝光显影后的截面图；4 is a cross-sectional view of an embodiment of the present invention after exposure and development of a gray-tone or half-tone mask in the first patterning process;
图5为本发明实施例在完成第一次构图工艺后的截面图；5 is a cross-sectional view of an embodiment of the present invention after the first patterning process is completed;
图6为本发明实施例在完成第二次构图工艺后的截面图；6 is a cross-sectional view of an embodiment of the present invention after the second patterning process is completed;
图7为本发明实施例在完成第三次构图工艺后的截面图；7 is a cross-sectional view of an embodiment of the present invention after the third patterning process is completed;
图8为本发明实施例在沉积透明导电薄膜和源漏金属薄膜后的截面图；8 is a cross-sectional view of an embodiment of the present invention after depositing a transparent conductive film and a source-drain metal film;
图9为本发明实施例在第四次构图工艺中经过灰色调或半色调掩模板曝光显影后的截面图。9 is a cross-sectional view of an embodiment of the present invention after exposure and development of a gray-tone or half-tone mask in the fourth patterning process.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图及具体实施例对本发明进行详细描述。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
图1为本发明实施例的阵列基板的截面图，参照图1，该阵列基板包括：FIG. 1 is a cross-sectional view of an array substrate according to an embodiment of the present invention. Referring to FIG. 1, the array substrate includes:
形成在基板1上的第一层像素电极2、栅线(图中未示出)和栅电极3和；The first layer of pixel electrodes 2, gate lines (not shown in the figure) and gate electrodes 3 formed on the substrate 1;
形成在第一层像素电极2、栅线和栅电极3上的栅绝缘层4；A gate insulating layer 4 formed on the first layer of pixel electrodes 2, gate lines and gate electrodes 3;
形成在栅绝缘层4上的有源层5和保护层6，以及形成在有源层5的沟道区域上方的阻挡层7；an active layer 5 and a protection layer 6 formed on the gate insulating layer 4, and a barrier layer 7 formed above the channel region of the active layer 5;
形成在有源层5上方的源漏电极9和数据线(图中未示出)，以及形成在保护层6上的第二层像素电极8。Source-drain electrodes 9 and data lines (not shown in the figure) are formed on the active layer 5 , and second-layer pixel electrodes 8 are formed on the protective layer 6 .
形成上述阵列基板各层图形的方法可以为先进行金属的沉积，然后采用包括掩膜、刻蚀等的构图工艺来实现，还可以为不进行金属的沉积而直接进行丝网印刷、打印等常用构图工艺来实现。本领域技术人员可以根据具体的需求进行选择。The method of forming the pattern of each layer of the above-mentioned array substrate can be to deposit metal first, and then use patterning processes including masking, etching, etc., or directly perform screen printing, printing, etc. without depositing metal. Composition process to achieve. Those skilled in the art can make selections according to specific requirements.
金属氧化物薄膜晶体管的迁移率高、均一性好、透明，可以更好地满足大尺寸液晶显示器和有源有机电致发光的需求。因此，作为一个优选方案，本发明实施例的上述阵列基板中的所述有源层5的材料为金属氧化物，例如，IGZO、IZO、ZnO等。通过将金属氧化物的高迁移率与FFS型宽视角结合在一起，使得该阵列基板能够在大尺寸TFT-LCD中得到广泛的应用，并同时具备高开口率、高迁移率和宽视角等优点。Metal oxide thin film transistors have high mobility, good uniformity, and transparency, which can better meet the needs of large-size liquid crystal displays and active organic electroluminescence. Therefore, as a preferred solution, the material of the active layer 5 in the above-mentioned array substrate in the embodiment of the present invention is a metal oxide, such as IGZO, IZO, ZnO and the like. By combining the high mobility of metal oxides with the wide viewing angle of the FFS type, the array substrate can be widely used in large-size TFT-LCDs, and has the advantages of high aperture ratio, high mobility and wide viewing angle. .
另外，对于此种结构的阵列基板，可以将保护层6与阻挡层7合为一张掩膜板(Mask)来完成，这样通过四次构图工艺就能实现阵列基板的制造，如此，能够简化阵列基板的制造工艺，降低生产成本。In addition, for the array substrate with this structure, the protection layer 6 and the barrier layer 7 can be combined into one mask (Mask), so that the manufacture of the array substrate can be realized through four patterning processes, thus simplifying the The manufacturing process of the array substrate reduces the production cost.
图2为本发明实施例的阵列基板的制造方法流程图，参照图2，该制造方法包括如下步骤：FIG. 2 is a flow chart of a manufacturing method of an array substrate according to an embodiment of the present invention. Referring to FIG. 2, the manufacturing method includes the following steps:
步骤100：在基板上依次沉积透明导电薄膜和栅金属薄膜，通过第一次构图工艺形成第一层像素电极、栅线和栅电极的图形；Step 100: sequentially depositing a transparent conductive film and a gate metal film on the substrate, and forming the pattern of the first layer of pixel electrodes, gate lines and gate electrodes through the first patterning process;
首先提供一基板，所述基板可以选用玻璃基板或者石英基板；然后，如图3所示，采用溅射、热蒸发或其它成膜方法在基板上依次沉积厚度为30-50nm的透明导电薄膜21和厚度为200-400nm的金属层31，所述透明导电薄膜可以为氧化铟锡、氧化锌锡等，金属层31可以是Cu、Al、Mo、Ti等，所述透明导电薄膜21用于形成所述第一层像素电极，所述金属层31用于形成所述栅线和所述栅电极；最后，如图5所示，通过第一次构图工艺形成第一层像素电极、栅线和栅电极的图形。First, a substrate is provided, and the substrate can be a glass substrate or a quartz substrate; then, as shown in Figure 3, a transparent conductive film 21 with a thickness of 30-50nm is sequentially deposited on the substrate by sputtering, thermal evaporation or other film-forming methods. And a metal layer 31 with a thickness of 200-400nm, the transparent conductive film can be indium tin oxide, zinc tin oxide, etc., the metal layer 31 can be Cu, Al, Mo, Ti, etc., and the transparent conductive film 21 is used to form The first layer of pixel electrodes, the metal layer 31 are used to form the gate lines and the gate electrodes; finally, as shown in FIG. 5 , the first layer of pixel electrodes, gate lines and The pattern of the grid electrode.
步骤200：在完成步骤100的基板上依次沉积栅绝缘层和有源层，通过第二次构图工艺形成有源层的图形；Step 200: sequentially depositing a gate insulating layer and an active layer on the substrate after step 100, and forming a pattern of the active layer through a second patterning process;
首先，采用等离子体增强化学气相沉积(PECVD)或磁控溅射方法，在完成步骤100的基板上依次沉积厚度为30nm-80nm的栅绝缘层和厚度为20nm-50nm的有源层，其中，栅绝缘层可以选用氧化物或者氮化物，有源层的材料优选为金属氧化物，所述金属氧化物可以为IGZO、ZnO或IZO等；然后，如图6所示，通过第二次构图工艺形成有源层的图形。First, a gate insulating layer with a thickness of 30nm-80nm and an active layer with a thickness of 20nm-50nm are sequentially deposited on the substrate after step 100 by using plasma enhanced chemical vapor deposition (PECVD) or magnetron sputtering, wherein, The gate insulating layer can be selected from oxide or nitride, and the material of the active layer is preferably a metal oxide, and the metal oxide can be IGZO, ZnO or IZO, etc.; then, as shown in Figure 6, through the second patterning process Form the pattern of the active layer.
步骤300：在完成步骤200的基板上沉积绝缘层，通过第三次构图工艺形成保护层和阻挡层的图形，所述阻挡层位于所述有源层的沟道区域上方；Step 300: Deposit an insulating layer on the substrate after step 200, and form a pattern of a protective layer and a barrier layer through a third patterning process, and the barrier layer is located above the channel region of the active layer;
首先，采用PECVD或磁控溅射方法，在完成步骤200的基板上沉积厚度为100nm-200nm的绝缘层，其中，绝缘层可以选用氧化物或者氮化物；然后，如图7所示，通过第三次构图工艺形成保护层和阻挡层的图形。First, an insulating layer with a thickness of 100nm-200nm is deposited on the substrate completed in step 200 by PECVD or magnetron sputtering, wherein the insulating layer can be an oxide or nitride; then, as shown in FIG. The patterns of the protection layer and the barrier layer are formed by three patterning processes.
步骤400：在完成步骤300的基板上依次沉积透明导电薄膜和源漏金属薄膜，通过第四次构图工艺形成第二层像素电极、源漏电极和数据线的图形。Step 400: Deposit a transparent conductive film and a source-drain metal film sequentially on the substrate completed in step 300, and form patterns of pixel electrodes, source-drain electrodes and data lines in the second layer through a fourth patterning process.
首先，如图8所示，采用溅射、热蒸发或其它成膜方法在完成步骤300的基板上依次沉积厚度为30-50nm的透明导电薄膜和厚度为200-400nm的金属层，所述透明导电薄膜可以为氧化铟锡、氧化锌锡等，金属层可以是Cu、Al、Mo、Ti等，所述透明导电薄膜用于形成所述第二层像素电极，所述金属层用于形成所述数据线和所述源漏电极；然后，如图1所示，通过第四次构图工艺形成第二层像素电极、源漏电极和数据线的图形。First, as shown in FIG. 8, a transparent conductive film with a thickness of 30-50 nm and a metal layer with a thickness of 200-400 nm are sequentially deposited on the substrate after step 300 by sputtering, thermal evaporation or other film-forming methods. The conductive film can be indium tin oxide, zinc tin oxide, etc., and the metal layer can be Cu, Al, Mo, Ti, etc., the transparent conductive film is used to form the second layer of pixel electrodes, and the metal layer is used to form the The data lines and the source-drain electrodes; then, as shown in FIG. 1 , the patterns of the second-layer pixel electrodes, source-drain electrodes, and data lines are formed through a fourth patterning process.
以下给出上述制造方法中构图工艺的详细流程。The detailed flow of the patterning process in the above manufacturing method is given below.
在步骤100中，所述通过第一次构图工艺形成第一层像素电极、栅线和栅电极的图形，具体包括：In step 100, the patterning of the first layer of pixel electrodes, gate lines and gate electrodes is formed through the first patterning process, which specifically includes:
步骤S11：在栅金属薄膜上涂敷一层光刻胶10；Step S11: coating a layer of photoresist 10 on the gate metal film;
步骤S12：采用灰色调或半色调掩模板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域、光刻胶部分保留区域和光刻胶完全保留区域，其中，光刻胶完全保留区域对应栅线和栅电极的图形所在区域，光刻胶部分保留区域对应第一层像素电极的图形所在区域，光刻胶未保留区域对应上述图形以外的区域；Step S12: exposing the photoresist by using a gray tone or halftone mask, so that the photoresist forms a photoresist unretained area, a photoresist partially reserved area, and a photoresist completely reserved area, wherein the photoresist is completely The reserved area corresponds to the area where the pattern of the gate line and the gate electrode is located, the partially reserved area of the photoresist corresponds to the area where the pattern of the pixel electrode of the first layer is located, and the unreserved area of the photoresist corresponds to the area other than the above-mentioned pattern;
步骤S13：进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶部分保留区域的光刻胶厚度变薄，光刻胶完全保留区域的光刻胶厚度保持不变；Step S13: performing a developing process, the photoresist in the region where the photoresist is not retained is completely removed, the thickness of the photoresist in the region where the photoresist is partially retained becomes thinner, and the thickness of the photoresist in the region where the photoresist is completely retained remains unchanged;
显影得到的图形如图4所示，图中，WP为光刻胶未保留区域，HP为光刻胶部分保留区域，NP为光刻胶完全保留区域。The image obtained by developing is shown in Figure 4. In the figure, WP is the area where the photoresist is not retained, HP is the area where the photoresist is partially retained, and NP is the area where the photoresist is completely retained.
步骤S14：刻蚀掉光刻胶未保留区域的栅金属薄膜和透明导电薄膜，形成栅线和栅电极的图形；Step S14: Etching away the gate metal film and the transparent conductive film in the unretained area of the photoresist to form the pattern of the gate line and the gate electrode;
步骤S15：通过灰化工艺去除光刻胶部分保留区域的光刻胶，保留光刻胶完全保留区域的光刻胶；Step S15: removing the photoresist in the partly reserved area of the photoresist through an ashing process, and retaining the photoresist in the completely reserved area of the photoresist;
步骤S16：刻蚀掉光刻胶部分保留区域的栅金属薄膜，形成第一层像素电极的图形；Step S16: Etching away the gate metal film in the partially reserved area of the photoresist to form the pattern of the first layer of pixel electrodes;
步骤S17：去除剩余的光刻胶。Step S17: removing the remaining photoresist.
在步骤200中，所述通过第二次构图工艺形成有源层的图形，具体包括：In step 200, forming the pattern of the active layer through the second patterning process specifically includes:
步骤S21：在有源层上涂敷一层光刻胶；Step S21: coating a layer of photoresist on the active layer;
步骤S22：采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶保留区域和光刻胶未保留区域，其中，光刻胶保留区域对应有源层的图形所在区域，光刻胶未保留区域对应上述图形以外的区域；Step S22: using a mask to expose the photoresist, so that the photoresist forms a photoresist reserved area and a photoresist unreserved area, wherein the photoresist reserved area corresponds to the area where the pattern of the active layer is located. The unretained area of glue corresponds to the area outside the above figure;
步骤S23：进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；Step S23: performing a developing process, the photoresist in the area where the photoresist is not retained is completely removed, and the thickness of the photoresist in the area where the photoresist is retained remains unchanged;
步骤S24：刻蚀掉光刻胶未保留区域的有源层，形成有源层的图形；Step S24: Etching away the active layer in the unretained area of the photoresist to form a pattern of the active layer;
步骤S25：去除剩余的光刻胶。Step S25: removing the remaining photoresist.
在步骤300中，所述通过第三次构图工艺形成保护层和阻挡层的图形，具体包括：In step 300, forming the pattern of the protective layer and the barrier layer through the third patterning process specifically includes:
步骤S31：在绝缘层上涂敷一层光刻胶；Step S31: coating a layer of photoresist on the insulating layer;
步骤S32：采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶保留区域和光刻胶未保留区域，其中，光刻胶保留区域对应保护层和阻挡层的图形所在区域，光刻胶未保留区域对应上述图形以外的区域；Step S32: using a mask to expose the photoresist, so that the photoresist forms a photoresist reserved area and a photoresist unreserved area, wherein the photoresist reserved area corresponds to the area where the pattern of the protective layer and the barrier layer are located, The unreserved area of photoresist corresponds to the area other than the above pattern;
步骤S33：进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；Step S33: performing a development process, the photoresist in the area where the photoresist is not retained is completely removed, and the thickness of the photoresist in the area where the photoresist is retained remains unchanged;
步骤S34：刻蚀掉光刻胶未保留区域的绝缘层，形成保护层和阻挡层的图形；Step S34: Etching away the insulating layer in the unretained area of the photoresist to form patterns of the protective layer and the barrier layer;
步骤S35：去除剩余的光刻胶。Step S35: removing the remaining photoresist.
通过第三次构图工艺，形成了TFT沟道过孔，用于源漏电极与有源层的电性连接。另外，在第三次构图工艺中，还可同时形成栅线外接过孔。Through the third patterning process, TFT channel via holes are formed for electrical connection between the source and drain electrodes and the active layer. In addition, in the third patterning process, the gate line circumscribed via holes can also be formed at the same time.
在步骤400中，所述通过第四次构图工艺形成第二层像素电极、源漏电极和数据线的图形，具体包括：In step 400, the patterning of the second layer of pixel electrodes, source and drain electrodes and data lines is formed through the fourth patterning process, which specifically includes:
步骤S41：在源漏金属薄膜上涂敷一层光刻胶11；Step S41: coating a layer of photoresist 11 on the source-drain metal film;
步骤S42：采用灰色调或半色调掩模板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域、光刻胶部分保留区域和光刻胶完全保留区域，其中，光刻胶完全保留区域对应源漏电极和数据线的图形所在区域，光刻胶部分保留区域对应第二层像素电极的图形所在区域，光刻胶未保留区域对应上述图形以外的区域；Step S42: Exposing the photoresist with a gray-tone or half-tone mask, so that the photoresist forms a photoresist unretained area, a photoresist partially reserved area, and a photoresist completely reserved area, wherein the photoresist is completely The reserved area corresponds to the area where the pattern of the source-drain electrode and the data line is located, the partially reserved area of the photoresist corresponds to the area where the pattern of the pixel electrode of the second layer is located, and the unreserved area of the photoresist corresponds to the area other than the above-mentioned pattern;
步骤S43：进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶部分保留区域的光刻胶厚度变薄，光刻胶完全保留区域的光刻胶厚度保持不变；Step S43: performing a development process, the photoresist in the photoresist unretained area is completely removed, the photoresist thickness in the photoresist partially reserved area becomes thinner, and the photoresist thickness in the photoresist completely reserved area remains unchanged;
显影得到的图形如图9所示，图中，WP为光刻胶未保留区域，HP为光刻胶部分保留区域，NP为光刻胶完全保留区域。The image obtained by developing is shown in FIG. 9 . In the figure, WP is the area where the photoresist is not retained, HP is the area where the photoresist is partially retained, and NP is the area where the photoresist is completely retained.
步骤S44：刻蚀掉光刻胶未保留区域的源漏金属薄膜和透明导电薄膜，形成源漏电极和数据线的图形；Step S44: Etching away the source-drain metal film and the transparent conductive film in the unreserved region of the photoresist to form patterns of source-drain electrodes and data lines;
步骤S45：通过灰化工艺去除光刻胶部分保留区域的光刻胶，保留光刻胶完全保留区域的光刻胶；Step S45: removing the photoresist in the partly reserved area of the photoresist through an ashing process, and retaining the photoresist in the completely reserved area of the photoresist;
步骤S46：刻蚀掉光刻胶部分保留区域的源漏金属薄膜，形成第二层像素电极的图形；Step S46: Etching away the source-drain metal film in the part of the photoresist reserved area to form the pattern of the second-layer pixel electrode;
步骤S47：去除剩余的光刻胶。Step S47: removing the remaining photoresist.
上述构图工艺中，光刻胶的形成是以涂敷的方式为例，当然也可以采用沉积等方式形成光刻胶。In the above patterning process, the formation of the photoresist is exemplified by coating, and of course the photoresist may also be formed by deposition or the like.
本发明实施例还提供一种显示装置，其特征在于，包括：彩膜基板；接合于所述彩膜基板的薄膜晶体管阵列基板；夹设于所述彩膜基板和所述薄膜晶体管阵列基板之间的液晶层。所述薄膜晶体管阵列基板包括：An embodiment of the present invention also provides a display device, which is characterized by comprising: a color filter substrate; a thin film transistor array substrate bonded to the color filter substrate; and sandwiched between the color filter substrate and the thin film transistor array substrate the liquid crystal layer in between. The thin film transistor array substrate includes:
形成在基板上的第一层像素电极、栅线和栅电极；A first layer of pixel electrodes, gate lines and gate electrodes formed on the substrate;
形成在栅线、栅电极和第一层像素电极上的栅绝缘层；a gate insulating layer formed on the gate lines, the gate electrodes and the first layer of pixel electrodes;
形成在栅绝缘层上的有源层和保护层，以及形成在有源层的沟道区域上方的阻挡层；an active layer and a protective layer formed on the gate insulating layer, and a barrier layer formed over a channel region of the active layer;
形成在有源层上方的源漏电极和数据线，以及形成在保护层上的第二层像素电极。A source-drain electrode and a data line are formed on the active layer, and a second-layer pixel electrode is formed on the protection layer.
优选地，所述有源层的材料为金属氧化物。Preferably, the material of the active layer is metal oxide.
需要说明的是，上述显示装置可以为液晶显示面板、液晶显示器、液晶电视、AMOLED显示面板、AMOLED显示器等，在此不对其进行限制。It should be noted that the above display device may be a liquid crystal display panel, a liquid crystal display, a liquid crystal television, an AMOLED display panel, an AMOLED display, etc., which is not limited here.
综上所述，本发明实施例提供的上述技术方案，在制造FFS型TFT的过程中，将刻蚀阻挡层与保护层利用一次构图工艺完成，这样通过四次构图工艺就能实现阵列基板的制造，从而缩短了生产时间，提高了生产效率，降低了生产成本。To sum up, in the above technical solution provided by the embodiment of the present invention, in the process of manufacturing the FFS type TFT, the etching barrier layer and the protective layer are completed by one patterning process, so that the array substrate can be realized by four patterning processes. Manufacturing, thereby shortening production time, improving production efficiency and reducing production costs.
最后应当说明的是，以上实施例仅用以说明本发明的技术方案而非限制，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神范围，其均应涵盖在本发明的权利要求范围当中。Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention and not to limit it. Those of ordinary skill in the art should understand that the technical solution of the present invention can be modified or equivalently replaced without departing from the technical solution of the present invention. The spiritual scope of the invention should be included in the scope of the claims of the present invention.
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| CN201110329601.3ACN102709235B (en) | 2011-10-26 | 2011-10-26 | Array base board as well as manufacturing method and display device thereof |
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