CN102648526B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes crystals whose c-axis is aligned with a direction substantially perpendicular to the surface of the oxide semiconductor layer.

Description

Translated fromChinese

半导体器件及其制造方法Semiconductor device and manufacturing method thereof

技术领域technical field

所公开的本发明的技术领域涉及包含氧化物半导体的半导体器件以及该半导体器件的制造方法。注意，此处，半导体器件是指通过利用半导体特性而起作用的通用元件和器件。The technical field of the disclosed invention relates to a semiconductor device including an oxide semiconductor and a method of manufacturing the semiconductor device. Note that here, a semiconductor device refers to general-purpose elements and devices that function by utilizing semiconductor characteristics.

背景技术Background technique

场效应晶体管是最广泛被使用的半导体元件之一。根据晶体管的用途，各种材料被用于场效应晶体管。特定地，包含硅的半导体材料经常被使用。Field effect transistors are one of the most widely used semiconductor components. Various materials are used for field effect transistors depending on the use of the transistor. In particular, semiconductor materials containing silicon are often used.

包含硅的场效应晶体管具有满足各种用途的需要的特性。例如，单晶硅被用于需要以高速操作的集成电路等，藉此满足需要。进一步，非晶硅被用于需要大面积的对象，诸如显示设备，藉此可满足需要。Field effect transistors including silicon have characteristics satisfying the needs of various uses. For example, single crystal silicon is used for integrated circuits and the like required to operate at high speed, thereby satisfying the demand. Further, amorphous silicon is used for objects requiring a large area, such as a display device, whereby the demand can be satisfied.

如上所述，硅是高度通用的且可被用于各种目的。然而，近年来，半导体材料已经变得被期待具有更高的性能以及通用性。例如，在改进大面积显示设备的性能方面，为了实现开关元件的高速操作，需要有助于增加显示设备面积且相比非晶硅表现出更高性能的半导体材料。As mentioned above, silicon is highly versatile and can be used for a variety of purposes. However, in recent years, semiconductor materials have become expected to have higher performance and versatility. For example, in improving the performance of a large-area display device, in order to realize high-speed operation of a switching element, a semiconductor material that contributes to an increase in the area of the display device and exhibits higher performance than amorphous silicon is required.

在这样的条件下，包含氧化物半导体的场效应晶体管(也被称为FET)的技术已经引起了注意。例如，专利文献1公开了包含同系化合物InMO₃(ZnO)_m(M是In、Fe、Ga、或Al，且m是大于或等于1且小于50的整数)的透明薄膜场效应晶体管。Under such conditions, the technology of field effect transistors (also referred to as FETs) including oxide semiconductors has attracted attention. For example, Patent Document 1 discloses a transparent thin film field effect transistor including a homologous compound InMO₃ (ZnO)_m (M is In, Fe, Ga, or Al, and m is an integer greater than or equal to 1 and less than 50).

此外，专利文献2公开了其中使用包含In、Ga和Zn且具有小于10¹⁸/cm³的电子载流子密度的非晶氧化物半导体的场效应晶体管。注意，在这个专利文献中，非晶氧化物半导体中In原子与Ga原子和Zn原子的比值为1∶1∶m(m＜6)。Furthermore, Patent Document 2 discloses a field effect transistor in which an amorphous oxide semiconductor containing In, Ga, and Zn and having an electron carrier density of less than 10¹⁸ /cm³ is used. Note that in this patent document, the ratio of In atoms to Ga atoms and Zn atoms in the amorphous oxide semiconductor is 1:1:m (m<6).

进一步，专利文献3公开了为活性层使用其中包含微晶的非晶氧化物半导体的场效应晶体管。Further, Patent Document 3 discloses a field effect transistor using an amorphous oxide semiconductor containing microcrystals therein for an active layer.

[参考文献][references]

[专利文献1]日本公开专利申请No.2004-103957[Patent Document 1] Japanese Laid-Open Patent Application No. 2004-103957

[专利文献2]PCT国际公开No.05/088726[Patent Document 2] PCT International Publication No. 05/088726

[专利文献3]日本公开专利申请No.2006-165529[Patent Document 3] Japanese Laid-Open Patent Application No. 2006-165529

发明内容Contents of the invention

专利文献3公开了处于非晶状态的组合物是InGaO₃(ZnO)_m(m是小于6的整数)。进一步，专利文献3在示例1中公开了InGaO₃(ZnO)₄的情况。然而，实际上，即使在使用了这样的氧化物半导体的情况下也没有获得充足的特性。Patent Document 3 discloses that a composition in an amorphous state is InGaO₃ (ZnO)_m (m is an integer smaller than 6). Further, Patent Document 3 discloses the case of InGaO₃ (ZnO)₄ in Example 1. Actually, however, sufficient characteristics are not obtained even when such an oxide semiconductor is used.

考虑到上述问题，目的是提供具有其中使用了具有新颖结构的氧化物半导体层的新颖结构的半导体器件。In view of the above-mentioned problems, an object is to provide a semiconductor device having a novel structure in which an oxide semiconductor layer having a novel structure is used.

在所公开的本发明的实施例中，使用被纯化且包括结晶区的氧化物半导体层而形成半导体器件。结晶区是，例如，具有电各向异性的区域或防止杂质进入的区域。In the disclosed embodiments of the present invention, a semiconductor device is formed using an oxide semiconductor layer that is purified and includes a crystalline region. The crystallization region is, for example, a region having electrical anisotropy or a region where entry of impurities is prevented.

例如可采用以下结构。For example, the following structures can be adopted.

所公开的本发明的实施例是半导体器件，其包括氧化物半导体层，该氧化物半导体层包含位于绝缘表面上的结晶区、与该氧化物半导体层相接触的源电极层和漏电极层、覆盖该氧化物半导体层、该源电极层、以及该漏电极层的栅绝缘层、以及在栅绝缘层上与结晶区相交迭的区域中的栅电极层。结晶区包括其c-轴与基本垂直于氧化物半导体层的表面的方向对齐的晶体。注意，在本说明书等中，“基本垂直”意味着相对于垂直方向在±10°范围内。An embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor layer including a crystalline region on an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, A gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer in a region overlapping the crystalline region on the gate insulating layer. The crystalline region includes crystals whose c-axis is aligned with a direction substantially perpendicular to the surface of the oxide semiconductor layer. Note that in this specification and the like, "substantially vertical" means within a range of ±10° with respect to the vertical direction.

所公开的本发明的另一个实施例是半导体器件，其包括位于绝缘表面上的第一栅电极层、覆盖该第一栅电极层的第一栅绝缘层、包含位于该第一栅绝缘层上结晶区的氧化物半导体层、与该氧化物半导体层相接触的源电极层和漏电极层、覆盖该氧化物半导体层、源电极层、以及漏电极层的第二栅绝缘层、以及位于第二栅绝缘层上与该结晶区相交迭的区域中的第二栅电极层。结晶区包括其c-轴与基本垂直于氧化物半导体层的表面的方向对齐的晶体。Another embodiment of the disclosed invention is a semiconductor device comprising a first gate electrode layer on an insulating surface, a first gate insulating layer covering the first gate electrode layer, including a first gate insulating layer on the first gate insulating layer The oxide semiconductor layer in the crystalline region, the source electrode layer and the drain electrode layer in contact with the oxide semiconductor layer, the second gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and the The second gate electrode layer in the area overlapping with the crystallization area on the second gate insulating layer. The crystalline region includes crystals whose c-axis is aligned with a direction substantially perpendicular to the surface of the oxide semiconductor layer.

此外，可在源电极层和漏电极层上提供具有与源电极层和漏电极层基本一样的形状的绝缘层。注意，在本说明书等中，表述“基本一样”或“基本是一样”并不必然意味着在严格意义上严格地一样且可意味着被认为是一样的。例如，由单个蚀刻工艺造成的差异是可接受的。进一步，厚度并不需要是一样的。In addition, an insulating layer having substantially the same shape as the source electrode layer and the drain electrode layer may be provided on the source electrode layer and the drain electrode layer. Note that in this specification and the like, the expression "substantially the same" or "substantially the same" does not necessarily mean strictly the same in a strict sense and may mean considered to be the same. For example, variance caused by a single etch process is acceptable. Further, the thickness need not be the same.

此外，源电极层和漏电极层与氧化物半导体层接触的一部分可包括具有低氧亲和力。In addition, a portion of the source electrode layer and the drain electrode layer in contact with the oxide semiconductor layer may have a low oxygen affinity.

氧化物半导体层中结晶区以外的区域(如，沟道形成区以外的区域)可具有非晶结构。Regions other than the crystalline region (for example, regions other than the channel formation region) in the oxide semiconductor layer may have an amorphous structure.

在与栅电极层相交迭的区域中，氧化物半导体层表面高度差异可以是1nm或更小。In a region overlapping with the gate electrode layer, the difference in surface height of the oxide semiconductor layer may be 1 nm or less.

所公开的本发明的另一个实施例是制造半导体器件的方法，其包括如下步骤：在绝缘表面上形成氧化物半导体层；在该氧化物半导体层上形成导电层；通过蚀刻该导电层而形成源电极层和漏电极层；通过执行热处理，形成具有与基本垂直于该氧化物半导体层表面的方向对齐的c-轴的结晶区；形成栅绝缘层来覆盖该氧化物半导体层、源电极层、以及漏电极层；并在该栅绝缘层上与结晶区相交迭的区域中形成栅电极层。Another embodiment of the disclosed invention is a method of manufacturing a semiconductor device, including the steps of: forming an oxide semiconductor layer on an insulating surface; forming a conductive layer on the oxide semiconductor layer; forming a source electrode layer and a drain electrode layer; by performing heat treatment, a crystalline region having a c-axis aligned with a direction substantially perpendicular to the surface of the oxide semiconductor layer is formed; a gate insulating layer is formed to cover the oxide semiconductor layer, the source electrode layer , and a drain electrode layer; and forming a gate electrode layer in a region overlapping the crystalline region on the gate insulating layer.

所公开的本发明的另一个实施例是制造半导体器件的方法，其包括如下步骤：在绝缘表面上形成第一栅电极层；形成第一栅绝缘层从而覆盖该第一栅电极层；在该第一栅绝缘层上形成氧化物半导体层，在该氧化物半导体层上形成导电层；通过蚀刻该导电层而形成源电极层和漏电极层；通过执行热处理，形成具有与基本垂直于该氧化物半导体层表面的方向对齐的c-轴的结晶区；形成第二栅绝缘层来覆盖该氧化物半导体层、源电极层、以及漏电极层；并在该第二栅绝缘层上与结晶区相交迭的区域中形成第二栅电极层。Another embodiment of the disclosed invention is a method of manufacturing a semiconductor device, including the steps of: forming a first gate electrode layer on an insulating surface; forming a first gate insulating layer so as to cover the first gate electrode layer; An oxide semiconductor layer is formed on the first gate insulating layer, and a conductive layer is formed on the oxide semiconductor layer; a source electrode layer and a drain electrode layer are formed by etching the conductive layer; c-axis crystalline region aligned in the direction of the surface of the material semiconductor layer; forming a second gate insulating layer to cover the oxide semiconductor layer, source electrode layer, and drain electrode layer; and forming the second gate insulating layer with the crystalline region A second gate electrode layer is formed in the overlapping area.

在上述实施例中，热处理可在高于或等于550℃且低于或等于850℃的温度下执行，优选地在高于或等于550℃且低于或等于750℃的温度下执行。当该导电层被蚀刻时，可移除该氧化物半导体层的部分。可在源电极层和漏电极层上形成具有与源电极层和漏电极层基本一样的形状的绝缘层。In the above-described embodiments, the heat treatment may be performed at a temperature higher than or equal to 550°C and lower than or equal to 850°C, preferably higher than or equal to 550°C and lower than or equal to 750°C. When the conductive layer is etched, part of the oxide semiconductor layer may be removed. An insulating layer having substantially the same shape as the source electrode layer and the drain electrode layer may be formed on the source electrode layer and the drain electrode layer.

源电极层和漏电极层与氧化物半导体层接触的一部分可使用具有低氧亲和力的材料形成。A portion of the source electrode layer and the drain electrode layer in contact with the oxide semiconductor layer may be formed using a material having a low oxygen affinity.

可将具有非晶结构的氧化物半导体层形成为氧化物半导体层，且该非晶结构可留在结晶区以外的区域中(如，沟道形成区以外的区域)。An oxide semiconductor layer having an amorphous structure may be formed as the oxide semiconductor layer, and the amorphous structure may remain in a region other than the crystalline region (eg, a region other than the channel formation region).

注意，在本说明书等中的诸如“上”或“下”之类的术语不一定是指组件直接置于另一组件之上或直接置于另一组件之下。例如，表述“栅绝缘层上的第一栅电极层”不排除有组件置于栅绝缘层和栅电极层之间的情况。此外，诸如“上”和“下”之类的术语只是为了方便描述，并且可包括组件的垂直关系颠倒的情况，除非另外指明。Note that terms such as "on" or "under" in this specification and the like do not necessarily mean that a component is placed directly on or directly below another component. For example, the expression "the first gate electrode layer on the gate insulating layer" does not exclude the case where a component is interposed between the gate insulating layer and the gate electrode layer. Furthermore, terms such as "upper" and "lower" are for convenience of description only and may include the case where the vertical relationship of components is reversed unless otherwise specified.

另外，在本说明书等中的诸如“电极”和“引线”之类的术语不限制组件的功能。例如，可使用“电极”作为部分的“引线”，且可使用“引线”作为部分的“电极”。此外，术语“电极”或“引线”可包括以集成的方式形成多个“电极”或“引线”的情况。In addition, terms such as "electrodes" and "leads" in this specification and the like do not limit the functions of components. For example, an "electrode" may be used as a part of a "lead", and a "lead" may be used as a part of a "electrode". Also, the term 'electrodes' or 'leads' may include a case where a plurality of 'electrodes' or 'leads' are formed in an integrated manner.

例如，当使用相反极性的晶体管时、或当在电路操作中改变电流流向时，“源极”和“漏极”的功能有时可彼此互换。因此，在本说明书中，术语“源极”与“漏极”可分别用于表示漏极和源极。For example, the functions of "source" and "drain" are sometimes interchanged with each other when using transistors of opposite polarity, or when changing the direction of current flow in circuit operation. Therefore, in this specification, the terms "source" and "drain" may be used to denote a drain and a source, respectively.

注意，在本说明书等中的术语“电连接”包括组件通过具有任何电功能的物体连接的情况。只要可在通过该物体连接的组件之间发射和接收电信号，对具有任何电功能的物体就没有具体限制。Note that the term "electrically connected" in this specification and the like includes a case where components are connected by an object having any electrical function. There is no particular limitation on an object having any electrical function as long as electric signals can be transmitted and received between components connected through the object.

“具有任何电功能的对象”的示例是诸如晶体管的开关元件、电阻器、电感器、电容器、以及具有各种功能以及电极和引线的元件。Examples of "objects having any electrical function" are switching elements such as transistors, resistors, inductors, capacitors, and elements having various functions as well as electrodes and leads.

在所公开的发明的实施例中，被提纯的氧化物半导体层被用于半导体器件。提纯意味着以下中的至少一项：从氧化物半导体层中尽量移除氢(氢导致氧化物半导体改变为n-型氧化物半导体)，和通过提供氧化物半导体层缺少的氧来减少缺陷(缺陷是由氧化物半导体层中的缺氧引起的)，缺氧。In an embodiment of the disclosed invention, the purified oxide semiconductor layer is used in a semiconductor device. Purification means at least one of the following: removing hydrogen as much as possible from the oxide semiconductor layer (hydrogen causes the oxide semiconductor to change into an n-type oxide semiconductor), and reducing defects by supplying oxygen lacking in the oxide semiconductor layer ( The defect is caused by oxygen deficiency in the oxide semiconductor layer), oxygen deficiency.

进行提纯从而获得本征(i-型)氧化物半导体层。由于氧化物半导体层一般具有n-型导电率，截止态电流较高。当截止态电流较高时，开关特性不充分，这对于半导体器件是不合适的。因此，氧化物半导体层被提纯从而改变为i-型或基本i-型的氧化物半导体层。Purification is performed to obtain an intrinsic (i-type) oxide semiconductor layer. Since the oxide semiconductor layer generally has n-type conductivity, the off-state current is high. When the off-state current is high, switching characteristics are insufficient, which is not suitable for a semiconductor device. Accordingly, the oxide semiconductor layer is purified to be changed into an i-type or substantially i-type oxide semiconductor layer.

在所公开的发明的实施例中，包括结晶区的氧化物半导体层被用在半导体器件中。In an embodiment of the disclosed invention, an oxide semiconductor layer including a crystalline region is used in a semiconductor device.

在包括具有电各向异性的结晶区的氧化物半导体层和没有结晶区的氧化物半导体层之间，电特性是不同的。例如，在包括具有与基本垂直于该氧化物半导体层表面的方向对齐的c-轴的结晶区的氧化物半导体层中，增加了与氧化物半导体层的表面平行的方向中的导电率且增加了与氧化物半导体层的表面垂直的方向中的绝缘性质。Electrical characteristics are different between an oxide semiconductor layer including a crystalline region having electrical anisotropy and an oxide semiconductor layer having no crystalline region. For example, in an oxide semiconductor layer including a crystalline region having a c-axis aligned with a direction substantially perpendicular to the surface of the oxide semiconductor layer, the conductivity in a direction parallel to the surface of the oxide semiconductor layer increases and increases The insulating property in the direction perpendicular to the surface of the oxide semiconductor layer is improved.

因此，当包括结晶区的氧化物半导体层被用作半导体器件时，半导体器件可具有良好的电特性。Therefore, when an oxide semiconductor layer including a crystalline region is used as a semiconductor device, the semiconductor device can have good electrical characteristics.

附图简述Brief description of the drawings

图1A和1B是各自示出半导体器件的截面图。1A and 1B are cross-sectional views each showing a semiconductor device.

图2是包括氧化物半导体的晶体管的截面图。FIG. 2 is a cross-sectional view of a transistor including an oxide semiconductor.

图3是图2中的A-A’截面的能带图(示意图)。Fig. 3 is an energy band diagram (schematic diagram) of the A-A' section in Fig. 2 .

图4A示出向栅极(GE1)施加正电压(V_G＞0)的状态，而图4B示出向栅极(GE1)施加负电压(V_G＜0)的状态。FIG. 4A shows a state where a positive voltage (_VG >0) is applied to the gate (GE1), and FIG. 4B shows a state where a negative voltage (_VG <0) is applied to the gate (GE1).

图5是示出真空能级和金属的功函数(φ_M)之间、以及真空能级和氧化物半导体的电子亲和力(χ)之间的关系的示图。5 is a graph showing the relationship between the vacuum level and the work function (φ_M ) of a metal, and between the vacuum level and the electron affinity (χ) of an oxide semiconductor.

图6示出在硅(Si)中热载流子注入所需的能量。Figure 6 shows the energy required for hot carrier injection in silicon (Si).

图7示出在In-Ga-Zn-O基氧化物半导体(IGZO)中热载流子注入所需的能量。FIG. 7 shows energy required for hot carrier injection in an In-Ga-Zn-O-based oxide semiconductor (IGZO).

图8示出关于短沟道效应的器件模拟的结果。FIG. 8 shows the results of device simulations regarding short channel effects.

图9示出关于短沟道效应的器件模拟的结果。FIG. 9 shows the results of device simulations regarding short channel effects.

图10示出C-V(电容-电压)特性。FIG. 10 shows C-V (capacitance-voltage) characteristics.

图11示出V_G和(1/C)²之间的关系。FIG. 11 shows the relationship between V_G and (1/C)² .

图12A至12D是示出半导体器件的制造工艺的截面图。12A to 12D are cross-sectional views illustrating a manufacturing process of a semiconductor device.

图13A至13D是示出半导体器件的制造工艺的截面图。13A to 13D are cross-sectional views illustrating a manufacturing process of a semiconductor device.

图14A到14C是各自示出半导体器件的截面图。14A to 14C are cross-sectional views each showing a semiconductor device.

图15A到15C是各自示出半导体器件的截面图。15A to 15C are cross-sectional views each showing a semiconductor device.

图16是示出半导体器件的图。FIG. 16 is a diagram illustrating a semiconductor device.

图17A和17B是各自示出半导体器件的截面图。17A and 17B are cross-sectional views each showing a semiconductor device.

图18A至18C是示出半导体器件的制造工艺的截面图。18A to 18C are cross-sectional views illustrating a manufacturing process of a semiconductor device.

图19A至19C是示出半导体器件的制造工艺的截面图。19A to 19C are cross-sectional views illustrating a manufacturing process of a semiconductor device.

图20A至20D是示出半导体器件的制造工艺的截面图。20A to 20D are cross-sectional views illustrating a manufacturing process of a semiconductor device.

图21A到21C是各自示出半导体器件的截面图。21A to 21C are cross-sectional views each showing a semiconductor device.

图22A到22C是各自示出半导体器件的截面图。22A to 22C are cross-sectional views each showing a semiconductor device.

图23A至23F各自示出包括半导体器件的电子设备。23A to 23F each illustrate an electronic device including a semiconductor device.

用于实现本发明的最佳模式Best Mode for Carrying Out the Invention

下文将参考附图描述本发明的实施例的示例。要注意，本发明不限于以下描述，且本领域技术人员将容易理解，可按各种方式改变本发明的方式与细节而不背离本发明的精神与范围。因此，本发明不应被解释为限于以下诸实施例的描述。Hereinafter, examples of embodiments of the present invention will be described with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

注意，为了容易理解起见，附图等所示的每一组件的位置、尺寸、范围等在一些情况下未准确地表示。因此，所公开的发明不一定限于附图等所公开的位置、尺寸、范围等。Note that the position, size, range, and the like of each component shown in the drawings and the like are not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the positions, dimensions, ranges, etc. disclosed in the drawings and the like.

要注意，为了避免组件之间的混淆而在本说明书等中使用诸如“第一”、“第二”和“第三”的序数，这些术语并不在数量上限制组件。It is to be noted that ordinal numbers such as "first", "second" and "third" are used in this specification and the like in order to avoid confusion among components, and these terms do not limit the components in number.

(实施例1)(Example 1)

在本实施例中，根据所公开的本发明的一个实施例的半导体器件的结构和制造方法将参考图1A和1B、图2、图3、图4A和4B、图5到11、图12A到12D、图13A到13D、图14A到14C、图15A到15C、以及图16而描述。In this embodiment, the structure and manufacturing method of a semiconductor device according to an embodiment of the disclosed invention will be referred to FIGS. 1A and 1B , FIG. 2 , FIG. 3 , FIGS. 12D, FIGS. 13A to 13D, FIGS. 14A to 14C, FIGS. 15A to 15C, and FIG. 16 are described.

<半导体器件的结构><Structure of Semiconductor Device>

图1A和1B是各自示出作为半导体器件的结构的示例的晶体管150的截面图。注意，在此晶体管150是n沟道晶体管；可选地，可使用p沟道晶体管。1A and 1B are cross-sectional views each showing a transistor 150 as an example of the structure of a semiconductor device. Note that here transistor 150 is an n-channel transistor; alternatively, a p-channel transistor could be used.

晶体管150包括在衬底100上的氧化物半导体层106a(绝缘层102夹在其之间)、在该氧化物半导体层106a中的结晶区110、电连接至该氧化物半导体层106a的源或漏电极层108a和源或漏电极层108b、覆盖该氧化物半导体层106a、源或漏电极层108a、以及源或漏电极层108b的栅绝缘层112、还有位于栅绝缘层112上的栅电极层114(见图1A和1B)。此处，图1A示出其中源或漏电极层108a和源或漏电极层108b具有层叠结构的情况，且图1B示出其中源或漏电极层108a和源或漏电极层108b具有单层结构的情况。注意，在单层结构的情况下，易于实现良好的楔形。The transistor 150 includes an oxide semiconductor layer 106a with the insulating layer 102 interposed therebetween on the substrate 100, a crystallization region 110 in the oxide semiconductor layer 106a, a source or a source electrically connected to the oxide semiconductor layer 106a. The drain electrode layer 108a and the source or drain electrode layer 108b, the gate insulating layer 112 covering the oxide semiconductor layer 106a, the source or drain electrode layer 108a, and the source or drain electrode layer 108b, and the gate insulating layer 112 on the gate insulating layer 112. Electrode layer 114 (see FIGS. 1A and 1B ). Here, FIG. 1A shows a case where the source or drain electrode layer 108a and the source or drain electrode layer 108b have a laminated structure, and FIG. 1B shows a case where the source or drain electrode layer 108a and the source or drain electrode layer 108b have a single-layer structure Case. Note that a good wedge shape is easy to achieve in the case of a single layer structure.

此外，层间绝缘层116和层间绝缘层118被提供在晶体管150上。注意，层间绝缘层116和层间绝缘层118并不是必须的组件且因此合适时可被省略。In addition, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150 . Note that the interlayer insulating layer 116 and the interlayer insulating layer 118 are not essential components and thus may be omitted as appropriate.

对于氧化物半导体层106a，可使用如下材料中的任意：四组分金属氧化物，如In-Sn-Ga-Zn-O基材料；三组分金属氧化物，如In-Ga-Zn-O基材料、In-Sn-Zn-O基材料、In-Al-Zn-O基材料、Sn-Ga-Zn-O基材料、Al-Ga-Zn-O基材料、和Sn-Al-Zn-O基材料；二组分金属氧化物，如In-Zn-O基材料、Sn-Zn-O基材料、Al-Zn-O基材料、Zn-Mg-O基材料、Sn-Mg-O基材料、和In-Mg-O基材料；单组分金属氧化物，如In-O基材料、Sn-O基材料、和Zn-O基材料；等等。For the oxide semiconductor layer 106a, any of the following materials can be used: four-component metal oxides such as In-Sn-Ga-Zn-O-based materials; three-component metal oxides such as In-Ga-Zn-O base material, In-Sn-Zn-O base material, In-Al-Zn-O base material, Sn-Ga-Zn-O base material, Al-Ga-Zn-O base material, and Sn-Al-Zn- O-based materials; two-component metal oxides, such as In-Zn-O-based materials, Sn-Zn-O-based materials, Al-Zn-O-based materials, Zn-Mg-O-based materials, Sn-Mg-O-based materials materials, and In-Mg-O-based materials; single-component metal oxides, such as In-O-based materials, Sn-O-based materials, and Zn-O-based materials; and so on.

特定地，当没有电场且因此截止态电流可被充分减少时，In-Ga-Zn-O-基氧化物半导体材料具有足够高的电阻。此外，In-Ga-Zn-O-基氧化物半导体材料还具有高场效应迁移率，适合于被用在半导体器件中的半导体材料。Specifically, the In-Ga-Zn-O-based oxide semiconductor material has sufficiently high resistance when there is no electric field and thus off-state current can be sufficiently reduced. In addition, In-Ga-Zn-O-based oxide semiconductor materials also have high field-effect mobility and are suitable for semiconductor materials used in semiconductor devices.

给出用InGaO₃(ZnO)_m(m＞0)表示的氧化物半导体材料作为In-Ga-Zn-O-基氧化物半导体材料的典型示例。使用M代替Ga，有用InMO₃(ZnO)_m(m＞0)表示的氧化物半导体材料。此处，M表示从镓(Ga)、铝(Al)、铁(Fe)、镍(Ni)、锰(Mn)钴(Co)等中选择的一种或多种金属元素。例如，M可以是Ga、Ga和Al、Ga和Fe、Ga和Ni、Ga和Mn、Ga和Co等等。注意，上述组合物是从氧化物半导体材料可具有的晶体结构中导出的且仅仅是示例。An oxide semiconductor material represented by InGaO₃ (ZnO)_m (m>0) is given as a typical example of the In-Ga-Zn-O-based oxide semiconductor material. Using M instead of Ga, there is an oxide semiconductor material represented by InMO₃ (ZnO)_m (m>0). Here, M represents one or more metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), and the like. For example, M may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, and the like. Note that the above composition is derived from the crystal structure that an oxide semiconductor material can have and is only an example.

氧化物半导体层106a优选地是通过从中充分移除诸如氢之类的杂质并向其提供氧而被高度提纯的氧化物半导体层。具体地，氧化物半导体层106a中的氢浓度为5×10¹⁹/cm³或更小、优选为5×10¹⁸/cm³或更小、更优选为5×10¹⁷/cm³或更小。注意，通过充分减少氢浓度并提供氧而被提纯的氧化物半导体层106a具有充分低于向其添加了杂质元素的硅的密度(约1×10¹⁴/cm³)的载流子密度(如，小于1×10¹²/cm³，优选地小于1.45×10¹⁰/cm³)。可通过使用这样的i-型或基本i-型的氧化物半导体层来获得具有优良截止状态电流特性的晶体管150。例如，当漏电压V_D为+1V或+10V而栅电压V_G被设置在-5V至-20V的范围内时，截止态电流1×10^-13A或更小。注意，上述氧化物半导体层106a中的氢浓度通过二次离子质谱法(SIMS)来测量。The oxide semiconductor layer 106 a is preferably an oxide semiconductor layer highly purified by sufficiently removing impurities such as hydrogen therefrom and supplying oxygen thereto. Specifically, the hydrogen concentration in the oxide semiconductor layer 106a is 5×10¹⁹ /cm³ or less, preferably 5×10¹⁸ /cm³ or less, more preferably 5×10¹⁷ /cm³ or less . Note that the^oxide semiconductor layer^106a purified by sufficiently reducing the hydrogen concentration and supplying oxygen has a carrier density (such as , less than 1×10¹² /cm³ , preferably less than 1.45×10¹⁰ /cm³ ). The transistor 150 having excellent off-state current characteristics can be obtained by using such an i-type or substantially i-type oxide semiconductor layer. For example, when the drain voltage V_D is +1 V or +10 V and the gate voltage V_G is set in the range of -5 V to -20 V, the off-state current is 1×10⁻¹³ A or less. Note that the hydrogen concentration in the above-described oxide semiconductor layer 106a is measured by secondary ion mass spectrometry (SIMS).

此处，氧化物半导体层106a包括结晶区110。该区域对应于包含氧化物半导体层106a的表面的区域，换言之，包含与栅绝缘层112相接触的部分的区域。Here, the oxide semiconductor layer 106 a includes a crystalline region 110 . This region corresponds to a region including the surface of the oxide semiconductor layer 106 a , in other words, a region including a portion in contact with the gate insulating layer 112 .

结晶区110优选地包括其c-轴与基本垂直于氧化物半导体层106a的表面的方向对齐的晶体。例如，结晶区110可以是包括其c-轴与基本垂直于氧化物半导体层106a的表面的方向对齐的晶粒的区域。此处，“基本垂直”意味着与垂直方向在±10°范围内。注意，结晶区110可仅在氧化物半导体层106a的表面附近形成(如，从表面延伸至距离(深度)10nm或更少的区域)，或者可被形成为达到氧化物半导体层106a的后表面。The crystallized region 110 preferably includes a crystal whose c-axis is aligned with a direction substantially perpendicular to the surface of the oxide semiconductor layer 106a. For example, the crystalline region 110 may be a region including crystal grains whose c-axis is aligned with a direction substantially perpendicular to the surface of the oxide semiconductor layer 106a. Here, "substantially perpendicular" means within ±10° from the vertical direction. Note that the crystalline region 110 may be formed only near the surface of the oxide semiconductor layer 106a (for example, a region extending from the surface to a distance (depth) of 10 nm or less), or may be formed to reach the rear surface of the oxide semiconductor layer 106a .

此外，结晶区110优选地包括平板式晶体。此处，平板式晶体意味着以平面形式生长的结晶且具有像薄板一样的形状。此外，结晶区的厚度优选为2nm到10nm。In addition, the crystallization region 110 preferably includes flat crystals. Here, the tabular crystal means a crystal grown in a planar form and having a shape like a thin plate. In addition, the thickness of the crystalline region is preferably 2 nm to 10 nm.

注意，氧化物半导体层106a可具有包括上述材料的非晶结构和非单晶结构(包括微晶结构、多晶结构等)。另一方面，结晶区110优选地具有非单晶结构等。优选的是至少结晶区110相比氧化物半导体层106a中的其他区域具有更高的结晶度。Note that the oxide semiconductor layer 106a may have an amorphous structure and a non-single crystal structure (including a microcrystalline structure, a polycrystalline structure, etc.) including the above materials. On the other hand, the crystalline region 110 preferably has a non-single crystal structure or the like. It is preferable that at least the crystalline region 110 has higher crystallinity than other regions in the oxide semiconductor layer 106a.

通过如上所述地包括结晶区110，氧化物半导体层106a可具有电各向异性。By including the crystalline region 110 as described above, the oxide semiconductor layer 106a can have electrical anisotropy.

注意，氧化物半导体层106a的表面优选地在沟道形成区(与栅电极层交迭的区域)中具有至少预确定的平面度。例如，氧化物半导体层106a的表面的高度差异在沟道形成区中为1nm或更少(优选地，为0.2nm或更少)。当氧化物半导体层106a的结晶区110用多晶等形成时，在一些情况下，相邻晶粒不具有相同的a-b平面。换言之，在一些情况下，与晶粒的a-轴和b-轴平行的层之间有差异。这样的差异可导致电导率的下降。因此，在沟道形成区中，与a-轴和b-轴平行的层优选地是相同的。Note that the surface of the oxide semiconductor layer 106a preferably has at least a predetermined flatness in the channel formation region (region overlapping with the gate electrode layer). For example, the difference in height of the surface of the oxide semiconductor layer 106a is 1 nm or less (preferably, 0.2 nm or less) in the channel formation region. When the crystallized region 110 of the oxide semiconductor layer 106a is formed of polycrystal or the like, adjacent crystal grains do not have the same a-b plane in some cases. In other words, in some cases, there is a difference between layers parallel to the a-axis and b-axis of the crystal grains. Such differences can lead to a drop in conductivity. Therefore, in the channel formation region, layers parallel to the a-axis and b-axis are preferably the same.

如上所述，使用被提纯且包括结晶区110的氧化物半导体层106a，可实现具有良好电特性的半导体器件。As described above, using the oxide semiconductor layer 106a that is purified and includes the crystalline region 110, a semiconductor device having good electrical characteristics can be realized.

此外，结晶区110相比氧化物半导体层106a中的其他区域是稳定的，且因此可防止杂质(如，水分等)进入氧化物半导体层106a。因此，可改进氧化物半导体层106a的可靠性。此外，由于结晶区110相比氧化物半导体层106a中的其他区域是稳定的，使用这个部分作为沟道形成区，可获得稳定的晶体管特性。In addition, the crystalline region 110 is stable compared to other regions in the oxide semiconductor layer 106a, and thus can prevent impurities (eg, moisture, etc.) from entering the oxide semiconductor layer 106a. Therefore, the reliability of the oxide semiconductor layer 106a can be improved. Furthermore, since the crystalline region 110 is stable compared to other regions in the oxide semiconductor layer 106a, using this portion as a channel formation region, stable transistor characteristics can be obtained.

下文中，将简略地描述氧化物半导体提纯导致氧化物半导体成为本征(i-型)氧化物半导体的意义、在半导体器件中使用氧化物半导体的优势等。Hereinafter, the significance of refining an oxide semiconductor to cause an oxide semiconductor to become an intrinsic (i-type) oxide semiconductor, advantages of using an oxide semiconductor in a semiconductor device, and the like will be briefly described.

<本征氧化物半导体的实现><Realization of Intrinsic Oxide Semiconductor>

对于氧化物半导体的性质，诸如态密度(DOS)，已经做了可观的研究；然而，研究并不包括充分地减少缺陷状态本身的理念。根据所公开的发明的实施例，通过从氧化物半导体中移除可能成为增加DOS的原因的水分或氢而制造被提纯的、本征(i-型)氧化物半导体。这是基于充分减少DOS本身的理念。由此，可制造优良的工业产品。Considerable research has been done on the properties of oxide semiconductors, such as the density of states (DOS); however, the research does not include the idea of sufficiently reducing the defect states themselves. According to an embodiment of the disclosed invention, a purified, intrinsic (i-type) oxide semiconductor is produced by removing moisture or hydrogen, which may be a cause of increased DOS, from the oxide semiconductor. This is based on the idea of substantially reducing DOS itself. Thereby, an excellent industrial product can be manufactured.

注意，在氢、水等被移除的同时可移除氧。因此，优选的是以将氧提供至由缺氧产生的金属悬空键的方式来实现进一步被提纯的、本征(i-型)氧化物半导体，从而减少了由于缺氧引起的DOS。例如，在与沟道形成区紧密接触处形成氧过量氧化物膜，且在约200℃到400℃的温度(一般是250℃)执行热处理，藉此可从该氧化物膜提供氧并可减少由于缺氧引起的DOS。在下文所描述的第一到第三热处理过程中，惰性气体可被转换为包括氧的气体。进一步，在第一到第三热处理之后，通过在氧气氛或其中充分减少了氢、水等的气氛的降温过程，可将氧提供给氧化物半导体。Note that oxygen may be removed at the same time as hydrogen, water, etc. are removed. Therefore, it is preferable to realize a further purified, intrinsic (i-type) oxide semiconductor in such a manner that oxygen is supplied to metal dangling bonds generated by oxygen deficiency, thereby reducing DOS due to oxygen deficiency. For example, an oxygen-excess oxide film is formed in close contact with a channel formation region, and heat treatment is performed at a temperature of about 200°C to 400°C (typically 250°C), whereby oxygen can be supplied from the oxide film and can be reduced. DOS due to hypoxia. During the first to third heat treatments described below, the inert gas may be switched to a gas including oxygen. Further, after the first to third heat treatments, oxygen can be supplied to the oxide semiconductor through a temperature-lowering process in an oxygen atmosphere or an atmosphere in which hydrogen, water, or the like is sufficiently reduced.

可认为引起氧化物半导体特性的劣化的因素是归因于过量氢在导带之下0.1eV到0.2eV的浅能级、由于缺氧引起的深能级、等。彻底消除氢且充分地供氧以消除这种缺陷的技术理念将会是正确的。It is considered that factors causing deterioration of oxide semiconductor characteristics are shallow levels attributable to excess hydrogen at 0.1 eV to 0.2 eV below the conduction band, deep levels due to oxygen deficiency, and the like. The technical concept of eliminating hydrogen completely and supplying oxygen sufficiently to eliminate this defect would be correct.

氧化物半导体一般被认为是n-型半导体；然而，根据所公开的发明的实施例，通过移除诸如水或氢之类的杂质并提供作为氧化物半导体的组成元素的氧来实现i-型氧化物半导体。在这个方面，可以说，所公开发明的一个实施例包括新颖的技术理念，因为它不是诸如通过添加杂质元素而获得的硅之类的i型半导体。An oxide semiconductor is generally considered to be an n-type semiconductor; however, according to an embodiment of the disclosed invention, the i-type is realized by removing impurities such as water or hydrogen and providing oxygen as a constituent element of the oxide semiconductor oxide semiconductor. In this regard, it can be said that one embodiment of the disclosed invention includes a novel technical idea because it is not an i-type semiconductor such as silicon obtained by adding an impurity element.

<优于其他半导体材料的工艺上的优势><Process advantages over other semiconductor materials>

可给出氮化硅(如，4H-SiC)等作为可与氧化物半导体相比的半导体材料。氧化物半导体和4H-SiC具有一些共同特征。载流子密度是其中一个示例。根据费米-狄拉克分布，氧化物半导体中的少数载流子的密度被估计为约10^-7/cm³。少数载流子密度的该值极小，与4H-SiC中的类似，为6.7×10^-11/cm³。相比硅的本征载流子密度(约1.45×10¹⁰/cm³)，可理解的是这个程度极低。Silicon nitride (eg, 4H-SiC) or the like can be given as a semiconductor material comparable to an oxide semiconductor. Oxide semiconductors and 4H-SiC share some common features. Carrier density is one example. From the Fermi-Dirac distribution, the density of minority carriers in an oxide semiconductor is estimated to be about 10^-7 /cm³ . This value of the minority carrier density is extremely small, 6.7×10^-11 /cm³ similar to that in 4H-SiC. Compared to the intrinsic carrier density of silicon (approximately 1.45×10¹⁰ /cm³ ), this level is understandably very low.

此外，氧化物半导体的能带隙为3.0eV至3.5eV，而4H-SiC的能带隙为3.26eV。因此，氧化物半导体和碳化硅的相似之处在于，它们都是宽带隙半导体。In addition, the energy band gap of the oxide semiconductor is 3.0 eV to 3.5 eV, while the energy band gap of 4H-SiC is 3.26 eV. Therefore, oxide semiconductors and silicon carbide are similar in that they are both wide bandgap semiconductors.

另一方面，氧化物半导体和碳化硅之间存在一重大差异，即，处理温度。一般而言，当使用碳化硅时，需要在1500℃到2000℃的加热处理。在这样高的温度，半导体衬底、半导体元件等被损坏，且因此，难以在使用氮化硅之外的半导体材料的半导体元件上形成使用碳化硅的半导体元件。另一方面，通过在850℃或更低，优选地750℃或更低的热处理可获得氧化物半导体。因此，在使用另一种半导体材料形成集成电路后，可能使用氧化物半导体形成半导体元件。On the other hand, there is a major difference between oxide semiconductors and silicon carbide, namely, processing temperature. In general, when silicon carbide is used, heat treatment at 1500°C to 2000°C is required. At such a high temperature, a semiconductor substrate, a semiconductor element, and the like are damaged, and therefore, it is difficult to form a semiconductor element using silicon carbide over a semiconductor element using a semiconductor material other than silicon nitride. On the other hand, an oxide semiconductor can be obtained by heat treatment at 850°C or lower, preferably 750°C or lower. Therefore, after forming an integrated circuit using another semiconductor material, it is possible to form a semiconductor element using an oxide semiconductor.

在使用氧化物半导体的情况下，存在可能使用诸如玻璃衬底之类的具有低耐热性的衬底的优势，这不同于使用碳化硅的情况。另外，还存在不需要高温热处理的优势，因此相比碳化硅，可充分减少能耗。进一步，在碳化硅中，晶体缺陷或非故意地被引入碳化硅的小量杂质是导致产生载流子的因素。理论上，在碳化硅的情况下可获得与本发明的氧化物半导体的载流子密度一样的较低载流子密度；然而，由于上面给出的理由，实践中难以获得小于10¹²/cm³的载流子密度。对于氧化物半导体和也已知作为宽带隙半导体的氮化镓之间的比较也是一样的。In the case of using an oxide semiconductor, there is an advantage that it is possible to use a substrate having low heat resistance such as a glass substrate, unlike the case of using silicon carbide. In addition, there is an advantage that high-temperature heat treatment is not required, so energy consumption can be substantially reduced compared to silicon carbide. Further, in silicon carbide, crystal defects or a small amount of impurities unintentionally introduced into silicon carbide are factors that cause generation of carriers. Theoretically, in the case of silicon carbide, a carrier density as low as that of the oxide semiconductor of the present invention can be obtained; however, it is difficult to obtain less than 10¹² /cm in practice for the reasons given above.³ carrier density. The same is true for the comparison between an oxide semiconductor and gallium nitride which is also known as a wide bandgap semiconductor.

<包括氧化物半导体的晶体管的导电机制><Conduction Mechanism of Transistor Including Oxide Semiconductor>

将参考图2、图3、图4A和4B、以及图5来描述包括氧化物半导体的晶体管的导电机制。注意，以下描述基于容易理解的理想情形的假设，并且不一定反映真实情形。还要注意以下描述仅是一种考虑。A conduction mechanism of a transistor including an oxide semiconductor will be described with reference to FIG. 2 , FIG. 3 , FIGS. 4A and 4B , and FIG. 5 . Note that the following descriptions are based on assumptions of ideal situations that are easy to understand and do not necessarily reflect real situations. Note also that the following description is a consideration only.

图2是包括氧化物半导体的晶体管(薄膜晶体管)的截面图。氧化物半导体层(OS)提供在栅电极(GE1)上，栅绝缘层(GI)夹在其中间。源电极(S)和漏电极(D)设置在该栅电极(GE1)上。绝缘层被设置成覆盖源电极(S)和漏电极(D)。FIG. 2 is a cross-sectional view of a transistor (thin film transistor) including an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate electrode (GE1) with a gate insulating layer (GI) interposed therebetween. A source electrode (S) and a drain electrode (D) are provided on the gate electrode (GE1). An insulating layer is provided to cover the source electrode (S) and the drain electrode (D).

图3是图2中的A-A’截面的能带图(示意图)。在图3中，黑色圆圈(●)和白色圆圈(○)表示电子和空穴，并且分别具有电荷(-q，+q)。正电压(V_D＞0)施加给漏电极，虚线示出没有电压施加至栅电极(V_G＝0)的情况而实线示出正电压施加至栅电极(V_G＞0)的情况。在未向栅电极施加电压的情况下，由于高电位势垒，载流子(电子)未从电极注入氧化物半导体侧，从而电流不流动，这意味着截止状态。另一方面，当向栅电极施加正电压时，电位垒势降低，并且由此电流流动，这意味着导通状态。FIG. 3 is an energy band diagram (schematic diagram) of the AA' section in FIG. 2 . In FIG. 3 , black circles (●) and white circles (◯) represent electrons and holes, and have charges (−q, +q), respectively. A positive voltage (V_D >0) is applied to the drain electrode, a dashed line shows the case of no voltage applied to the gate electrode (V_G =0) and a solid line shows the case of a positive voltage applied to the gate electrode (V_G >0). When no voltage is applied to the gate electrode, carriers (electrons) are not injected from the electrode to the oxide semiconductor side due to a high potential barrier, so that current does not flow, which means an off state. On the other hand, when a positive voltage is applied to the gate electrode, the potential barrier decreases, and thus current flows, which means an on state.

图4A和4B是图2中的B-B’截面的能带图(示意图)。图4A示出其中正电压(V_G＞0)被施加到栅电极(GE1)并且载流子(电子)在源电极和漏电极之间流动的导通状态。图4B示出其中负电压(V_G＜0)被施加到栅电极(GE1)而少数载流子不流动的截止状态。4A and 4B are energy band diagrams (schematic diagrams) of the BB' section in FIG. 2 . FIG. 4A shows a conduction state in which a positive voltage (V_G >0) is applied to the gate electrode (GE1) and carriers (electrons) flow between the source electrode and the drain electrode. FIG. 4B shows an off state in which a negative voltage (V_G <0) is applied to the gate electrode ( GE1 ) and minority carriers do not flow.

图5示出真空能级和金属的功函数(φ_M)之间、以及真空能级和氧化物半导体的电子亲和力(χ)之间的关系。FIG. 5 shows the relationship between the vacuum level and the work function (φ_M ) of a metal, and between the vacuum level and the electron affinity (χ) of an oxide semiconductor.

在常温下，金属中的电子被简并，并且费米能级位于导带中。另一方面，常规氧化物半导体是n型氧化物半导体，其中费米能级(E_F)远离位于带隙中间的本征费米能级(E_i)，并且位于更接近导带处。注意，已知氢的部分是氧化物半导体中的施主，并且是使氧化物半导体成为n型氧化物半导体的一个因素。At normal temperature, electrons in metals are degenerated, and the Fermi level is located in the conduction band. On the other hand, a conventional oxide semiconductor is an n-type oxide semiconductor in which the Fermi level (_EF ) is far from the intrinsic Fermi level (E_i ) located in the middle of the band gap, and is located closer to the conduction band. Note that a portion of hydrogen is known to be a donor in an oxide semiconductor, and is a factor that makes an oxide semiconductor an n-type oxide semiconductor.

另一方面，根据所公开的发明的一个实施例的氧化物半导体是本征(i型)或基本本征的氧化物半导体，其通过从氧化物半导体中去除作为n型氧化物半导体的因素的氢以及纯化氧化物半导体(从而尽可能防止氧化物半导体的主要组分之外的元素(即，杂质元素)被包含在内)而获得的。换句话说，特征在于，经提纯的i型(本征)半导体、或接近其的半导体不是通过添加杂质元素、而是通过尽可能地去除杂质(诸如氢或水)来获取的。由此，费米能级(E_F)可与本征费米能级(E_i)相当。On the other hand, the oxide semiconductor according to one embodiment of the disclosed invention is an intrinsic (i-type) or substantially intrinsic oxide semiconductor obtained by removing a factor that is an n-type oxide semiconductor from the oxide semiconductor. Hydrogen and purification of the oxide semiconductor so as to prevent inclusion of elements other than the main components of the oxide semiconductor (ie, impurity elements) as much as possible. In other words, it is characterized in that a purified i-type (intrinsic) semiconductor, or a semiconductor close thereto, is obtained not by adding impurity elements but by removing impurities such as hydrogen or water as much as possible. Thus, the Fermi level (_EF ) is comparable to the intrinsic Fermi level (E_i ).

可以说，氧化物半导体的能隙(E_g)为3.15eV，而电子亲和力(χ)为4.3V。源电极和漏电极中所包括的钛(Ti)的功函数基本上等于氧化物半导体的电子亲和力(χ)。在此情况下，在金属和氧化物半导体之间的界面处不形成电子的肖特基势垒。It can be said that the energy gap (E_g ) of the oxide semiconductor is 3.15 eV, and the electron affinity (χ) is 4.3V. The work function of titanium (Ti) included in the source and drain electrodes is substantially equal to the electron affinity (χ) of the oxide semiconductor. In this case, a Schottky barrier for electrons is not formed at the interface between the metal and the oxide semiconductor.

此时，如图4A所示，电子在栅绝缘层和经提纯的氧化物半导体之间的界面附近(在能量方面是稳定的氧化物半导体的最低部分)移动。At this time, as shown in FIG. 4A , electrons move in the vicinity of the interface between the gate insulating layer and the purified oxide semiconductor (the lowest portion of the oxide semiconductor that is energetically stable).

另外，如图4B中所示，当向栅电极(GE1)施加负电位时，电流值极接近于零，因为作为少数载流子的空穴基本上为零。In addition, as shown in FIG. 4B, when a negative potential is applied to the gate electrode (GE1), the current value is extremely close to zero because holes as minority carriers are substantially zero.

以此方式，通过提纯以尽可能少地包含除其主要元素以外的元素(即，杂质元素)，获取本征(i-型)或基本本征的氧化物半导体。由此，氧化物半导体和栅绝缘层之间的界面的特性变得明显。为此，栅绝缘层需要形成与氧化物半导体的良好界面。具体地，优选使用，例如，通过使用用在VHF带到微波带的范围内的电源频率生成的高密度等离子体的CVD法而形成的绝缘层、通过溅射法形成的绝缘层、等等。In this way, an intrinsic (i-type) or substantially intrinsic oxide semiconductor is obtained by refining to contain elements other than its main elements (ie, impurity elements) as little as possible. Thereby, the characteristics of the interface between the oxide semiconductor and the gate insulating layer become apparent. For this reason, the gate insulating layer needs to form a good interface with the oxide semiconductor. Specifically, it is preferable to use, for example, an insulating layer formed by a CVD method using high-density plasma generated with a power supply frequency in the range of the VHF band, an insulating layer formed by a sputtering method, or the like.

当氧化物半导体被提纯且氧化物半导体和栅绝缘层之间的界面变为良好时，在晶体管具有1×10⁴μm的沟道宽度(W)和3μm的沟道长度(L)的情况下，例如，有可能实现诸如10^-13A或更小的截止态电流、以及0.1V/dec的子阈值摆动(S值)(具有100nm厚的栅绝缘层)之类的特性。When the oxide semiconductor is purified and the interface between the oxide semiconductor and the gate insulating layer becomes good, in the case of a transistor having a channel width (W) of 1×10⁴ μm and a channel length (L) of 3 μm , for example, it is possible to realize characteristics such as an off-state current of 10⁻¹³ A or less, and a sub-threshold swing (S value) of 0.1 V/dec (with a gate insulating layer 100 nm thick).

如上所述，氧化物半导体被提纯为尽可能少地包含除其主要元素以外的元素(即，杂质元素)，从而薄膜晶体管可以良好的方式操作。As described above, an oxide semiconductor is purified to contain elements other than its main elements (ie, impurity elements) as little as possible, so that a thin film transistor can operate in a good manner.

<包括氧化物半导体的晶体管对于热载流子衰减的抵抗><Resistance of Transistor Including Oxide Semiconductor to Hot Carrier Decay>

接着，将参考图6以及图7而描述包括氧化物半导体的晶体管对于热载流子衰减的抵抗。注意，以下描述基于容易理解的理想情形的假设，并且不一定反映真实情形。还要注意以下描述仅是一种考虑。Next, resistance of a transistor including an oxide semiconductor to hot carrier decay will be described with reference to FIGS. 6 and 7 . Note that the following descriptions are based on assumptions of ideal situations that are easy to understand and do not necessarily reflect real situations. Note also that the following description is a consideration only.

热载流子衰减的主要原因是沟道热电子注入(CHE注入)以及漏极雪崩热载流子注入(DAHC注入)。注意，以下为简洁起见仅考虑电子。The main causes of hot carrier decay are channel hot electron injection (CHE injection) and drain avalanche hot carrier injection (DAHC injection). Note that only electrons are considered below for brevity.

CHE注入是指其中具有高于半导体层中的栅绝缘层的势垒的增益能量(gained energy)的电子被注入栅绝缘层等中的现象。电子通过被低电场加速而增益能量。CHE injection refers to a phenomenon in which electrons having a gained energy higher than the potential barrier of a gate insulating layer in a semiconductor layer are injected into a gate insulating layer or the like. Electrons gain energy by being accelerated by a low electric field.

DAHC注入是指其中由高电场加速的电子的碰撞而产生的电子被注入栅绝缘层等中的现象。DAHC注入和CHE注入之间的差异在于它们是否涉及由碰撞电离引起的雪崩击穿。注意，DAHC注入需要具有高于或等于半导体带隙的动能的电子。DAHC injection refers to a phenomenon in which electrons generated by collision of electrons accelerated by a high electric field are injected into a gate insulating layer or the like. The difference between DAHC injection and CHE injection is whether they involve avalanche breakdown caused by impact ionization. Note that DAHC injection requires electrons with kinetic energy higher than or equal to the semiconductor bandgap.

图6和图7示出从硅(Si)和In-Ga-Zn-O-基氧化物半导体(IGZO)的能带结构中估算出来的每一个热载流子注入所需要的能量。图6和图7在左边示出CHE注入，且在右边示出DAHC注入。6 and 7 show the energy required for each hot carrier injection estimated from the energy band structures of silicon (Si) and In-Ga-Zn-O-based oxide semiconductor (IGZO). Figures 6 and 7 show CHE implants on the left and DAHC implants on the right.

关于硅，DAHC注入所引起的衰减比CHE注入引起的衰减更严重。这是因为硅具有较窄的能带隙且易于在其中发生雪崩击穿。因为在硅中没有碰撞而被加速的载流子(电子)非常少，因此CHE注入的可能性非常低。另一方面，雪崩击穿增加了能穿过栅绝缘层的势垒的电子的数量，且这样增加了被注入栅绝缘层的电子的数量。Regarding silicon, the attenuation caused by DAHC implants is more severe than that caused by CHE implants. This is because silicon has a narrow energy band gap and is prone to avalanche breakdown in it. Since there are very few carriers (electrons) that are accelerated without collisions in silicon, the possibility of CHE injection is very low. On the other hand, avalanche breakdown increases the number of electrons that can pass through the potential barrier of the gate insulating layer, and thus increases the number of electrons injected into the gate insulating layer.

关于In-Ga-Zn-O-基氧化物半导体，由于宽带隙，CHE注入所需要的能量与硅的情况中所需要的能量没有很大不同，且DAHC注入所需要的能量基本等于CHE注入所需要的能量。换言之，DAHC注入的可能性较低。Regarding In-Ga-Zn-O-based oxide semiconductors, due to the wide bandgap, the energy required for CHE implantation is not much different from that required in the case of silicon, and the energy required for DAHC implantation is substantially equal to that required for CHE implantation. energy required. In other words, the possibility of DAHC injection is low.

另一方面，与硅类似，没有碰撞而被加速的载流子(电子)非常少，因此CHE注入的可能性非常低。换言之，In-Ga-Zn-O-基氧化物半导体相比硅对抗热载流子衰减具有更高的抵抗力。On the other hand, similarly to silicon, there are very few carriers (electrons) that are accelerated without collisions, so the possibility of CHE injection is very low. In other words, the In-Ga-Zn-O-based oxide semiconductor has higher resistance against hot carrier decay than silicon.

<包括氧化物半导体的晶体管中的短沟道效应><Short Channel Effect in Transistors Including Oxide Semiconductors>

接着，将参考图8和图9而描述包括氧化物半导体的晶体管中的短沟道效应。注意，以下描述基于容易理解的理想情形的假设，并且不一定反映真实情形。还要注意以下描述仅是一种考虑。Next, the short channel effect in a transistor including an oxide semiconductor will be described with reference to FIGS. 8 and 9 . Note that the following descriptions are based on assumptions of ideal situations that are easy to understand and do not necessarily reflect real situations. Note also that the following description is a consideration only.

短沟道效应是指随着晶体管的小型化(沟道长度(L)减少)而变得明显的电特性的衰减。短沟道效应源自漏极在源极上的影响。短沟道效应的特定示例是阈值电压的减少、子阈值摆动(S值)的增加、漏电流的增加等。The short-channel effect refers to attenuation of electrical characteristics that becomes conspicuous as transistors are miniaturized (channel length (L) decreases). The short channel effect arises from the effect of the drain on the source. Specific examples of short-channel effects are decrease in threshold voltage, increase in sub-threshold swing (S value), increase in leakage current, and the like.

此处，通过器件模拟而检验能抑制短沟道效应的结构。特定地，制备了四种模型，每一个具有不同的载流子密度和不同的氧化物半导体层的厚度，检查了沟道长度(L)和阈值电压(V_th)之间的关系。采用底栅晶体管作为模型，在每一个底栅晶体管中，载流子密度为1.7×10^-8/cm³或1.0×10¹⁵/cm³且氧化物半导体层具有1μm或30nm的厚度。注意，为氧化物半导体层使用In-Ga-Zn-O基氧化物半导体，且使用具有100nm厚度的氧氮化硅膜作为栅绝缘层。Here, a structure capable of suppressing the short-channel effect was examined by device simulation. Specifically, four models were prepared, each having a different carrier density and a different thickness of the oxide semiconductor layer, and the relationship between the channel length (L) and the threshold voltage (V_th ) was examined. Using bottom-gate transistors as models, in each of the bottom-gate transistors, the carrier density is 1.7×10⁻⁸ /cm³ or 1.0×10¹⁵ /cm³ and the oxide semiconductor layer has a thickness of 1 μm or 30 nm. Note that an In-Ga-Zn-O-based oxide semiconductor is used for the oxide semiconductor layer, and a silicon oxynitride film having a thickness of 100 nm is used as the gate insulating layer.

注意，在顶栅晶体管和底栅晶体管之间的计算结果没有很大差异。Note that the calculated results do not differ greatly between top-gate and bottom-gate transistors.

图8和图9示出计算结果。图8示出其中载流子密度为1.7×10^-8/cm³的情况，图9示出其中载流子密度为1.0×10¹⁵/cm³的情况。结果显示，通过减少氧化物半导体层的厚度，在包括氧化物半导体的晶体管中可抑制短沟道效应。例如，在沟道长度(L)为约1μm的情况下，即使是使用具有足够低的载流子密度的氧化物半导体层，可理解的是，当氧化物半导体层的厚度被设置为约3nm至50nm时，优选3nm至20nm时，可充分抑制短沟道效应。8 and 9 show calculation results. FIG. 8 shows the case where the carrier density is 1.7×10^-8 /cm³ , and FIG. 9 shows the case where the carrier density is 1.0×10¹⁵ /cm³ . The results showed that the short channel effect can be suppressed in a transistor including an oxide semiconductor by reducing the thickness of the oxide semiconductor layer. For example, in the case where the channel length (L) is about 1 μm, even if an oxide semiconductor layer having a sufficiently low carrier density is used, it is understood that when the thickness of the oxide semiconductor layer is set to about 3 nm When the thickness is 50 nm, preferably 3 nm to 20 nm, the short channel effect can be sufficiently suppressed.

<氧化物半导体的载流子密度><Carrier Density of Oxide Semiconductor>

根据所公开的发明的技术理念是通过充分地减少氧化物半导体层中的载流子密度，制成尽可能接近于本征(i-型)氧化物半导体层的氧化物半导体层。将参考图10和图11而描述用于计算氧化物半导体层的载流子密度的方法以及实际测得的载流子密度。The technical idea according to the disclosed invention is to make an oxide semiconductor layer as close as possible to an intrinsic (i-type) oxide semiconductor layer by sufficiently reducing the carrier density in the oxide semiconductor layer. A method for calculating the carrier density of the oxide semiconductor layer and the actually measured carrier density will be described with reference to FIGS. 10 and 11 .

制造包括氧化物半导体层的MOS电容器，并估算该MOS电容器的C-V(电容-电压)测量结果(C-V特性)，以此方式来计算氧化物半导体层的载流子密度。The carrier density of the oxide semiconductor layer was calculated in such a manner that a MOS capacitor including an oxide semiconductor layer was fabricated and a C-V (capacitance-voltage) measurement result (C-V characteristic) of the MOS capacitor was evaluated.

根据如下步骤(1)到(3)而测量该载流子密度：(1)通过绘制MOS电容器的栅电压V_g和电容C之间的关系来获得C-V特性；(2)使用该C-V特性来获得示出栅电压V_g和(1/C)²之间的关系的图，且获得在该图的弱反型区中的(1/C)²的微分值；以及(3)将所获得的该微分值代入公式1中，公式1如下所示，其表示载流子密度(N_d)。注意，公式1中的e、ε₀、以及ε分别代表氧化物半导体的基本电荷、真空电容率、以及相对电容率。The carrier density is measured according to the following steps (1) to (3): (1) obtain the CV characteristic by plotting the relationship between the gate voltage V_g and the capacitance C of the MOS capacitor; (2) use the CV characteristic to obtaining a graph showing the relationship between the gate voltage V_g and (1/C)² , and obtaining a differential value of (1/C)² in the weak inversion region of the graph; and (3) obtaining the obtained This differential value of is substituted into Equation 1, which is shown below, which represents the carrier density (N_d ). Note that e, ε₀ , and ε in Formula 1 represent the elementary charge, vacuum permittivity, and relative permittivity of the oxide semiconductor, respectively.

[公式1][Formula 1]

${\mathrm{<span><span>N</span>N</span>}}_{\mathrm{<span><span>d</span>d</span>}}<span><span>=</span>=</span><span><span>-</span>-</span><span><span>(</span>(</span>\frac{\mathrm{<span><span>2</span>2</span>}}{\mathrm{<span><span>e</span>e</span>}{\mathrm{<span><span>\&epsiv;</span>\&epsiv;</span>}}_{\mathrm{<span><span>0</span>0</span>}}\mathrm{<span><span>\&epsiv;</span>\&epsiv;</span>}}<span><span>)</span>)</span><span><span>/</span>/</span>\frac{\mathrm{<span><span>d</span>d</span>}{<span><span>(</span>(</span>\mathrm{<span><span>1</span>1</span>}<span><span>/</span>/</span>\mathrm{<span><span>C</span>C</span>}<span><span>)</span>)</span>}^{\mathrm{<span><span>2</span>2</span>}}}{\mathrm{<span><span>dV</span>dV</span>}}$

使用具有如下结构的MOS电容器作为用于测量的样本。该MOS电容器包括在玻璃衬底上的300nm厚的钛层、在该钛层上的100nm厚的氮化钛层、在该氮化钛层上的包括In-Ga-Zn-O-基氧化物半导体(IGZO)的2μm厚的氧化物半导体层、在该氧化物半导体层上的300nm厚的氧氮化硅层、以及在该氧氮化硅层上的300nm厚的银层。A MOS capacitor having the following structure was used as a sample for measurement. The MOS capacitor comprises a 300nm thick titanium layer on a glass substrate, a 100nm thick titanium nitride layer on the titanium layer, an In-Ga-Zn-O-based oxide layer on the titanium nitride layer A 2 μm thick oxide semiconductor layer of semiconductor (IGZO), a 300 nm thick silicon oxynitride layer on the oxide semiconductor layer, and a 300 nm thick silver layer on the silicon oxynitride layer.

注意，用溅射法使用用于沉积包含In、Ga、和Zn(In∶Ga∶Zn＝1∶1∶0.5[原子比])的金属氧化物靶形成氧化物半导体层。进一步，氧化物半导体层是在氩和氧的混合气氛(流量比为Ar∶O₂＝30(sccm)∶15(sccm))中形成的。Note that the oxide semiconductor layer is formed by a sputtering method using a metal oxide target for depositing In, Ga, and Zn (In:Ga:Zn=1:1:0.5 [atomic ratio]). Further, the oxide semiconductor layer was formed in a mixed atmosphere of argon and oxygen (flow ratio: Ar:O₂ =30 (sccm):15 (sccm)).

图10和图11分别示出C-V特性和V_g和(1/C)²之间的关系。从图11的图的弱反型区中的(1/C)²的微分值使用公式1计算出的载流子密度是6.0×10¹⁰/cm³。10 and 11 show the relationship between CV characteristics and V_g and (1/C)² , respectively. The carrier density calculated using Formula 1 from the differential value of (1/C)² in the weak inversion region of the graph of FIG. 11 is 6.0×10¹⁰ /cm³ .

以此方式，通过使用i-型或基本i-型氧化物半导体(如，具有小于1×10¹²/cm³的载流子密度，优选地，小于1.45×10¹⁰/cm³)，可获得具有良好截止态电流特性的晶体管。In this way, by using an i-type or substantially i-type oxide semiconductor (eg, having a carrier density of less than 1×10¹² /cm³ , preferably, less than 1.45×10¹⁰ /cm³ ), it is possible to obtain A transistor with good off-state current characteristics.

如上所述，可理解，当使用氧化物半导体，特别是，经提纯的本征氧化物半导体时，可获得各种有利效果。此外，当如所公开的本发明而实现具有结晶结构的本征氧化物半导体层时，实现具有良好特性的新颖的半导体器件。As described above, it can be understood that various advantageous effects can be obtained when an oxide semiconductor, particularly, a purified intrinsic oxide semiconductor is used. Furthermore, when an intrinsic oxide semiconductor layer having a crystalline structure is realized as the disclosed invention, a novel semiconductor device having good characteristics is realized.

<半导体器件的制造方法><Manufacturing method of semiconductor device>

接着，将参考图12A到12D以及图13A到13D而描述作为半导体器件的结构的示例的晶体管150的制造方法。Next, a method of manufacturing the transistor 150 as an example of the structure of the semiconductor device will be described with reference to FIGS. 12A to 12D and FIGS. 13A to 13D .

首先，在衬底100上形成绝缘层102。然后，在绝缘层102上形成氧化物半导体层106(见图12A)。First, an insulating layer 102 is formed on a substrate 100 . Then, an oxide semiconductor layer 106 is formed on the insulating layer 102 (see FIG. 12A ).

衬底100可以是具有绝缘表面的任何衬底，且可以是例如，玻璃衬底。玻璃衬底优选地是无碱玻璃衬底。例如，使用诸如铝硅酸盐玻璃、铝硼硅酸盐玻璃、钡硼硅酸盐玻璃等之类的玻璃材料作为无碱玻璃衬底的材料。可选地，可使用用诸如陶瓷衬底、石英衬底、或兰宝石衬底之类的绝缘体形成的绝缘衬底、用诸如硅之类的半导体材料形成的且其表面被覆盖有绝缘材料的半导体衬底、或用诸如金属或不锈钢之类的导体形成且其表面被覆盖有绝缘材料的导电衬底，作为衬底100。The substrate 100 may be any substrate having an insulating surface, and may be, for example, a glass substrate. The glass substrate is preferably an alkali-free glass substrate. For example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, barium borosilicate glass, or the like is used as the material of the non-alkali glass substrate. Alternatively, an insulating substrate formed with an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate, a semiconductor material formed with a semiconductor material such as silicon and whose surface is covered with an insulating material may be used. A semiconductor substrate, or a conductive substrate formed with a conductor such as metal or stainless steel and whose surface is covered with an insulating material serves as the substrate 100 .

绝缘层102用作基底且可用CVD法、溅射法等形成。优选形成绝缘层102从而包括氧化硅、氮化硅、氧氮化硅、氮氧化硅、氧化铝、氧化铪、氧化钽等。注意，绝缘层102可具有单层结构或层叠结构。对绝缘层102的厚度没有具体限制；例如，绝缘层102可具有10nm至500nm的厚度。此处，绝缘层102并不是必要组件；因此，其中没有提供绝缘层102的结构也是可能的。The insulating layer 102 serves as a base and can be formed by a CVD method, a sputtering method, or the like. The insulating layer 102 is preferably formed so as to include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the insulating layer 102 may have a single-layer structure or a laminated structure. There is no specific limitation on the thickness of the insulating layer 102; for example, the insulating layer 102 may have a thickness of 10 nm to 500 nm. Here, the insulating layer 102 is not an essential component; therefore, a structure in which the insulating layer 102 is not provided is also possible.

如果在绝缘层102中包含氢、水等，氢可进入氧化物半导体层或从氧化物半导体层中抽取氧，藉此晶体管的特性可被劣化。因此，理想的是形成绝缘层102从而包括尽可能少的氢或水。If hydrogen, water, or the like is contained in the insulating layer 102, hydrogen may enter the oxide semiconductor layer or extract oxygen from the oxide semiconductor layer, whereby the characteristics of the transistor may be degraded. Therefore, it is desirable to form the insulating layer 102 so as to include as little hydrogen or water as possible.

在使用溅射法等的情况下，例如，理想的是在移除了处理腔室中剩余的水分的状态中形成绝缘层102。为了去除残留在处理腔室中的水分，优选使用诸如低温泵、离子泵、或钛升华泵的截留真空泵。可使用设置有冷阱的涡轮泵。从用低温泵等抽空的处理腔室中，氢、水等被充分移除；因此，绝缘层102中的杂质可被减少。In the case of using a sputtering method or the like, for example, it is desirable to form the insulating layer 102 in a state in which moisture remaining in the processing chamber is removed. In order to remove the moisture remaining in the processing chamber, it is preferable to use a trap vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. A turbo pump provided with a cold trap can be used. From the processing chamber evacuated with a cryopump or the like, hydrogen, water, and the like are sufficiently removed; therefore, impurities in the insulating layer 102 can be reduced.

在形成绝缘层102时，理想的是使用其中诸如氢或水之类的杂质被减少至约百万分之几(优选地为十亿分之几)的浓度的高纯度气体。In forming the insulating layer 102, it is desirable to use a high-purity gas in which impurities such as hydrogen or water are reduced to a concentration of about several parts per million (preferably several parts per billion).

可使用如下材料中的任意形成氧化物半导体层106：四组分金属氧化物，如In-Sn-Ga-Zn-O基材料；三组分金属氧化物，如In-Ga-Zn-O基材料、In-Sn-Zn-O基材料、In-Al-Zn-O基材料、Sn-Ga-Zn-O基材料、Al-Ga-Zn-O基材料、和Sn-Al-Zn-O基材料；二组分金属氧化物，如In-Zn-O基材料、Sn-Zn-O基材料、Al-Zn-O基材料、Zn-Mg-O基材料、Sn-Mg-O基材料、和In-Mg-O基材料；单组分金属氧化物，如In-O基材料、Sn-O基材料、和Zn-O基材料；等等。The oxide semiconductor layer 106 can be formed using any of the following materials: a four-component metal oxide such as an In-Sn-Ga-Zn-O-based material; a three-component metal oxide such as an In-Ga-Zn-O-based material; materials, In-Sn-Zn-O-based materials, In-Al-Zn-O-based materials, Sn-Ga-Zn-O-based materials, Al-Ga-Zn-O-based materials, and Sn-Al-Zn-O Base materials; two-component metal oxides, such as In-Zn-O base materials, Sn-Zn-O base materials, Al-Zn-O base materials, Zn-Mg-O base materials, Sn-Mg-O base materials , and In-Mg-O-based materials; single-component metal oxides, such as In-O-based materials, Sn-O-based materials, and Zn-O-based materials; and so on.

特定地，当没有电场且因此截止态电流可被充分减少时，In-Ga-Zn-O-基氧化物半导体材料具有足够高的电阻。此外，In-Ga-Zn-O-基氧化物半导体材料还具有高场效应迁移率，适合于被用在半导体器件中的半导体材料。Specifically, the In-Ga-Zn-O-based oxide semiconductor material has sufficiently high resistance when there is no electric field and thus off-state current can be sufficiently reduced. In addition, In-Ga-Zn-O-based oxide semiconductor materials also have high field-effect mobility and are suitable for semiconductor materials used in semiconductor devices.

给出用InGaO₃(ZnO)_m(m＞0)表示的氧化物半导体材料作为In-Ga-Zn-O-基氧化物半导体材料的典型示例。使用M代替Ga，有用InMO₃(ZnO)_m(m＞0)表示的氧化物半导体材料。此处，M表示从镓(Ga)、铝(Al)、铁(Fe)、镍(Ni)、锰(Mn)钴(Co)等中选择的一种或多种金属元素。例如，M可以是Ga、Ga和Al、Ga和Fe、Ga和Ni、Ga和Mn、Ga和Co等等。注意，上述组合物是从氧化物半导体材料可具有的晶体结构中导出的且仅仅是示例。An oxide semiconductor material represented by InGaO₃ (ZnO)_m (m>0) is given as a typical example of the In-Ga-Zn-O-based oxide semiconductor material. Using M instead of Ga, there is an oxide semiconductor material represented by InMO₃ (ZnO)_m (m>0). Here, M represents one or more metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), and the like. For example, M may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, and the like. Note that the above composition is derived from the crystal structure that an oxide semiconductor material can have and is only an example.

在本实施例中，通过将靶用于沉积In-Ga-Zn-O基氧化物半导体的溅射法来形成非晶氧化物半导体层作为该氧化物半导体层106。In this embodiment, an amorphous oxide semiconductor layer is formed as the oxide semiconductor layer 106 by a sputtering method using a target for depositing an In-Ga-Zn-O-based oxide semiconductor.

例如，可使用包含氧化锌作为其主要组分的金属氧化物靶来作为用于通过溅射法形成氧化物半导体层106的靶。进一步，用于沉积包括In、Ga、和Zn的氧化物半导体的靶具有组分比例为In∶Ga∶Zn＝1∶x∶y(x大于或等于0且小于或等于2，且y大于或等于1且小于或等于5)。例如，可使用具有组分比例In∶Ga∶Zn＝1∶1∶1[原子比](x＝1，y＝1)或组分比例In₂O₃∶Ga₂O₃∶ZnO＝1∶1∶2[摩尔比])的靶。进一步，可使用具有组分比例In∶Ga∶Zn＝1∶1∶0.5[原子比]或组分比例In∶Ga∶Zn＝1∶1∶2[原子比]或In∶Ga∶Zn＝1∶0∶1[原子比](x＝0，y＝1)的靶作为用于沉积氧化物半导体的靶。在这个实施例中，稍后进行热处理从而有意地结晶化氧化物半导体层；因此，优选地使用一种用于沉积氧化物半导体的靶，使用该靶能使该氧化物半导体层可易于被结晶化。For example, a metal oxide target containing zinc oxide as its main component can be used as a target for forming the oxide semiconductor layer 106 by a sputtering method. Further, the target for depositing an oxide semiconductor including In, Ga, and Zn has a composition ratio of In:Ga:Zn=1:x:y (x is greater than or equal to 0 and less than or equal to 2, and y is greater than or equal to equal to 1 and less than or equal to 5). For example, a compound having a composition ratio In:Ga:Zn=1:1:1 [atomic ratio] (x=1, y=1) or a composition ratio In₂ O₃ :Ga₂ O₃ :ZnO=1: 1:2 [molar ratio]) targets. Further, a composition ratio In:Ga:Zn=1:1:0.5 [atomic ratio] or a composition ratio In:Ga:Zn=1:1:2 [atomic ratio] or In:Ga:Zn=1 can be used A target of :0:1 [atomic ratio] (x=0, y=1) was used as a target for depositing an oxide semiconductor. In this embodiment, the heat treatment is performed later to intentionally crystallize the oxide semiconductor layer; therefore, it is preferable to use a target for depositing the oxide semiconductor with which the oxide semiconductor layer can be easily crystallized change.

在用于沉积氧化物半导体的靶中的氧化物半导体的相对密度为80％或更大，优选地为95％或更大，更优选地为99.9％或更大。使用用于沉积具有较高相对密度的氧化物半导体的靶，使得可能形成具有致密结构的氧化物半导体层。The relative density of the oxide semiconductor in the target for depositing the oxide semiconductor is 80% or more, preferably 95% or more, more preferably 99.9% or more. Using a target for depositing an oxide semiconductor having a higher relative density makes it possible to form an oxide semiconductor layer having a dense structure.

其中形成氧化物半导体层106的气氛优选是稀有气体(通常是氩)气氛、氧气氛、或者稀有气体(通常是氩)和氧的混合气氛。具体地，优选使用例如将诸如氢、水、羟基、或氢化物之类的杂质去除到约百万分之几(优选十亿分之几)的浓度的高纯度气体气氛。The atmosphere in which the oxide semiconductor layer 106 is formed is preferably a rare gas (usually argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (usually argon) and oxygen. Specifically, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed, for example, to a concentration of about several parts per million (preferably several parts per billion).

在形成氧化物半导体层106时，例如，将衬底保持在维持在减小压力且衬底被加热至100℃至600℃的温度、优选为200℃至400℃下的处理腔室中。然后，将去除氢和水的溅射气体引入去除了剩余水分的处理腔室中，并且使用金属氧化物作为靶来形成氧化物半导体层106。通过在加热衬底同时形成氧化物半导体层106，可减少氧化物半导体层106中的杂质。此外，减少因溅射造成的损坏。为了移除处理腔室中剩余的水分，优选使用截留真空泵。例如，可使用低温泵、离子泵、钛升华泵等。可使用设置有冷阱的涡轮泵。从用低温泵等抽空的处理腔室中，氢、水等被充分移除；因此，氧化物半导体层106中的杂质可被减少。In forming the oxide semiconductor layer 106, for example, the substrate is held in a processing chamber maintained at reduced pressure and the substrate is heated to a temperature of 100°C to 600°C, preferably 200°C to 400°C. Then, a sputtering gas from which hydrogen and water are removed is introduced into the processing chamber from which remaining moisture is removed, and the oxide semiconductor layer 106 is formed using the metal oxide as a target. By forming the oxide semiconductor layer 106 while heating the substrate, impurities in the oxide semiconductor layer 106 can be reduced. Additionally, damage due to sputtering is reduced. In order to remove remaining moisture in the processing chamber, it is preferred to use an intercepted vacuum pump. For example, cryopumps, ion pumps, titanium sublimation pumps, and the like can be used. A turbo pump provided with a cold trap can be used. From the processing chamber evacuated with a cryopump or the like, hydrogen, water, and the like are sufficiently removed; therefore, impurities in the oxide semiconductor layer 106 can be reduced.

例如，形成氧化物半导体层106的条件可被设置如下：衬底和靶之间的距离为170mm，压力为0.4Pa、直流(DC)电源为0.5kW，且气氛为氧(100％氧)气氛，氩(100％氩)气氛、或氧和氩的混合气氛。注意，优选使用脉冲直流(DC)电源，因为可减少灰尘(在成膜时形成的粉末或片状物质)并且膜厚可以是均匀的。氧化物半导体层106的厚度被设置为2nm至200nm、优选为5nm至30nm。注意，氧化物半导体层106的合适厚度取决于所使用的氧化物半导体材料、所意在的用途等而变化；因此，可根据材料、所意在的用途等而适当地确定厚度。For example, the conditions for forming the oxide semiconductor layer 106 can be set as follows: the distance between the substrate and the target is 170mm, the pressure is 0.4Pa, the direct current (DC) power supply is 0.5kW, and the atmosphere is an oxygen (100% oxygen) atmosphere. , argon (100% argon) atmosphere, or a mixed atmosphere of oxygen and argon. Note that it is preferable to use a pulsed direct current (DC) power supply because dust (powder or flake-like substances formed at the time of film formation) can be reduced and the film thickness can be uniform. The thickness of the oxide semiconductor layer 106 is set to 2 nm to 200 nm, preferably 5 nm to 30 nm. Note that an appropriate thickness of the oxide semiconductor layer 106 varies depending on the oxide semiconductor material used, intended use, and the like; therefore, the thickness can be appropriately determined depending on the material, intended use, and the like.

注意，在通过溅射法形成氧化物半导体层106之前，优选地执行其中用所引入的氩气产生等离子体的反溅射，从而移除附着至绝缘层102的表面的材料。在此，不同于离子与溅射靶碰撞的正常溅射，反溅射是离子与要处理的表面碰撞以使该表面改性的方法。用于使离子与要处理的表面碰撞的方法的示例是在氩气氛中将高频电压施加到该表面侧从而在衬底附近生成等离子体的方法。注意，可使用氮、氦、氧等气氛来代替氩气氛。Note that before forming the oxide semiconductor layer 106 by the sputtering method, reverse sputtering in which plasma is generated with introduced argon gas is preferably performed, thereby removing the material attached to the surface of the insulating layer 102 . Here, unlike normal sputtering in which ions collide with a sputtering target, reverse sputtering is a method in which ions collide with a surface to be processed to modify the surface. An example of a method for colliding ions with a surface to be processed is a method of applying a high-frequency voltage to the surface side in an argon atmosphere to generate plasma near the substrate. Note that an atmosphere of nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere.

接着，通过诸如使用掩模的蚀刻之类的方法处理氧化物半导体层106；因此，形成具有岛状形状的氧化物半导体层106a(见图12B)。Next, the oxide semiconductor layer 106 is processed by a method such as etching using a mask; thus, the oxide semiconductor layer 106a having an island shape is formed (see FIG. 12B ).

可采用干法蚀刻或湿法蚀刻作为用于蚀刻氧化物半导体层的方法。毋庸赘言，干法蚀刻和湿法蚀刻可组合使用。蚀刻条件(例如，蚀刻气体或蚀刻剂、蚀刻时间、以及温度)根据材料适当地设定，从而可将氧化物半导体层蚀刻成期望形状。Dry etching or wet etching can be employed as a method for etching the oxide semiconductor layer. Needless to say, dry etching and wet etching may be used in combination. Etching conditions (for example, etching gas or etchant, etching time, and temperature) are appropriately set according to the material, so that the oxide semiconductor layer can be etched into a desired shape.

作为干法蚀刻，可使用平行板反应离子蚀刻(RIE)法、感应耦合等离子体(ICP)蚀刻法等。还是在这个情况下，需要适当地设置蚀刻条件(例如，施加到线圈状(coiled)电极的电功率量、施加到衬底侧上的电极的电功率量、以及衬底侧上的电极温度)。As dry etching, a parallel plate reactive ion etching (RIE) method, an inductively coupled plasma (ICP) etching method, or the like can be used. Also in this case, etching conditions (for example, the amount of electric power applied to the coiled electrode, the amount of electric power applied to the electrode on the substrate side, and the temperature of the electrode on the substrate side) need to be set appropriately.

可被用于干法蚀刻的蚀刻气体的示例是包含氯的气体(诸如氯气(Cl₂)、三氯化硼(BCl₃)、四氯化硅(SiCl₄)、或四氯化碳(CCl₄)之类的氯基气体)。另外，可使用含氟气体(诸如四氟化碳(CF₄)、六氟化硫(SF₆)、三氟化氮(NF₃)、或三氟甲烷(CHF₃)之类的氟基气体)；溴化氢(HBr)；氧气(O₂)、添加了诸如氦(He)或氩(Ar)之类的稀有气体的这些气体中的任一种等。Examples of etching gases that can be used for dry etching are gases containing chlorine such as chlorine (Cl₂ ), boron trichloride (BCl₃ ), silicon tetrachloride (SiCl₄ ), or carbon tetrachloride (CCl₄ ) such as chlorine-based gases). In addition, a fluorine-containing gas (fluorine-based gas such as carbon tetrafluoride (CF₄ ), sulfur hexafluoride (SF₆ ), nitrogen trifluoride (NF₃ ), or trifluoromethane (CHF₃ ) may be used ); hydrogen bromide (HBr); oxygen (O₂ ), any of these gases to which a rare gas such as helium (He) or argon (Ar) is added, and the like.

可被用于湿法蚀刻的蚀刻剂的示例包括磷酸、醋酸、以及硝酸的混合溶液、氨过氧化氢混合物(31wt％的双氧水溶液∶28wt％的氨溶液∶水＝5∶2∶2)等。还可使用诸如ITO-07N(由KANTO化学公司(KANTO CHEMICAL CO.，INC.)生产)之类的蚀刻剂。Examples of etchant that can be used for wet etching include a mixed solution of phosphoric acid, acetic acid, and nitric acid, ammonia peroxide mixture (31 wt % hydrogen peroxide solution: 28 wt % ammonia solution: water = 5: 2: 2), etc. . An etchant such as ITO-07N (manufactured by KANTO CHEMICAL CO., INC.) can also be used.

在那之后，优选地在氧化物半导体层106a上进行热处理(第一热处理)。通过该第一热处理可移除氧化物半导体层106a中包含的水(包括羟基)、氢等。例如，第一热处理的温度可被设置为高于或等于300℃且低于550℃，优选高于或等于400℃且低于550℃。注意，该第一热处理可以再一次执行作为要执行的第二热处理(用于形成结晶区的热处理)。在这个情况下，热处理的温度优选地被设置为高于或等于550℃且低于或等于850℃。After that, heat treatment (first heat treatment) is preferably performed on the oxide semiconductor layer 106a. Water (including hydroxyl groups), hydrogen, and the like contained in the oxide semiconductor layer 106a can be removed by this first heat treatment. For example, the temperature of the first heat treatment may be set to be higher than or equal to 300°C and lower than 550°C, preferably higher than or equal to 400°C and lower than 550°C. Note that this first heat treatment may be performed again as the second heat treatment (heat treatment for forming a crystalline region) to be performed. In this case, the temperature of the heat treatment is preferably set to be higher than or equal to 550°C and lower than or equal to 850°C.

例如，在衬底100被引入包括电阻加热器等的电炉之后，可在氮气氛中在450℃执行热处理达一小时。氧化物半导体层106a在热处理期间不暴露于空气，从而可防止水或氢进入。For example, heat treatment may be performed at 450° C. for one hour in a nitrogen atmosphere after the substrate 100 is introduced into an electric furnace including a resistance heater or the like. The oxide semiconductor layer 106a is not exposed to air during heat treatment, so that water or hydrogen can be prevented from entering.

热处理装置不限于电炉，并且可以是用于通过热辐射或来自诸如经加热气体之类的介质的热传导对将要被处理的物体加热的装置。例如，可使用诸如气体快速热退火(GRTA)装置或灯快速热退火(LRTA)装置之类的快速热退火(RTA)装置。LRTA装置是用于通过从诸如卤素灯、卤化金属灯、氙弧灯、碳弧灯、高压钠灯、或高压汞灯之类的灯发射的光(电磁波)辐射来对要处理的物体加热的装置。GRTA装置是用于使用高温气体来进行热处理的装置。可使用不与将要通过热处理被处理的物体反应的惰性气体(例如，氮或诸如氩之类的稀有气体)作为该气体。The heat treatment device is not limited to an electric furnace, and may be a device for heating an object to be processed by heat radiation or heat conduction from a medium such as heated gas. For example, a rapid thermal anneal (RTA) apparatus such as a gas rapid thermal anneal (GRTA) apparatus or a lamp rapid thermal anneal (LRTA) apparatus may be used. The LRTA apparatus is an apparatus for heating an object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp . The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. An inert gas (for example, nitrogen or a rare gas such as argon) which does not react with an object to be processed by heat treatment can be used as the gas.

例如，作为第一热处理，GRTA处理可被如下执行。将衬底放在已加热到650℃至700℃高温的惰性气体气氛中，加热几分钟，并从惰性气体气氛中取出。GRTA处理能实现较短时间内的高温热处理。另外，即使当温度超过衬底的上限温度是也可采用GRTA处理，因为该热处理可在短时间内进行。在使用玻璃衬底的情况下，在温度高于上限温度(应变点)时衬底的收缩成为问题，但是在短时间内执行热处理的情况下就不是问题。注意，在该处理期间，惰性气体可被切换成包括氧的气体。这是由于通过在包括氧的气氛中执行第一热处理可减少由于缺氧引起的缺陷。For example, as the first heat treatment, GRTA treatment may be performed as follows. The substrate is placed in an inert gas atmosphere heated to a high temperature of 650°C to 700°C, heated for several minutes, and taken out of the inert gas atmosphere. GRTA treatment can achieve high temperature heat treatment in a relatively short period of time. In addition, GRTA treatment can be employed even when the temperature exceeds the upper limit temperature of the substrate, because the heat treatment can be performed in a short time. In the case of using a glass substrate, shrinkage of the substrate becomes a problem at a temperature higher than the upper limit temperature (strain point), but it is not a problem in the case of performing heat treatment in a short time. Note that the inert gas may be switched to a gas including oxygen during this process. This is because defects due to oxygen deficiency can be reduced by performing the first heat treatment in an atmosphere including oxygen.

注意，作为惰性气体气氛，优选使用包含氮或稀有气体(例如，氦、氖、或氩)作为其主要成分并且不包含水、氢等的气氛。例如，向热处理装置中引入的氮或诸如氦、氖或氩的稀有气体的纯度设为6N(99.9999％)或更高，优选为7N(99.99999％)或更高(即，杂质浓度为1ppm或更低，优选为0.1ppm或更低)。Note that, as the inert gas atmosphere, an atmosphere containing nitrogen or a rare gas (for example, helium, neon, or argon) as its main component and not containing water, hydrogen, or the like is preferably used. For example, the purity of nitrogen or a rare gas such as helium, neon or argon introduced into the heat treatment device is set to 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

在任何情况下，使用作为通过第一热处理移除杂质而获得的i-型或基本i-型氧化物半导体层的氧化物半导体层106a可获得具有极为良好的特性的晶体管150。In any case, the transistor 150 having extremely good characteristics can be obtained using the oxide semiconductor layer 106 a which is an i-type or substantially i-type oxide semiconductor layer obtained by removing impurities through the first heat treatment.

注意，可在还没有被处理为具有岛状形状的氧化物半导体层106a的氧化物半导体层106上执行第一热处理。在此情况下，在第一热处理之后，从加热装置中取出衬底100，并且执行光刻步骤。Note that the first heat treatment may be performed on the oxide semiconductor layer 106 that has not been processed into the oxide semiconductor layer 106 a having an island shape. In this case, after the first heat treatment, the substrate 100 is taken out from the heating apparatus, and a photolithography step is performed.

第一热处理因为其具有去除氢或水的效果，也可被称为脱水处理、脱氢处理等。可在形成氧化物半导体层之后、在源电极层和漏电极层被层叠在该氧化物半导体层106a上之后、或者在源电极层和漏电极层上形成栅绝缘层之后进行这种脱水处理或脱氢处理。这种脱水处理或脱氢处理可进行一次或多次。The first heat treatment may also be called dehydration treatment, dehydrogenation treatment, or the like because it has an effect of removing hydrogen or water. Such dehydration treatment may be performed after the oxide semiconductor layer is formed, after the source electrode layer and the drain electrode layer are laminated on the oxide semiconductor layer 106a, or after the gate insulating layer is formed on the source electrode layer and the drain electrode layer or Dehydrogenation treatment. Such dehydration treatment or dehydrogenation treatment may be performed one or more times.

接着，形成导电层108从而与该氧化物半导体层106a相接触(见图12C)。Next, a conductive layer 108 is formed so as to be in contact with the oxide semiconductor layer 106a (see FIG. 12C ).

导电层108可通过诸如溅射法之类的PVD法、或者诸如等离子体CVD法之类的CVD法形成。可使用从铝、铬、铜、钽、钛、钼、以及钨中选择的元素、包含这些元素中的任意作为组分的合金等形成导电层108。可使用包含锰、镁、锆和铍中的一种或多种的材料。可使用包括铝与从钛、钽、钨、钼、铬、钕、和钪中选择的一种或多种元素的材料。The conductive layer 108 can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer 108 can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing any of these elements as a component, or the like. A material containing one or more of manganese, magnesium, zirconium, and beryllium may be used. A material including aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

也可使用导电金属氧化物来形成该导电层108。作为导电金属氧化物，可使用氧化铟(In₂O₃)、氧化锡(SnO₂)、氧化锌(ZnO)、氧化铟-氧化锡合金(In₂O₃-SnO₂，在一些情况下缩写为ITO)、氧化铟-氧化锌合金(In₂O₃-ZnO)、或者包含硅或氧化硅的这些金属氧化物材料中的任一种。The conductive layer 108 may also be formed using a conductive metal oxide. As conductive metal oxides, indium oxide (In₂ O₃ ), tin oxide (SnO₂ ), zinc oxide (ZnO), indium oxide-tin oxide alloy (In₂ O₃ -SnO₂ , abbreviated in some cases is ITO), indium oxide-zinc oxide alloy (In₂ O₃ -ZnO), or any of these metal oxide materials containing silicon or silicon oxide.

导电层108可具有单层结构、或者包含两层或更多层的层叠结构。例如，导电层108可具有其中在钛膜上堆叠铝钛且在该铝钛上堆叠钛钛的三层结构，或者其中在钼钛上堆叠铝钛且在该铝钛上堆叠钼钛的三层结构。可选地，导电层108可具有其中铝钛和钨钛堆叠的两层结构、其中铜钛和钨钛堆叠的两层结构、或者其中铝钛和钼钛堆叠的两层结构。毋庸赘言，导电层108可具有单层结构、或者四层或更多层的层叠结构。在单层结构的情况下，钛膜的单层结构是优选的。使用钛膜的单层结构，可实现用于形成良好楔形的后续蚀刻。此处，采用了钛膜、铝膜、和钛膜的三层结构。The conductive layer 108 may have a single-layer structure, or a laminated structure including two or more layers. For example, the conductive layer 108 may have a three-layer structure in which aluminum titanium is stacked on a titanium film and titanium titanium is stacked on the aluminum titanium, or a three-layer structure in which aluminum titanium is stacked on molybdenum titanium and molybdenum titanium is stacked on the aluminum titanium structure. Alternatively, the conductive layer 108 may have a two-layer structure in which aluminum titanium and tungsten titanium are stacked, a two layer structure in which copper titanium and tungsten titanium are stacked, or a two layer structure in which aluminum titanium and molybdenum titanium are stacked. Needless to say, the conductive layer 108 may have a single-layer structure, or a laminated structure of four or more layers. In the case of a single-layer structure, a single-layer structure of a titanium film is preferable. Using a single-layer structure of the titanium film, subsequent etching for forming a fine wedge can be achieved. Here, a three-layer structure of a titanium film, an aluminum film, and a titanium film is employed.

注意，可在与氧化物半导体层106a相接触的导电层108的一部分中使用具有较低的抽氧能力的材料(具有较低氧亲和力的材料)。例如，可给出氮化钛、氮化钨、铂等作为这样的材料。以与上述类似的方式，导电层108可具有单层结构或层叠结构。在导电层108具有层叠结构的情况下，例如，可采用氮化钛膜和钛膜的两层结构、氮化钛膜和钨膜的两层结构、氮化钛膜和铜-钼合金膜的两层结构、氮化钽膜和钨膜的两层结构、氮化钽膜和铜膜的两层结构、氮化钛膜、钨膜和钛膜的三层结构，等。Note that a material having a lower oxygen extraction capability (a material having a lower oxygen affinity) may be used in a part of the conductive layer 108 in contact with the oxide semiconductor layer 106a. For example, titanium nitride, tungsten nitride, platinum, and the like can be given as such a material. In a similar manner to the above, the conductive layer 108 may have a single-layer structure or a laminated structure. In the case where the conductive layer 108 has a laminated structure, for example, a two-layer structure of a titanium nitride film and a titanium film, a two-layer structure of a titanium nitride film and a tungsten film, a titanium nitride film and a copper-molybdenum alloy film can be used. Two-layer structure, two-layer structure of tantalum nitride film and tungsten film, two-layer structure of tantalum nitride film and copper film, three-layer structure of titanium nitride film, tungsten film and titanium film, etc.

在为导电层108使用如上所述的具有较低的抽氧能力的材料的情况下，可防止由于氧的抽取而从氧化物半导体层变化至n-型的变化；相应地，可防止由于变化至n-型的不均匀变化导致的对晶体管特性的不利影响。In the case of using a material having a low oxygen extraction capability as described above for the conductive layer 108, the change from the oxide semiconductor layer to the n-type due to the extraction of oxygen can be prevented; Adverse effects on transistor characteristics due to non-uniform change to n-type.

在与氧化物半导体层106a相接触的导电层108的一部分中使用具有高阻挡性的材料(诸如如上所述的氮化钛膜或氮化钽膜)的情况下，可防止杂质进入氧化物半导体层106a并可减少对于晶体管特性的不利影响。In the case where a material having high barrier properties such as the titanium nitride film or tantalum nitride film as described above is used in a part of the conductive layer 108 in contact with the oxide semiconductor layer 106a, impurities can be prevented from entering the oxide semiconductor layer 106a. Layer 106a can also reduce adverse effects on transistor characteristics.

接着，选择性蚀刻导电层108；因此，形成源或漏电极层108a和源或漏电极层108b(见图12D)。注意，可在导电层108上形成绝缘层，且可蚀刻该绝缘层；因此，可在源或漏电极层上形成与该源或漏电极层基本一样形状的绝缘层。在这个情况下，可减少源或漏电极层与栅电极层之间的电容(所谓的栅极电容)。注意，表达“基本一样”或“基本是一样”并不必然意味着在严格意义上严格地一样且可意味着被认为是一样的。例如，由单个蚀刻工艺造成的差异是可接受的。进一步，厚度并不需要是一样的。Next, the conductive layer 108 is selectively etched; thus, the source or drain electrode layer 108a and the source or drain electrode layer 108b are formed (see FIG. 12D ). Note that an insulating layer may be formed on the conductive layer 108 and may be etched; therefore, an insulating layer having substantially the same shape as the source or drain electrode layer may be formed on the source or drain electrode layer. In this case, the capacitance between the source or drain electrode layer and the gate electrode layer (so-called gate capacitance) can be reduced. Note that the expression "substantially the same" or "substantially the same" does not necessarily mean strictly the same in a strict sense and may mean considered to be the same. For example, variance caused by a single etch process is acceptable. Further, the thickness need not be the same.

对于在形成用于蚀刻的掩模时的曝光，优选使用紫外光、KrF激光、或ArF激光。特别对于在沟道长度(L)小于25nm的情况下的曝光，优选用其波长为极短的几纳米至几十纳米的极紫外光来进行用于形成掩模的曝光。在使用极紫外光的曝光时，分辨率高且聚焦深度大。因此，稍后形成的晶体管的沟道长度(L)也可被制成10nm到1000nm。通过这样的方法进行沟道长度的减少，可改进操作速度。此外，包括上述氧化物半导体的晶体管的截止态电流较小；因此，可抑制由于微型化引起的功耗的增加。For exposure when forming a mask for etching, ultraviolet light, KrF laser, or ArF laser is preferably used. Especially for exposure in the case where the channel length (L) is less than 25 nm, it is preferable to perform exposure for mask formation with extreme ultraviolet light whose wavelength is extremely short from several nanometers to several tens of nanometers. High resolution and large depth of focus for exposures using extreme ultraviolet light. Therefore, the channel length (L) of a transistor formed later can also be made 10 nm to 1000 nm. By performing channel length reduction in this way, the operating speed can be improved. In addition, the off-state current of a transistor including the above-mentioned oxide semiconductor is small; therefore, an increase in power consumption due to miniaturization can be suppressed.

适当地调节导电层108和氧化物半导体层106a的材料和蚀刻条件，从而在蚀刻导电层108时不去除氧化物半导体层106a。注意，在一些情况下，氧化物半导体层106a根据材料和蚀刻条件在蚀刻步骤中部分地蚀刻，并且由此具有凹槽部分(凹陷部分)。The materials and etching conditions of the conductive layer 108 and the oxide semiconductor layer 106a are appropriately adjusted so that the oxide semiconductor layer 106a is not removed when the conductive layer 108 is etched. Note that, in some cases, the oxide semiconductor layer 106a is partially etched in the etching step depending on the material and etching conditions, and thus has a groove portion (recessed portion).

为了减少所使用的掩模的数量和减少步骤的数量，蚀刻步骤可使用通过使用多色调掩模而形成的抗蚀剂掩模来执行，该多色调掩模是透射光以使其具有多个强度的曝光掩模。通过使用多色调掩模而形成的抗蚀剂掩模具有多个厚度(具有阶梯式的形状)，并且还可通过灰化来改变形状；因此，抗蚀剂掩模可在多个蚀刻步骤中使用。即，可通过使用一个多色调掩模来形成与至少两种不同的图案相对应的抗蚀剂掩模。由此，可减少曝光掩模的数量，并且还可减少相应的光刻步骤的数量，由此可简化工艺。In order to reduce the number of masks used and to reduce the number of steps, the etching step can be performed using a resist mask formed by using a multi-tone mask that transmits light so that it has multiple Intensity exposure mask. A resist mask formed by using a multi-tone mask has multiple thicknesses (having a stepped shape), and the shape can also be changed by ashing; therefore, the resist mask can be processed in multiple etching steps use. That is, resist masks corresponding to at least two different patterns can be formed by using one multi-tone mask. Thereby, the number of exposure masks can be reduced, and the number of corresponding photolithography steps can also be reduced, whereby the process can be simplified.

接着，在氧化物半导体层106a上进行热处理(第二热处理)。通过这个第二热处理，在包括氧化物半导体层106a的表面的区域中形成结晶区110(见图13A)。注意，结晶区110的范围取决于氧化物半导体层106a的材料、热处理的条件等而变化。例如，结晶区110可被形成至氧化物半导体层106a的较低界面处。Next, heat treatment (second heat treatment) is performed on the oxide semiconductor layer 106a. Through this second heat treatment, a crystallization region 110 is formed in a region including the surface of the oxide semiconductor layer 106a (see FIG. 13A ). Note that the range of the crystallization region 110 varies depending on the material of the oxide semiconductor layer 106a, the conditions of heat treatment, and the like. For example, the crystallization region 110 may be formed up to the lower interface of the oxide semiconductor layer 106a.

对于第二热处理，可采用与第一热处理类似的热处理。换言之，可采用使用电炉的热处理、使用从诸如经加热的气体之类的介质的热传导的热处理、使用热辐射的热处理等。For the second heat treatment, heat treatment similar to that of the first heat treatment may be employed. In other words, heat treatment using an electric furnace, heat treatment using heat conduction from a medium such as heated gas, heat treatment using heat radiation, or the like may be employed.

注意，优选的是在处理气氛中不包含氧。这是因为，当处理气氛中不包含氧时，源或漏电极层108a等的氧化可被防止。例如，可采用其中氢、水等被充分减少的惰性气体(氮、稀有气体等)作为特定的气氛。温度被设置为高于或等于550℃且低于或等于850℃，优选高于或等于550℃且低于或等于750℃。这是由于，通过在相对高的温度执行第二热处理可生长良好的晶体。Note that it is preferable not to contain oxygen in the treatment atmosphere. This is because, when oxygen is not contained in the process atmosphere, oxidation of the source or drain electrode layer 108a or the like can be prevented. For example, an inert gas (nitrogen, rare gas, etc.) in which hydrogen, water, etc. are sufficiently reduced can be employed as the specific atmosphere. The temperature is set to be higher than or equal to 550°C and lower than or equal to 850°C, preferably higher than or equal to 550°C and lower than or equal to 750°C. This is because good crystals can be grown by performing the second heat treatment at a relatively high temperature.

注意，尽管本发明的必要部分不要求对于热处理温度的特定上限，在其中衬底100具有较低耐热性的情况下，热处理温度的上限需要低于衬底100的可允许的温度极限。Note that although an essential part of the present invention does not require a specific upper limit for the heat treatment temperature, in the case where the substrate 100 has low heat resistance, the upper limit of the heat treatment temperature needs to be lower than the allowable temperature limit of the substrate 100.

在采用GRTA处理的情况下，热处理时间段优选为1分钟到100分钟长。例如，优选地在650℃执行GRTA处理达约3分钟至6分钟。通过采用上述GRTA处理，可在短时间内执行热处理；因此，可减少热对于衬底100的不利影响。即，相比其中执行热处理达较长时间的情况，在这个情况下可增加热处理温度的上限。此外，可易于在包括氧化物半导体层106a的表面的区域中形成结晶区110。In the case of employing GRTA treatment, the heat treatment period is preferably 1 minute to 100 minutes long. For example, GRTA treatment is preferably performed at 650°C for about 3 minutes to 6 minutes. By employing the above-described GRTA treatment, heat treatment can be performed in a short time; therefore, adverse effects of heat on the substrate 100 can be reduced. That is, the upper limit of the heat treatment temperature can be increased in this case compared to the case where the heat treatment is performed for a longer time. Furthermore, the crystalline region 110 can be easily formed in a region including the surface of the oxide semiconductor layer 106a.

在第二热处理中，优选的是在处理气氛中不包含氢(包括水)等。例如，被引入热处理装置的惰性气体的纯度被设置为6N(99.9999％，即，杂质浓度为1ppm或更低)或更大，优选地，7N(99.99999％，即，杂质浓度为0.1ppm或更低)或更大。替代惰性气体，可使用其中氢(包括水)等被充分减少的氧气、极干燥空气(具有-40℃或更低，优选为-60℃或更低的露点)等。In the second heat treatment, it is preferable not to contain hydrogen (including water) or the like in the treatment atmosphere. For example, the purity of the inert gas introduced into the heat treatment device is set to 6N (99.9999%, that is, the impurity concentration is 1 ppm or less) or more, preferably 7N (99.99999%, that is, the impurity concentration is 0.1 ppm or more low) or greater. Instead of the inert gas, oxygen in which hydrogen (including water) and the like is sufficiently reduced, extremely dry air (having a dew point of -40°C or lower, preferably -60°C or lower), or the like can be used.

注意，只要在形成氧化物半导体层106之后执行，可在任何时间执行该第二热处理。因此，例如，可能执行既用作第一热处理又用作第二处理的热处理。在这个情况下，执行第一热处理或第二热处理。此外，第二热处理可被执行一次或多次。Note that this second heat treatment may be performed at any time as long as it is performed after forming the oxide semiconductor layer 106 . Therefore, for example, it is possible to perform heat treatment that serves as both the first heat treatment and the second heat treatment. In this case, the first heat treatment or the second heat treatment is performed. In addition, the second heat treatment may be performed one or more times.

在以此方式形成结晶区110中，氧化物半导体中的晶体被对齐，从而其c-轴处于与氧化物半导体层的表面基本垂直的方向。此处，“基本垂直”意味着与垂直方向在±10°范围内。In forming the crystallized region 110 in this manner, crystals in the oxide semiconductor are aligned such that their c-axis is in a direction substantially perpendicular to the surface of the oxide semiconductor layer. Here, "substantially perpendicular" means within ±10° from the vertical direction.

例如，在其中使用In-Ga-Zn-O-基氧化物半导体材料用作氧化物半导体层106a的情况下，结晶区110可包括用InGaO₃(ZnO)_m(m：整数)所代表的晶体、用In₂Ga₂ZnO₇所代表的晶体，等。由于第二热处理，这样的晶体被对齐，从而其c-轴处于与氧化物半导体层106a的表面基本垂直的方向。For example, in the case where an In-Ga-Zn-O-based oxide semiconductor material is used as the oxide semiconductor layer 106a, the crystallization region 110 may include a crystal represented by InGaO₃ (ZnO)_m (m: integer) , a crystal represented by In₂ Ga₂ ZnO₇ , etc. Due to the second heat treatment, such crystals are aligned such that their c-axis is in a direction substantially perpendicular to the surface of the oxide semiconductor layer 106a.

此处，上述晶体包括In、Ga和Zn中的任意，且可被认为具有平行于a-轴和b-轴的层的层叠结构。特定地，上述晶体具有其中在c-轴方向中层叠包括In的层和不包括In的层(包括Ga或Zn的层)的结构。Here, the above crystal includes any of In, Ga, and Zn, and can be considered to have a stacked structure of layers parallel to the a-axis and b-axis. Specifically, the above crystal has a structure in which a layer including In and a layer not including In (a layer including Ga or Zn) are stacked in the c-axis direction.

在In-Ga-Zn-O-基氧化物半导体晶体中，在与a-轴和b-轴平行的方向中包括In的层的导电率是良好的。这是由于，导电率主要受控于In-Ga-Zn-O-基氧化物半导体晶体中的In，以及一个In原子的5s轨道与相邻In原子的5s轨道相交迭且藉此形成了载流子路径。在与上述层垂直的方向中(即，c-轴方向)，增加了绝缘性质。In the In-Ga-Zn-O-based oxide semiconductor crystal, the conductivity of the layer including In in the direction parallel to the a-axis and the b-axis is good. This is because the conductivity is mainly controlled by In in the In-Ga-Zn-O-based oxide semiconductor crystal, and the 5s orbital of an In atom overlaps with the 5s orbital of an adjacent In atom and thereby forms a carrier stream path. In the direction perpendicular to the above-mentioned layers (ie, the c-axis direction), the insulating properties are increased.

通过如上所述地包括结晶区110，氧化物半导体层106a可具有电各向异性。在上述示例中，增加了与氧化物半导体层106a的表面平行的方向中的导电率，且增加了在与氧化物半导体层106a的表面垂直的方向中的绝缘性质。因此，使用如上所述的包括结晶区110的氧化物半导体层106a，可实现具有良好电特性的半导体器件。By including the crystalline region 110 as described above, the oxide semiconductor layer 106a can have electrical anisotropy. In the above example, the electrical conductivity in the direction parallel to the surface of the oxide semiconductor layer 106a is increased, and the insulating property is increased in the direction perpendicular to the surface of the oxide semiconductor layer 106a. Therefore, using the oxide semiconductor layer 106a including the crystalline region 110 as described above, a semiconductor device having good electrical characteristics can be realized.

注意，优选的是在结晶区110下留有非晶结构等，因为可防止结晶区110中流动的载流子受到与绝缘层102间的界面的影响。Note that it is preferable to leave an amorphous structure or the like under the crystalline region 110 because carriers flowing in the crystalline region 110 can be prevented from being affected by the interface with the insulating layer 102 .

接着，在不暴露于空气的情况下，栅绝缘层112被形成为与氧化物半导体层106a的一部分接触(参见图13B)。栅绝缘层112可通过CVD法、溅射法等形成。优选形成栅绝缘层112从而包括氧化硅、氮化硅、氧氮化硅、氮氧化硅、氧化铝、氧化铪、氧化钽等。注意，栅绝缘层112可具有单层结构或层叠结构。对栅绝缘层112的厚度没有具体限制；例如，栅绝缘层112的厚度可以是10nm至500nm。Next, the gate insulating layer 112 is formed in contact with a part of the oxide semiconductor layer 106a without being exposed to air (see FIG. 13B ). The gate insulating layer 112 may be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 112 is preferably formed so as to include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 112 may have a single-layer structure or a stacked structure. There is no specific limitation on the thickness of the gate insulating layer 112; for example, the thickness of the gate insulating layer 112 may be 10 nm to 500 nm.

注意，通过移除杂质等而获得的i-型或基本i-型的氧化物半导体(被提纯的氧化物半导体)高度易于受到界面状态或界面电荷的影响；因此，栅绝缘层112需要具有高质量。Note that an i-type or substantially i-type oxide semiconductor (purified oxide semiconductor) obtained by removing impurities or the like is highly susceptible to the influence of interface states or interface charges; therefore, the gate insulating layer 112 needs to have a high quality.

例如，使用微波(2.45GHz)的高密度等离子体CVD法是良好的，其中栅绝缘层112可以是致密的且具有高耐压和高质量。这是由于被提纯的氧化物半导体层和高质量栅绝缘层之间的紧密接触减少了界面状态并产生理想的界面特性。For example, a high-density plasma CVD method using microwaves (2.45 GHz) is good, in which the gate insulating layer 112 can be dense and have high withstand voltage and high quality. This is because close contact between the purified oxide semiconductor layer and the high-quality gate insulating layer reduces interface states and produces desirable interface characteristics.

毋庸赘言，只要可形成高质量的绝缘层作为栅绝缘层112，也可采用诸如溅射法或等离子体CVD法之类的另一种方法。此外，有可能使用其质量、界面特性等通过在形成绝缘层之后进行的热处理而得以改进的绝缘层。在任何情况下，提供了具有减少的界面态密度且可形成与氧化物半导体层间的良好界面且具有良好膜质量的绝缘层，作为栅绝缘层112。Needless to say, another method such as a sputtering method or a plasma CVD method may also be used as long as a high-quality insulating layer can be formed as the gate insulating layer 112 . In addition, it is possible to use an insulating layer whose quality, interface characteristics, etc. are improved by heat treatment performed after forming the insulating layer. In any case, an insulating layer having a reduced interface state density and capable of forming a good interface with the oxide semiconductor layer and having good film quality is provided as gate insulating layer 112 .

通过如此改进与栅绝缘层的界面的特性并从氧化物半导体中消除杂质，特别是氢、水等，可能获得稳定的晶体管，其阈值电压(V_th)不随着栅极偏压-温度应力测试(BT测试，如，在85℃和2×10⁶V/cm达12小时)而变化。By thus improving the characteristics of the interface with the gate insulating layer and eliminating impurities, especially hydrogen, water, etc., from the oxide semiconductor, it is possible to obtain a stable transistor whose threshold voltage (V_th ) does not vary with the gate bias-temperature stress test (BT test, eg, at 85°C and 2×10⁶ V/cm for 12 hours) varies.

此后，优选地在惰性气体气氛或氧气氛中执行第三热处理。该热处理的温度被设置在200℃到400℃范围内，优选在250℃至350℃。例如，可在氮气氛中、在250℃下执行一小时的热处理。第三热处理可减少晶体管的电特性的变化。进一步，通过该第三热处理，可将氧提供给氧化物半导体层106a。注意，在目标为向氧化物半导体层106a提供氧的情况下，优选的是在通过溅射法形成氧化硅膜作为栅绝缘层112之后执行该第三热处理。Thereafter, a third heat treatment is preferably performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of this heat treatment is set in the range of 200°C to 400°C, preferably in the range of 250°C to 350°C. For example, heat treatment may be performed at 250° C. for one hour in a nitrogen atmosphere. The third heat treatment can reduce variations in electrical characteristics of the transistor. Further, by this third heat treatment, oxygen can be supplied to the oxide semiconductor layer 106a. Note that in the case where the aim is to supply oxygen to the oxide semiconductor layer 106a, it is preferable to perform this third heat treatment after forming a silicon oxide film as the gate insulating layer 112 by a sputtering method.

注意，在这个实施例中在栅绝缘层112形成之后执行该第三热处理；只要在第二热处理之后执行，对于第三热处理的时间没有特别限制。此外，该第三热处理不是必要步骤。Note that this third heat treatment is performed after the gate insulating layer 112 is formed in this embodiment; there is no particular limitation on the time of the third heat treatment as long as it is performed after the second heat treatment. Also, this third heat treatment is not an essential step.

接着，在栅绝缘层112上与氧化物半导体层106a相交迭的区域中(特别是在与结晶区110相交迭的区域中)的栅绝缘层112上形成栅电极层114(见图13C)。可通过在栅绝缘层112上形成导电层且然后选择性地蚀刻该导电层而形成栅电极层114。Next, gate electrode layer 114 is formed on gate insulating layer 112 in a region overlapping oxide semiconductor layer 106a (particularly, in a region overlapping crystalline region 110) on gate insulating layer 112 (see FIG. 13C). The gate electrode layer 114 may be formed by forming a conductive layer on the gate insulating layer 112 and then selectively etching the conductive layer.

导电层可通过诸如溅射法之类的PVD法、或者诸如等离子体CVD法之类的CVD法形成。可使用从铝、铬、铜、钽、钛、钼、以及钨中选择的元素、包含这些元素中的任意作为组分的合金等形成导电层。可使用包含锰、镁、锆和铍中的一种或多种的材料。可使用包括铝与从钛、钽、钨、钼、铬、钕、和钪中选择的一种或多种元素的材料。The conductive layer can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing any of these elements as a component, or the like. A material containing one or more of manganese, magnesium, zirconium, and beryllium may be used. A material including aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

也可使用导电金属氧化物来形成该导电层。作为导电金属氧化物，可使用氧化铟(In₂O₃)、氧化锡(SnO₂)、氧化锌(ZnO)、氧化铟-氧化锡合金(In₂O₃-SnO₂，在一些情况下缩写为ITO)、氧化铟-氧化锌合金(In₂O₃-ZnO)、或者包含硅或氧化硅的这些金属氧化物材料中的任一种。A conductive metal oxide may also be used to form the conductive layer. As conductive metal oxides, indium oxide (In₂ O₃ ), tin oxide (SnO₂ ), zinc oxide (ZnO), indium oxide-tin oxide alloy (In₂ O₃ -SnO₂ , abbreviated in some cases is ITO), indium oxide-zinc oxide alloy (In₂ O₃ -ZnO), or any of these metal oxide materials containing silicon or silicon oxide.

导电层可具有单层结构、或者包含两层或更多层的层叠结构。例如，导电层可具有包括硅的铝膜的单层结构、其中在铝膜上堆叠钛膜的双层结构、或者其中钛膜、铝膜、以及钛膜按该次序堆叠的三层结构。此处，使用包括钛的材料形成导电层且然后被处理为栅电极层114。The conductive layer may have a single-layer structure, or a laminated structure including two or more layers. For example, the conductive layer may have a single-layer structure of an aluminum film including silicon, a double-layer structure in which a titanium film is stacked on the aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. Here, a conductive layer is formed using a material including titanium and then processed into the gate electrode layer 114 .

接着，在栅绝缘层112和栅电极层114上形成层间绝缘层116和层间绝缘层118(见图13D)。层间绝缘层116和118可通过PVD法、CVD法等形成。可使用包括无机绝缘材料(诸如氧化硅、氮氧化硅、氮化硅、氧化铪、氧化铝、或氧化钽)的材料来形成层间绝缘层116和118。注意，在这个实施例中使用了层间绝缘层116和118的层叠结构，不过所公开的发明的实施例并不限于这个示例。也可使用单层结构或包括三层或更多层的层叠结构。Next, an interlayer insulating layer 116 and an interlayer insulating layer 118 are formed on the gate insulating layer 112 and the gate electrode layer 114 (see FIG. 13D ). The insulating interlayers 116 and 118 may be formed by a PVD method, a CVD method, or the like. The interlayer insulating layers 116 and 118 may be formed using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Note that a laminated structure of interlayer insulating layers 116 and 118 is used in this embodiment, but embodiments of the disclosed invention are not limited to this example. A single-layer structure or a laminated structure including three or more layers may also be used.

注意、理想的是形成层间绝缘层118以具有平的表面。这是因为当层间绝缘层118被形成为具有平的表面时，在该层间绝缘层118上可良好地形成电极、引线等。Note that it is desirable to form the interlayer insulating layer 118 to have a flat surface. This is because electrodes, leads, and the like can be well formed on the interlayer insulating layer 118 when the interlayer insulating layer 118 is formed to have a flat surface.

通过上述步骤，完成了具有包括结晶区110的氧化物半导体层106a的晶体管150。Through the above steps, the transistor 150 having the oxide semiconductor layer 106a including the crystallized region 110 is completed.

通过在这个实施例中所描述的方法，可在氧化物半导体层106a中形成结晶区110；相应地，可实现具有良好电特性的半导体器件。By the method described in this embodiment, the crystalline region 110 can be formed in the oxide semiconductor layer 106a; accordingly, a semiconductor device having good electrical characteristics can be realized.

通过在这个实施例中所描述的方法，氧化物半导体层106a的氢浓度为5×10¹⁹/cm³或更少，且晶体管的截止态电流为1×10^-13A或更少，这是测量极限。使用如上所述地通过充分减少氢浓度并提供氧而被提纯的氧化物半导体层106a，可获得具有良好特性的半导体器件。By the method described in this embodiment, the hydrogen concentration of the oxide semiconductor layer 106a is 5×10¹⁹ /cm³ or less, and the off-state current of the transistor is 1×10⁻¹³ A or less, which is measurement limit. Using the oxide semiconductor layer 106a purified by sufficiently reducing the hydrogen concentration and supplying oxygen as described above, a semiconductor device having good characteristics can be obtained.

如上所述，所公开的发明实现了具有新颖结构和良好特性的半导体器件。As described above, the disclosed invention realizes a semiconductor device having a novel structure and good characteristics.

<修改的示例><Modified example>

接着，将参考图14A到14C、图15A到15C、以及图16而描述在图1A和1B、图2、图3、图4A和4B、图5到11、图12A到12D、以及图13A到13D中所示出的半导体器件的修改的示例。注意，在图14A到14C、图15A到15C、以及图16中所示出的半导体器件的很多组件类似于在图1A和1B、图2、图3、图4A和4B、图5到11、图12A到12D、以及图13A到13D中所示出的半导体器件的组件；因此，仅描述不同的点。1A and 1B, FIG. 2, FIG. 3, FIGS. 4A and 4B, FIGS. 5 to 11, FIGS. 12A to 12D, and FIGS. An example of a modification of the semiconductor device shown in 13D. Note that many components of the semiconductor device shown in FIGS. 14A to 14C, FIGS. 15A to 15C, and FIG. 16 are similar to those in FIGS. Components of the semiconductor device shown in FIGS. 12A to 12D , and FIGS. 13A to 13D ; therefore, only different points will be described.

图14A中所示的晶体管150包括具有凹入部分(凹槽部分)的氧化物半导体层106a。注意，在形成源或漏电极层108a和源或漏电极层108b时，通过蚀刻形成该凹入部分。相应地，在与栅电极层114相交迭的区域中形成该凹入部分。该凹入部分可减少在沟道形成区中的半导体层的厚度，藉此对于防止短沟道效有所贡献。A transistor 150 shown in FIG. 14A includes an oxide semiconductor layer 106a having a concave portion (groove portion). Note that this concave portion is formed by etching when the source or drain electrode layer 108a and the source or drain electrode layer 108b are formed. Accordingly, the concave portion is formed in a region overlapping with the gate electrode layer 114 . The concave portion can reduce the thickness of the semiconductor layer in the channel formation region, thereby contributing to preventing the short channel effect.

图14B中所示的晶体管150包括位于源或漏电极层108a和源或漏电极层108b上，具有与源或漏电极层108a和源或漏电极层108b基本一样的形状的绝缘层109a和绝缘层109b。在这个情况下，具有减少源或漏电极层与栅电极层之间的电容(所谓的栅极电容)的优势。注意，表达“基本一样”或“基本是一样”并不必然意味着在严格意义上严格地一样且可意味着被认为是一样的。例如，由单个蚀刻工艺造成的差异是可接受的。进一步，厚度并不需要是一样的。The transistor 150 shown in FIG. 14B includes an insulating layer 109a and an insulating layer having substantially the same shape as the source or drain electrode layer 108a and the source or drain electrode layer 108b on the source or drain electrode layer 108a and the source or drain electrode layer 108b. Layer 109b. In this case, there is an advantage of reducing the capacitance between the source or drain electrode layer and the gate electrode layer (so-called gate capacitance). Note that the expression "substantially the same" or "substantially the same" does not necessarily mean strictly the same in a strict sense and may mean considered to be the same. For example, variance caused by a single etch process is acceptable. Further, the thickness need not be the same.

图14C中所示的晶体管150包括具有凹入部分(凹槽部分)的氧化物半导体层106a，且也包括位于源或漏电极层108a和源或漏电极层108b上，具有与源或漏电极层108a和源或漏电极层108b基本一样的形状的绝缘层109a和绝缘层109b。换言之，图14C中所示的晶体管150具有图14A的晶体管150和图14B的晶体管150二者的特征。这个结构带来的效果类似于在图14A和图14B的情况下所获得的效果。A transistor 150 shown in FIG. 14C includes an oxide semiconductor layer 106a having a concave portion (groove portion), and also includes a layer having a source or drain electrode layer 108a and a source or drain electrode layer 108b, which are connected to the source or drain electrode layer. Layer 108a and source or drain electrode layer 108b are substantially the same shape as insulating layer 109a and insulating layer 109b. In other words, the transistor 150 shown in FIG. 14C has features of both the transistor 150 of FIG. 14A and the transistor 150 of FIG. 14B . This structure brings about effects similar to those obtained in the cases of FIGS. 14A and 14B .

图15A中所示的晶体管150包括在源或漏电极层108a和源或漏电极层108b与氧化物半导体层106a相接触的区域中用具有低抽氧能力的材料(具有低氧亲和力的材料，诸如氮化钛、氮化钨、或铂)形成的导电层107a和导电层107b。使用具有低抽氧能力的导电层，可防止由于氧的抽取引起的氧化物半导体层变化至n-型；相应地，可防止由于氧化物半导体层变化至n-型的不均匀的变化等引起的对晶体管特性的不利影响。The transistor 150 shown in FIG. 15A includes a material having a low oxygen extraction capability (a material having a low oxygen affinity, The conductive layer 107a and the conductive layer 107b are formed such as titanium nitride, tungsten nitride, or platinum. Using a conductive layer having a low oxygen extraction capability can prevent the oxide semiconductor layer from changing to n-type due to the extraction of oxygen; adverse effects on transistor characteristics.

注意，在图15A中采用了具有两层结构的源或漏电极层108a和源或漏电极层108b；然而，所公开的发明的实施例并不限于这个结构。它们可具有由具有低抽氧能力的材料形成的导电层的单层结构或包括三层或更多层的层叠结构。在单层结构的情况下，例如，可采用氮化钛膜的单层结构。在层叠结构的情况下，例如，可采用氮化钛膜和钛膜的两层结构。Note that the source or drain electrode layer 108a and the source or drain electrode layer 108b having a two-layer structure are employed in FIG. 15A; however, embodiments of the disclosed invention are not limited to this structure. They may have a single-layer structure of a conductive layer formed of a material having a low oxygen-extraction capability or a laminated structure including three or more layers. In the case of a single-layer structure, for example, a single-layer structure of a titanium nitride film can be employed. In the case of a laminated structure, for example, a two-layer structure of a titanium nitride film and a titanium film can be employed.

图15B中所示的晶体管150包括在整个上部包含结晶区110的氧化物半导体层106a。换言之，该结晶区110相比图1A和1B、图2、图3、图4A和4B、图5到11、图12A到12D、以及图13A到13D的情况而言更为广阔。用在导电层108形成之前执行的热处理(第一热处理)形成结晶区110。在这个情况下，第一热处理再一次执行作为第二热处理；因此，可省略第二热处理。换言之，可减少制造步骤的数量。此外，可进一步增强氧化物半导体层106a的各向异性。The transistor 150 shown in FIG. 15B includes the oxide semiconductor layer 106a including the crystalline region 110 in the entire upper portion. In other words, the crystalline region 110 is wider than that of FIGS. 1A and 1B , 2 , 3 , 4A and 4B , 5 to 11 , 12A to 12D , and 13A to 13D . The crystallized region 110 is formed with heat treatment (first heat treatment) performed before the formation of the conductive layer 108 . In this case, the first heat treatment is performed again as the second heat treatment; therefore, the second heat treatment can be omitted. In other words, the number of manufacturing steps can be reduced. In addition, the anisotropy of the oxide semiconductor layer 106a can be further enhanced.

图15C中所示的晶体管150包括在源或漏电极层108a和源或漏电极层108b与氧化物半导体层106a相接触的区域中用具有低抽氧能力的材料(具有低氧亲和力的材料)形成的导电层107a和导电层107b，且还包括在整个上部包含结晶区110的氧化物半导体层106a。换言之，图15C中所示的晶体管150具有图15A的晶体管150和图15B的晶体管150二者的特征。这个结构带来的效果类似于在图15A和图15B的情况下所获得的效果。The transistor 150 shown in FIG. 15C includes a material having a low oxygen extraction capability (a material having a low oxygen affinity) used in a region where the source or drain electrode layer 108a and the source or drain electrode layer 108b are in contact with the oxide semiconductor layer 106a. The conductive layer 107a and the conductive layer 107b are formed, and also includes the oxide semiconductor layer 106a including the crystalline region 110 in the entire upper portion. In other words, the transistor 150 shown in FIG. 15C has features of both the transistor 150 of FIG. 15A and the transistor 150 of FIG. 15B . This structure brings about an effect similar to that obtained in the case of FIGS. 15A and 15B .

图16示出半导体器件的修改的示例，该半导体器件在下部中，包括包含氧化物半导体外的材料(如，硅)的晶体管250，且在其上部中，包括包含氧化物半导体的晶体管150。包括氧化物半导体的晶体管150的结构类似于图1A中所示的晶体管150的结构。16 shows a modified example of a semiconductor device including, in a lower part, a transistor 250 including a material other than an oxide semiconductor (for example, silicon), and in an upper part thereof, including a transistor 150 including an oxide semiconductor. The structure of the transistor 150 including an oxide semiconductor is similar to that of the transistor 150 shown in FIG. 1A .

晶体管250包括提供在包含半导体材料的衬底200中的沟道形成区216、提供成在其之间夹持沟道形成区216的杂质区214和高浓度杂质区220(这些区域可简单地统称为杂质区)、提供在沟道形成区216上的栅绝缘层208a、提供在栅绝缘层208a上的栅电极210a、以及电连接到杂质区214的源电极或漏电极层230a和源电极或漏电极层230b(见图16)。例如，硅衬底、SOI衬底等可被用作包含半导体材料的衬底200。The transistor 250 includes a channel formation region 216 provided in a substrate 200 containing a semiconductor material, an impurity region 214 and a high-concentration impurity region 220 provided to sandwich the channel formation region 216 therebetween (these regions may simply be collectively referred to as is an impurity region), a gate insulating layer 208a provided on the channel formation region 216, a gate electrode 210a provided on the gate insulating layer 208a, and a source or drain electrode layer 230a electrically connected to the impurity region 214 and the source electrode or Drain electrode layer 230b (see FIG. 16). For example, a silicon substrate, an SOI substrate, or the like can be used as the substrate 200 including a semiconductor material.

此处，侧壁绝缘层218被形成在栅电极层210a的侧面上。当从垂直于衬底200的主表面的方向看时，在衬底200的未与侧壁绝缘层218相交迭的区域中提供了高浓度杂质区220。金属化合物区224被提供为与高浓度杂质区220相接触。元件隔离绝缘层206设置在衬底200上以包围晶体管250。层间绝缘层226和层间绝缘层228被设置成覆盖晶体管250。源或漏电极层230a和源或漏电极层230b通过在层间绝缘层226、层间绝缘层228、以及绝缘层234中形成的开口电连接至金属化合物区224。换言之，源或漏电极层230a和源或漏电极层230b通过金属化合物区224电连接至高浓度杂质区220和杂质区214。注意，绝缘层234优选地被充分地平面化。具体地，绝缘层234可由化学机械抛光(CMP)等平面化，从而高度差变为3nm或更少，优选地为1nm或更少。通过形成如上所述地平坦的绝缘层234，可改进在绝缘层234上形成的每一个组件的平面度。Here, the sidewall insulating layer 218 is formed on the side of the gate electrode layer 210a. High-concentration impurity region 220 is provided in a region of substrate 200 that does not overlap sidewall insulating layer 218 when viewed from a direction perpendicular to the main surface of substrate 200 . Metal compound region 224 is provided in contact with high concentration impurity region 220 . An element isolation insulating layer 206 is provided on the substrate 200 to surround the transistor 250 . The interlayer insulating layer 226 and the interlayer insulating layer 228 are provided to cover the transistor 250 . Source or drain electrode layer 230 a and source or drain electrode layer 230 b are electrically connected to metal compound region 224 through openings formed in interlayer insulating layer 226 , interlayer insulating layer 228 , and insulating layer 234 . In other words, source or drain electrode layer 230 a and source or drain electrode layer 230 b are electrically connected to high concentration impurity region 220 and impurity region 214 through metal compound region 224 . Note that the insulating layer 234 is preferably sufficiently planarized. Specifically, the insulating layer 234 may be planarized by chemical mechanical polishing (CMP) or the like so that the height difference becomes 3nm or less, preferably 1nm or less. By forming the insulating layer 234 flat as described above, the flatness of each component formed on the insulating layer 234 can be improved.

晶体管150包括在绝缘层102上提供的氧化物半导体层106a(包括结晶区110)、在氧化物半导体层106a提供的且电连接至该氧化物半导体层106a的源或漏电极层108a和源或漏电极层108b、被提供为覆盖该氧化物半导体层、源或漏电极层108a和源或漏电极层108b的栅绝缘层112、以及提供在栅绝缘层112上与氧化物半导体层106a相交迭的区域中的栅电极层114(见图16)。注意，优选的是如上所述地充分平面化绝缘层234，从而在其上形成的绝缘层102和氧化物半导体层106a可被制成为足够平坦。在如上所述地平坦的氧化物半导体层106a中形成的结晶区的结晶度可被制成为良好的。The transistor 150 includes an oxide semiconductor layer 106a (including the crystallization region 110) provided on the insulating layer 102, a source or drain electrode layer 108a provided on the oxide semiconductor layer 106a and electrically connected to the oxide semiconductor layer 106a, and a source or drain electrode layer 108a. The drain electrode layer 108b, the gate insulating layer 112 provided to cover the oxide semiconductor layer, the source or drain electrode layer 108a, and the source or drain electrode layer 108b, and the gate insulating layer 112 provided to overlap the oxide semiconductor layer 106a The gate electrode layer 114 in the region (see FIG. 16 ). Note that it is preferable to sufficiently planarize the insulating layer 234 as described above so that the insulating layer 102 and the oxide semiconductor layer 106 a formed thereon can be made sufficiently flat. The crystallinity of the crystallized region formed in the oxide semiconductor layer 106a that is flat as described above can be made good.

此外，层间绝缘层116和层间绝缘层118被提供在晶体管150上。此处，在栅绝缘层112、层间绝缘层116、以及层间绝缘层118中形成达到源或漏电极层108a和源或漏电极层108b的开口。电极层254d和电极层254e被形成为分别通过相应开口与源电极或漏电极层108a以及源电极或漏电极层108b接触。与电极层254d和254e类似，电极层254a、电极层254b、以及电极层254c被形成为分别通过在绝缘层102、栅绝缘层112、层间绝缘层116、以及层间绝缘层118中所提供的开口与电极层236a、电极层236b、以及电极层236c相接触。In addition, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150 . Here, openings reaching the source or drain electrode layer 108 a and the source or drain electrode layer 108 b are formed in the gate insulating layer 112 , the interlayer insulating layer 116 , and the interlayer insulating layer 118 . The electrode layer 254d and the electrode layer 254e are formed to be in contact with the source or drain electrode layer 108a and the source or drain electrode layer 108b through the corresponding openings, respectively. Similar to the electrode layers 254d and 254e, the electrode layer 254a, the electrode layer 254b, and the electrode layer 254c are formed by providing in the insulating layer 102, the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118, respectively. The openings are in contact with the electrode layer 236a, the electrode layer 236b, and the electrode layer 236c.

绝缘层256设置在层间绝缘层118上。电极层258a、电极层258b、电极层258c、以及电极层258d被提供成嵌入绝缘层256内。此处，电极层258a与电极层254a相接触。电极层258b与电极层254b接触。电极层258c与电极层254c和电极层254d相接触。电极层258d与电极层254e接触。The insulating layer 256 is disposed on the interlayer insulating layer 118 . An electrode layer 258 a , an electrode layer 258 b , an electrode layer 258 c , and an electrode layer 258 d are provided embedded within the insulating layer 256 . Here, the electrode layer 258a is in contact with the electrode layer 254a. The electrode layer 258b is in contact with the electrode layer 254b. The electrode layer 258c is in contact with the electrode layer 254c and the electrode layer 254d. The electrode layer 258d is in contact with the electrode layer 254e.

换言之，晶体管150的源或漏电极层108a通过电极层230c、电极层236c、电极层254c、电极层258c、以及电极层254d(见图16)电连接至另一个元件(诸如包含氧化物半导体外的材料的晶体管)。此外，晶体管150的源或漏电极层108b通过电极层254e和电极层258d电连接至另一个元件。注意，连接电极(诸如电极层230c、电极层236c、电极层254c、电极层258c、以及电极层254d)的结构并不限于上述结构，且合适的增加、省略等是可能的。In other words, the source or drain electrode layer 108a of the transistor 150 is electrically connected to another element (such as an external element including an oxide semiconductor) through the electrode layer 230c, the electrode layer 236c, the electrode layer 254c, the electrode layer 258c, and the electrode layer 254d (see FIG. 16 ). material transistors). In addition, the source or drain electrode layer 108b of the transistor 150 is electrically connected to another element through the electrode layer 254e and the electrode layer 258d. Note that the structure of the connection electrodes such as the electrode layer 230c, the electrode layer 236c, the electrode layer 254c, the electrode layer 258c, and the electrode layer 254d is not limited to the above-mentioned structure, and appropriate additions, omissions, etc. are possible.

优选的是使用包含铜的材料用于上述各电极的部分(包括引线)。在为电极的部分等使用包含铜的材料的情况下，可改进电极等的导电率。例如，可由其中在绝缘层中所提供的开口中通过PVD法或CVD法形成阻挡膜(钛膜、氮化钛膜等)且然后用电镀法等形成铜膜的方法(所谓镶嵌法)而形成这样的电极与引线。It is preferable to use a material containing copper for parts (including lead wires) of the above-mentioned respective electrodes. In the case of using a material containing copper for parts of the electrodes and the like, the conductivity of the electrodes and the like can be improved. For example, it can be formed by a method (so-called damascene method) in which a barrier film (a titanium film, a titanium nitride film, etc.) is formed by a PVD method or a CVD method in an opening provided in an insulating layer, and then a copper film is formed by an electroplating method or the like Such electrodes and leads.

如图16中所示，在所公开的发明的实施例中，可在各种衬底(半导体衬底、绝缘衬底、或金属衬底)、绝缘膜、半导体膜、金属膜等的给定表面上形成包括结晶区的氧化物半导体层。换言之，可在提供有集成电路的衬底上毫无困难地形成结晶氧化物半导体层。因此，可易于实现三维集成。As shown in FIG. 16, in an embodiment of the disclosed invention, a given substrate (semiconductor substrate, insulating substrate, or metal substrate), insulating film, semiconductor film, metal film, etc. An oxide semiconductor layer including a crystalline region is formed on the surface. In other words, a crystalline oxide semiconductor layer can be formed without difficulty on a substrate provided with an integrated circuit. Therefore, three-dimensional integration can be easily realized.

如上所述，可将所公开的发明的实施例改变为各种模式。此外，修改的示例不限于上述示例。例如，图14A、图14B、图14C、图15A、图15B、图15C、以及图16的结构可被适当地组合为另一个修改的示例。毋庸赘言，在本说明书等的描述的范围内添加、省略等是可能的。As described above, the disclosed embodiments of the invention can be changed into various modes. In addition, modified examples are not limited to the above-mentioned examples. For example, the structures of FIGS. 14A , 14B, 14C, 15A, 15B, 15C, and 16 may be appropriately combined as another modified example. Needless to say, addition, omission, and the like are possible within the scope of the description in this specification and the like.

本实施例中描述的结构、方法等可与其他实施例中描述的任一结构、方法等适当地组合。The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

(实施例2)(Example 2)

在这个实施例中，将参考图17A和17B、图18A到18C、图19A到19C、图20A到20D、图21A到21C、以及图22A到22C而描述具有与上述实施例的半导体器件不同的结构的半导体器件以及其制造方法。注意在这个实施例所描述的结构在很多点上类似于上述实施例中所描述的结构；因此，下文主要描述不同点。In this embodiment, a semiconductor device having a structure different from that of the above-described embodiment will be described with reference to FIGS. 17A and 17B, FIGS. 18A to 18C, FIGS. 19A to 19C, FIGS. Structured semiconductor devices and their fabrication methods. Note that the structure described in this embodiment is similar in many points to the structure described in the above-mentioned embodiments; therefore, different points will be mainly described below.

<半导体器件的结构><Structure of Semiconductor Device>

图17A和17B是各自示出作为半导体器件的结构的示例的晶体管150的截面图。17A and 17B are cross-sectional views each showing a transistor 150 as an example of the structure of a semiconductor device.

与图1A和1B的结构不同的点在于在氧化物半导体层106a下提供栅电极层101a。换言之，在图17A或17B中所示的晶体管150包括在衬底100上的栅电极层101a、覆盖该栅电极层101a的绝缘层102、位于绝缘层102上的氧化物半导体层106a、在该氧化物半导体层106a中的结晶区110、电连接至该氧化物半导体层106a的源或漏电极层108a和源或漏电极层108b、覆盖该氧化物半导体层106a、源或漏电极层108a和源或漏电极层108b的栅绝缘层112、以及位于栅绝缘层112上的栅电极层114(见图17A和17B)。此处，绝缘层102也用作栅绝缘层。此处，图17A示出其中源或漏电极层108a和源或漏电极层108b具有层叠结构的情况，且图17B示出其中源或漏电极层108a和源或漏电极层108b具有单层结构的情况。注意，在单层结构的情况下，易于实现良好的楔形。A point different from the structure of FIGS. 1A and 1B is that the gate electrode layer 101a is provided under the oxide semiconductor layer 106a. In other words, the transistor 150 shown in FIG. 17A or 17B includes the gate electrode layer 101a on the substrate 100, the insulating layer 102 covering the gate electrode layer 101a, the oxide semiconductor layer 106a on the insulating layer 102, the The crystalline region 110 in the oxide semiconductor layer 106a, the source or drain electrode layer 108a and the source or drain electrode layer 108b electrically connected to the oxide semiconductor layer 106a, the source or drain electrode layer 108a covering the oxide semiconductor layer 106a, the source or drain electrode layer 108a and The gate insulating layer 112 of the source or drain electrode layer 108b, and the gate electrode layer 114 on the gate insulating layer 112 (see FIGS. 17A and 17B ). Here, the insulating layer 102 also functions as a gate insulating layer. Here, FIG. 17A shows a case where the source or drain electrode layer 108a and the source or drain electrode layer 108b have a stacked structure, and FIG. 17B shows a case where the source or drain electrode layer 108a and the source or drain electrode layer 108b have a single-layer structure Case. Note that a good wedge shape is easy to achieve in the case of a single layer structure.

以与图1A和1B中所示的结构类似的方式，氧化物半导体层106a包括结晶区110。该区域对应于包含氧化物半导体层106a的表面的区域，换言之，包含与栅绝缘层112相接触的部分的区域。In a similar manner to the structure shown in FIGS. 1A and 1B , the oxide semiconductor layer 106 a includes a crystalline region 110 . This region corresponds to a region including the surface of the oxide semiconductor layer 106 a , in other words, a region including a portion in contact with the gate insulating layer 112 .

此外，层间绝缘层116和层间绝缘层118被提供在晶体管150上。注意，层间绝缘层116和层间绝缘层118并不是必须的组件且因此合适时可被省略。In addition, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150 . Note that the interlayer insulating layer 116 and the interlayer insulating layer 118 are not essential components and thus may be omitted as appropriate.

此处省略了每一个组件的细节，因为这些可参考前述实施例。The details of each component are omitted here since these refer to the previous embodiments.

在如图17A和17B中所示的结构中，通过使用被提纯且包括结晶区110的氧化物半导体层106a，可实现具有良好电特性的半导体器件。In the structure as shown in FIGS. 17A and 17B , by using the oxide semiconductor layer 106 a that is purified and includes the crystalline region 110 , a semiconductor device having good electrical characteristics can be realized.

此外，结晶区110相比氧化物半导体层106a中的其他区域是稳定的，且因此可防止杂质(如，水分等)进入氧化物半导体层106a。因此，可获得氧化物半导体层106a的可靠性。In addition, the crystalline region 110 is stable compared to other regions in the oxide semiconductor layer 106a, and thus can prevent impurities (eg, moisture, etc.) from entering the oxide semiconductor layer 106a. Therefore, the reliability of the oxide semiconductor layer 106a can be obtained.

进一步，使用作为所谓背栅极的栅电极层101a，可易于控制晶体管150的电特性。注意，可将与施加至栅电极层114的电位相同或不同的电位施加至栅电极层101a。可选地，栅电极层101a可处于浮动状态。Further, using the gate electrode layer 101a as a so-called back gate, the electrical characteristics of the transistor 150 can be easily controlled. Note that the same or different potential from that applied to the gate electrode layer 114 may be applied to the gate electrode layer 101a. Alternatively, the gate electrode layer 101a may be in a floating state.

<半导体器件的制造方法><Manufacturing method of semiconductor device>

接着，将参考图18A到18C、图19A到19C、以及图20A到20D而描述作为半导体器件的结构的示例的晶体管150的制造方法。Next, a method of manufacturing the transistor 150 as an example of the structure of the semiconductor device will be described with reference to FIGS. 18A to 18C , FIGS. 19A to 19C , and FIGS. 20A to 20D .

首先，在衬底100上形成导电层101(见图18A)。此处省略了衬底100的细节，因为这些可参考前述实施例。First, a conductive layer 101 is formed on a substrate 100 (see FIG. 18A). Details of the substrate 100 are omitted here, since these refer to the previous embodiments.

导电层101可通过诸如溅射法之类的PVD法、或者诸如等离子体CVD法之类的CVD法形成。可使用从铝、铬、铜、钽、钛、钼、以及钨中选择的元素、包含这些元素中的任意作为组分的合金等形成导电层101。可使用包含锰、镁、锆和铍中的一种或多种的材料。可使用包括铝与从钛、钽、钨、钼、铬、钕、和钪中选择的一种或多种元素的材料。The conductive layer 101 can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer 101 can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing any of these elements as a component, or the like. A material containing one or more of manganese, magnesium, zirconium, and beryllium may be used. A material including aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

也可使用导电金属氧化物来形成该导电层101。作为导电金属氧化物，可使用氧化铟(In₂O₃)、氧化锡(SnO₂)、氧化锌(ZnO)、氧化铟-氧化锡合金(In₂O₃-SnO₂，在一些情况下缩写为ITO)、氧化铟-氧化锌合金(In₂O₃-ZnO)、或者包含硅或氧化硅的这些金属氧化物材料中的任一种。The conductive layer 101 may also be formed using a conductive metal oxide. As conductive metal oxides, indium oxide (In₂ O₃ ), tin oxide (SnO₂ ), zinc oxide (ZnO), indium oxide-tin oxide alloy (In₂ O₃ -SnO₂ , abbreviated in some cases is ITO), indium oxide-zinc oxide alloy (In₂ O₃ -ZnO), or any of these metal oxide materials containing silicon or silicon oxide.

导电层101可具有单层结构、或者包含两层或更多层的层叠结构。在所公开的发明的实施例中，由于在导电层101形成之后在相对高温下执行热处理，导电层101优选地使用具有高耐热性的材料形成。作为具有高耐热性的材料，例如，可给出钛、钽、钨、钼等。也可使用通过添加杂质元素等而增加其导电性的多晶硅。The conductive layer 101 may have a single-layer structure, or a laminated structure including two or more layers. In an embodiment of the disclosed invention, since the heat treatment is performed at a relatively high temperature after the conductive layer 101 is formed, the conductive layer 101 is preferably formed using a material having high heat resistance. As a material having high heat resistance, for example, titanium, tantalum, tungsten, molybdenum, and the like can be given. Polysilicon whose conductivity is increased by adding impurity elements and the like may also be used.

接着，选择性蚀刻导电层101；因此，形成栅电极层101a。然后，形成绝缘层102从而覆盖栅电极层101a(见图18B)。Next, the conductive layer 101 is selectively etched; thus, the gate electrode layer 101a is formed. Then, insulating layer 102 is formed so as to cover gate electrode layer 101a (see FIG. 18B).

对于在形成用于蚀刻的掩模时的曝光，优选使用紫外光、KrF激光、或ArF激光。特别对于在沟道长度(L)小于25nm的情况下的曝光，优选用其波长为极短的几纳米至几十纳米的极紫外光来进行用于形成掩模的曝光。在使用极紫外光的曝光时，分辨率高且聚焦深度大，这适于微型化。For exposure when forming a mask for etching, ultraviolet light, KrF laser, or ArF laser is preferably used. Especially for exposure in the case where the channel length (L) is less than 25 nm, it is preferable to perform exposure for mask formation with extreme ultraviolet light whose wavelength is extremely short from several nanometers to several tens of nanometers. In exposure using extreme ultraviolet light, the resolution is high and the depth of focus is large, which is suitable for miniaturization.

栅电极层101a是所谓背栅极。使用栅电极层101a，氧化物半导体层106a中的电场可被控制，藉此可控制晶体管150的电特性。注意，栅电极层101a可电连接至另一个引线、电极等，从而电位被施加至栅电极层101a，或栅电极层101a可被绝缘从而处于浮动状态。The gate electrode layer 101a is a so-called back gate. Using the gate electrode layer 101a, the electric field in the oxide semiconductor layer 106a can be controlled, whereby the electrical characteristics of the transistor 150 can be controlled. Note that the gate electrode layer 101a may be electrically connected to another lead, electrode, or the like so that a potential is applied to the gate electrode layer 101a, or the gate electrode layer 101a may be insulated so as to be in a floating state.

注意“栅电极”一般是指电位可被有意地控制的栅电极；在本说明书中的“栅电极”还指电位未被有意地控制的栅电极。例如，如上所述的被绝缘且处于浮动状态的导电层，在一些情况下，被称为“栅电极层”。Note that "gate electrode" generally refers to a gate electrode whose potential can be intentionally controlled; "gate electrode" in this specification also refers to a gate electrode whose potential is not intentionally controlled. For example, the conductive layer that is insulated and in a floating state as described above is called a "gate electrode layer" in some cases.

绝缘层102用作基底且还作为栅绝缘层。绝缘层102可通过CVD法、溅射法等形成。优选形成栅绝缘层102从而包括氧化硅、氮化硅、氧氮化硅、氮氧化硅、氧化铝、氧化铪、氧化钽等。注意，绝缘层102可具有单层结构或层叠结构。对绝缘层102的厚度没有具体限制；例如，绝缘层102可具有10nm至500nm的厚度。The insulating layer 102 serves as a base and also serves as a gate insulating layer. The insulating layer 102 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 102 is preferably formed so as to include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the insulating layer 102 may have a single-layer structure or a laminated structure. There is no specific limitation on the thickness of the insulating layer 102; for example, the insulating layer 102 may have a thickness of 10 nm to 500 nm.

如果在绝缘层102中包含氢、水等，氢可进入氧化物半导体层或从氧化物半导体层中抽取氧，藉此晶体管的特性可被劣化。因此，理想的是形成绝缘层102从而包括尽可能少的氢或水。If hydrogen, water, or the like is contained in the insulating layer 102, hydrogen may enter the oxide semiconductor layer or extract oxygen from the oxide semiconductor layer, whereby the characteristics of the transistor may be degraded. Therefore, it is desirable to form the insulating layer 102 so as to include as little hydrogen or water as possible.

在使用溅射法等的情况下，例如，理想的是在移除了处理腔室中剩余的水分的状态中形成绝缘层102。为了去除残留在处理腔室中的水分，优选使用诸如低温泵、离子泵、或钛升华泵的截留真空泵。可使用设置有冷阱的涡轮泵。从用低温泵等抽空的处理腔室中，氢、水等被充分移除；因此，绝缘层102中的杂质可被减少。In the case of using a sputtering method or the like, for example, it is desirable to form the insulating layer 102 in a state in which moisture remaining in the processing chamber is removed. In order to remove the moisture remaining in the processing chamber, it is preferable to use a trap vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. A turbo pump provided with a cold trap can be used. From the processing chamber evacuated with a cryopump or the like, hydrogen, water, and the like are sufficiently removed; therefore, impurities in the insulating layer 102 can be reduced.

在形成绝缘层102时，理想的是使用其中诸如氢或水之类的杂质被减少至约百万分之几(优选地为十亿分之几)的浓度的高纯度气体。In forming the insulating layer 102, it is desirable to use a high-purity gas in which impurities such as hydrogen or water are reduced to a concentration of about several parts per million (preferably several parts per billion).

注意，绝缘层102需要具有高质量，与栅绝缘层112的质量类似。因此，优选地通过可为栅绝缘层112所采用的方法来形成绝缘层102。此处省略了细节，因为这些可参考前述实施例。Note that the insulating layer 102 needs to be of high quality, similar to that of the gate insulating layer 112 . Therefore, the insulating layer 102 is preferably formed by a method that can be employed for the gate insulating layer 112 . Details are omitted here, since these refer to the previous embodiments.

接着，在绝缘层102上形成氧化物半导体层106(见图18C)。对于氧化物半导体层106的细节，可参考前述实施例。Next, an oxide semiconductor layer 106 is formed on the insulating layer 102 (see FIG. 18C ). For details of the oxide semiconductor layer 106, the foregoing embodiments can be referred to.

接着，通过诸如使用掩模的蚀刻之类的方法处理氧化物半导体层106；因此，形成具有岛状形状的氧化物半导体层106a(见图19A)。此处，需要注意的是在与栅电极层101a相交迭的区域中形成氧化物半导体层106a。对于细节，可参考前述实施例。Next, the oxide semiconductor layer 106 is processed by a method such as etching using a mask; thus, the oxide semiconductor layer 106a having an island shape is formed (see FIG. 19A ). Here, it is to be noted that the oxide semiconductor layer 106a is formed in a region overlapping with the gate electrode layer 101a. For details, reference may be made to the foregoing embodiments.

在那之后，优选地在氧化物半导体层106a上进行热处理(第一热处理)。通过该第一热处理可移除氧化物半导体层106a中包含的水(包括羟基)、氢等。例如，第一热处理的温度可被设置为高于或等于300℃且低于550℃，优选高于或等于400℃且低于550℃。注意，该第一热处理可再次执行作为随后要执行的第二热处理(用于形成结晶区的热处理)。在这个情况下，热处理的温度优选地被设置为高于或等于550℃且低于或等于850℃。此处省略了热处理的细节，因为这些可参考前述实施例。After that, heat treatment (first heat treatment) is preferably performed on the oxide semiconductor layer 106a. Water (including hydroxyl groups), hydrogen, and the like contained in the oxide semiconductor layer 106a can be removed by this first heat treatment. For example, the temperature of the first heat treatment may be set to be higher than or equal to 300°C and lower than 550°C, preferably higher than or equal to 400°C and lower than 550°C. Note that this first heat treatment may be performed again as the second heat treatment (heat treatment for forming a crystalline region) to be performed subsequently. In this case, the temperature of the heat treatment is preferably set to be higher than or equal to 550°C and lower than or equal to 850°C. The details of the heat treatment are omitted here, since these refer to the previous examples.

接着，形成导电层108从而与该氧化物半导体层106a相接触(见图19B)。然后，选择性蚀刻导电层108；因此，形成源或漏电极层108a和源或漏电极层108b(见图19C)。对于导电层108、源或漏电极层108a、源或漏电极层108b、蚀刻步骤等的细节，可参考前述实施例。Next, a conductive layer 108 is formed so as to be in contact with the oxide semiconductor layer 106a (see FIG. 19B ). Then, the conductive layer 108 is selectively etched; thus, the source or drain electrode layer 108a and the source or drain electrode layer 108b are formed (see FIG. 19C ). For details of the conductive layer 108 , the source or drain electrode layer 108 a , the source or drain electrode layer 108 b , etching steps, etc., reference may be made to the foregoing embodiments.

接着，在氧化物半导体层106a上进行热处理(第二热处理)。通过这个第二热处理，在包括氧化物半导体层106a的表面的区域中形成结晶区110(见图20A)。注意，结晶区110的范围取决于氧化物半导体层106a的材料、热处理的条件等而变化。例如，结晶区110可被形成至氧化物半导体层106a的较低界面处。对于第二热处理的细节等，可参考前述实施例。Next, heat treatment (second heat treatment) is performed on the oxide semiconductor layer 106a. Through this second heat treatment, a crystallization region 110 is formed in a region including the surface of the oxide semiconductor layer 106a (see FIG. 20A ). Note that the range of the crystallization region 110 varies depending on the material of the oxide semiconductor layer 106a, the conditions of heat treatment, and the like. For example, the crystallization region 110 may be formed up to the lower interface of the oxide semiconductor layer 106a. For details and the like of the second heat treatment, the foregoing embodiments can be referred to.

接着，在不暴露于空气的情况下，栅绝缘层112被形成为与氧化物半导体层106a的一部分接触(参见图20B)。此后，在栅绝缘层112上与氧化物半导体层106a相交迭的区域中(特别是在与结晶区110相交迭的区域中)形成栅电极层114(见图20C)。然后，在栅绝缘层112和栅电极层114上形成层间绝缘层116和层间绝缘层118(见图20D)。对于上述步骤的细节，可参考前述实施例。Next, the gate insulating layer 112 is formed in contact with a part of the oxide semiconductor layer 106a without being exposed to air (see FIG. 20B ). Thereafter, gate electrode layer 114 is formed on gate insulating layer 112 in a region overlapping oxide semiconductor layer 106a (particularly, in a region overlapping crystalline region 110) (see FIG. 20C ). Then, an interlayer insulating layer 116 and an interlayer insulating layer 118 are formed on the gate insulating layer 112 and the gate electrode layer 114 (see FIG. 20D ). For the details of the above steps, reference may be made to the foregoing embodiments.

通过在这个实施例中所描述的方法，可在氧化物半导体层106a中形成结晶区110；相应地，可实现具有良好电特性的半导体器件。By the method described in this embodiment, the crystalline region 110 can be formed in the oxide semiconductor layer 106a; accordingly, a semiconductor device having good electrical characteristics can be realized.

通过在这个实施例中所描述的方法，氧化物半导体层106a的氢浓度为5×10¹⁹/cm³或更少，且晶体管的截止态电流为1×10^-13A或更少，这是测量极限。使用如上所述地通过充分减少氢浓度并提供氧而被提纯的氧化物半导体层106a，可获得具有良好特性的半导体器件。By the method described in this embodiment, the hydrogen concentration of the oxide semiconductor layer 106a is 5×10¹⁹ /cm³ or less, and the off-state current of the transistor is 1×10⁻¹³ A or less, which is measurement limit. Using the oxide semiconductor layer 106a purified by sufficiently reducing the hydrogen concentration and supplying oxygen as described above, a semiconductor device having good characteristics can be obtained.

进一步，使用用作所谓背栅极的栅电极层，可易于控制半导体器件的电特性。Further, using the gate electrode layer serving as a so-called back gate, the electrical characteristics of the semiconductor device can be easily controlled.

如上所述，所公开的发明实现了具有新颖结构和良好特性的半导体器件。As described above, the disclosed invention realizes a semiconductor device having a novel structure and good characteristics.

<修改的示例><Modified example>

接着，将参考图21A到21C以及图22A到22C而描述图17A和17B、图18A到18C、图19A到19C、以及图20A到20D中所示的半导体器件的修改的示例。注意，图21A到21C以及图22A到22C中所示的半导体器件的很多组件类似于图17A和17B、图18A到18C、图19A到19C、以及图20A到20D所示的半导体器件的组件；因此，将仅描述不同点。Next, modified examples of the semiconductor devices shown in FIGS. 17A and 17B , FIGS. 18A to 18C , FIGS. 19A to 19C , and FIGS. 20A to 20D will be described with reference to FIGS. 21A to 21C and FIGS. 22A to 22C . Note that many components of the semiconductor device shown in FIGS. 21A to 21C and FIGS. 22A to 22C are similar to those of the semiconductor device shown in FIGS. 17A and 17B, FIGS. 18A to 18C, FIGS. 19A to 19C, and FIGS. 20A to 20D; Therefore, only different points will be described.

图21A中所示的晶体管150包括具有凹入部分(凹槽部分)的氧化物半导体层106a。注意，在形成源或漏电极层108a和源或漏电极层108b时，通过蚀刻形成该凹入部分。相应地，在与栅电极层114相交迭的区域中形成该凹入部分。该凹入部分可减少在沟道形成区中的半导体层的厚度，藉此对于防止短沟道效有所贡献。A transistor 150 shown in FIG. 21A includes an oxide semiconductor layer 106a having a concave portion (groove portion). Note that this concave portion is formed by etching when the source or drain electrode layer 108a and the source or drain electrode layer 108b are formed. Accordingly, the concave portion is formed in a region overlapping with the gate electrode layer 114 . The concave portion can reduce the thickness of the semiconductor layer in the channel formation region, thereby contributing to preventing the short channel effect.

图21B中所示的晶体管150包括位于源或漏电极层108a和源或漏108b上，具有与源或漏电极层108a和源或漏108b基本一样的形状的绝缘层109a和绝缘层109b。在这个情况下，具有可减少源或漏电极层与栅电极层之间之间的电容(所谓的栅极电容)的优势。注意，表达“基本一样”或“基本是一样”并不必然意味着在严格意义上严格地一样且可意味着被认为是一样的。例如，由单个蚀刻工艺造成的差异是可接受的。进一步，厚度并不需要是一样的。Transistor 150 shown in FIG. 21B includes insulating layer 109a and insulating layer 109b having substantially the same shape as source or drain electrode layer 108a and source or drain 108b on source or drain electrode layer 108a and source or drain 108b. In this case, there is an advantage that the capacitance between the source or drain electrode layer and the gate electrode layer (so-called gate capacitance) can be reduced. Note that the expression "substantially the same" or "substantially the same" does not necessarily mean strictly the same in a strict sense and may mean considered to be the same. For example, variance caused by a single etch process is acceptable. Further, the thickness need not be the same.

图21C中所示的晶体管150包括具有凹入部分(凹槽部分)的氧化物半导体层106a，且也包括位于源或漏电极层108a和源或漏电极层108b上，具有与源或漏电极层108a和源或漏电极层108b基本一样的形状的绝缘层109a和绝缘层109b。换言之，图21C中所示的晶体管150具有图21A的晶体管150和图21B的晶体管150的特征。这个结构带来的效果类似于在图21A和图21B的情况下所获得的效果。A transistor 150 shown in FIG. 21C includes an oxide semiconductor layer 106a having a concave portion (groove portion), and also includes a layer 108a located on the source or drain electrode layer 108a and a source or drain electrode layer 108b, having the same structure as the source or drain electrode layer. Layer 108a and source or drain electrode layer 108b are substantially the same shape as insulating layer 109a and insulating layer 109b. In other words, the transistor 150 shown in FIG. 21C has the characteristics of the transistor 150 of FIG. 21A and the transistor 150 of FIG. 21B . This structure brings about effects similar to those obtained in the cases of FIGS. 21A and 21B .

图22A中所示的晶体管150包括在源或漏电极层108a和源或漏电极层108b与氧化物半导体层106a相接触的区域中用具有低抽氧能力的材料(具有低氧亲和力的材料，诸如氮化钛、氮化钨、或铂)形成的导电层107a和导电层107b。使用如上所述的具有低抽氧能力的导电层，可防止由于氧的抽取引起的改变至n-型；相应地，可防止由于变化至n-型的不均匀变化导致的对晶体管特性的不利影响。The transistor 150 shown in FIG. 22A includes a material having a low oxygen extraction capability (a material having a low oxygen affinity, The conductive layer 107a and the conductive layer 107b are formed such as titanium nitride, tungsten nitride, or platinum. Using a conductive layer having a low oxygen extraction capability as described above, change to n-type due to oxygen extraction can be prevented; accordingly, adverse effects on transistor characteristics due to uneven change to n-type can be prevented Influence.

注意，在图22A中采用了具有两层结构的源或漏电极层108a和源或漏电极层108b；然而，所公开的发明的实施例并不限于这个结构。它们可具有由具有低抽氧能力的材料形成的导电层的单层结构或包括三层或更多层的层叠结构。在单层结构的情况下，例如，可采用氮化钛膜的单层结构。在层叠结构的情况下，例如，可采用氮化钛膜和钛膜的两层结构。Note that the source or drain electrode layer 108a and the source or drain electrode layer 108b having a two-layer structure are employed in FIG. 22A; however, embodiments of the disclosed invention are not limited to this structure. They may have a single-layer structure of a conductive layer formed of a material having a low oxygen-extraction capability or a laminated structure including three or more layers. In the case of a single-layer structure, for example, a single-layer structure of a titanium nitride film can be employed. In the case of a laminated structure, for example, a two-layer structure of a titanium nitride film and a titanium film can be employed.

图22B中所示的晶体管150包括在整个上部包含结晶区110的氧化物半导体层106a。换言之，结晶区110相比图17A和17B、图18A到18C、图19A到19C、以及图20A到20D所示的情况而言更为扩展。用在导电层108形成之前执行的热处理(第一热处理)形成结晶区110。在这个情况下，第一热处理再一次执行作为第二热处理；因此，可省略第二热处理。换言之，可减少制造步骤的数量。此外，可进一步增强氧化物半导体层106a的各向异性。The transistor 150 shown in FIG. 22B includes the oxide semiconductor layer 106a including the crystalline region 110 in the entire upper portion. In other words, the crystalline region 110 is more extended than that shown in FIGS. 17A and 17B , FIGS. 18A to 18C , FIGS. 19A to 19C , and FIGS. 20A to 20D . The crystallized region 110 is formed with heat treatment (first heat treatment) performed before the formation of the conductive layer 108 . In this case, the first heat treatment is performed again as the second heat treatment; therefore, the second heat treatment can be omitted. In other words, the number of manufacturing steps can be reduced. In addition, the anisotropy of the oxide semiconductor layer 106a can be further enhanced.

图22C中所示的晶体管150包括在源或漏电极层108a和源或漏电极层108b与氧化物半导体层106a相接触的区域中用具有较低抽氧能力的材料(具有低氧亲和力的材料)形成的导电层107a和导电层107b，且还包括在整个上部包含结晶区110的氧化物半导体层106a。换言之，图22C中所示的晶体管150具有图22A的晶体管150和图22B的晶体管150的特征。这个结构带来的效果类似于在图22A和图22B的情况下所获得的效果。The transistor 150 shown in FIG. 22C includes a material having a low oxygen-extracting ability (a material having a low oxygen affinity ) formed conductive layer 107a and conductive layer 107b, and also includes the oxide semiconductor layer 106a including the crystalline region 110 in the entire upper portion. In other words, the transistor 150 shown in FIG. 22C has the characteristics of the transistor 150 of FIG. 22A and the transistor 150 of FIG. 22B. This structure brings about an effect similar to that obtained in the case of FIGS. 22A and 22B .

此外，如在上述实施例中所述，也可采用这样的结构，该结构在下部中，包括包含氧化物半导体外的材料(如，硅)的晶体管250，且在其上部中，包括包含氧化物半导体的晶体管150(见图16)。包括氧化物半导体的晶体管150的结构类似于图17A和17B等中所示的晶体管150的结构。对于细节，可参考前述实施例。Furthermore, as described in the above-described embodiments, it is also possible to employ a structure in which, in the lower part, the transistor 250 including a material other than an oxide semiconductor (for example, silicon) is included, and in its upper part, a transistor 250 including an oxide semiconductor is included. A transistor 150 (see FIG. 16 ) of a material semiconductor. The structure of the transistor 150 including an oxide semiconductor is similar to that of the transistor 150 shown in FIGS. 17A and 17B and the like. For details, reference may be made to the foregoing embodiments.

如上所述，可将所公开的发明的实施例改变为各种模式。此外，修改的示例不限于上述示例。例如，图21A、图21B、图21C、图22A、图22B、图22C等的结构可被适当地组合为另一个修改的示例。毋庸赘言，在本说明书等的描述的范围内添加、省略等是可能的。As described above, the disclosed embodiments of the invention can be changed into various modes. In addition, modified examples are not limited to the above-mentioned examples. For example, the structures of FIG. 21A, FIG. 21B, FIG. 21C, FIG. 22A, FIG. 22B, FIG. 22C, etc. may be appropriately combined as another modified example. Needless to say, addition, omission, and the like are possible within the scope of the description in this specification and the like.

本实施例中描述的结构、方法等可与其他实施例中描述的任一结构、方法等适当地组合。The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

(实施例3)(Example 3)

在这个实施例中，将参考图23A至23F来描述各自包括根据任一上述实施例的半导体器件的电子设备的示例。根据上述实施例中的任意的半导体器件具有空前良好的特性。因此，通过使用半导体器件可提供具有新颖结构的电子设备。In this embodiment, examples of electronic equipment each including the semiconductor device according to any of the above-described embodiments will be described with reference to FIGS. 23A to 23F . The semiconductor device according to any of the above-described embodiments has unprecedentedly good characteristics. Therefore, electronic equipment having a novel structure can be provided by using the semiconductor device.

图23A示出笔记本个人计算机，其包括根据上述实施例中的任意的半导体器件且包括主体301、外壳302、显示部分303、键盘304等。根据所公开的发明的半导体器件被集成、安装在电路板等之上，且被结合至外壳302中。此外，根据本发明的半导体器件可被应用于显示部分303。通过将根据所公开的发明的半导体器件应用到集成电路板上等，可实现高速电路操作。进一步，通过将根据所公开的发明的半导体器件应用到显示部分303，可显示高质量图像。通过将根据所公开的发明的半导体器件应用到上述个人计算机，可提供高性能的个人计算机。FIG. 23A shows a notebook personal computer including the semiconductor device according to any of the above-described embodiments and including a main body 301, a casing 302, a display portion 303, a keyboard 304, and the like. A semiconductor device according to the disclosed invention is integrated, mounted on a circuit board or the like, and incorporated into the housing 302 . Furthermore, the semiconductor device according to the present invention can be applied to the display portion 303 . High-speed circuit operation can be realized by applying the semiconductor device according to the disclosed invention to an integrated circuit board or the like. Further, by applying the semiconductor device according to the disclosed invention to the display portion 303, high-quality images can be displayed. By applying the semiconductor device according to the disclosed invention to the above-mentioned personal computer, a high-performance personal computer can be provided.

图23B示出包括根据以上实施例的任意的半导体器件的个人数字助理(PDA)。主体311设置有显示部分313、外部接口315、操作键314等。此外，指示笔312被设置为用于操作的附件。根据所公开的发明的半导体器件被集成、安装在电路板等之上，且被结合至主体311中。此外，根据本发明的半导体器件可被应用于显示部分313。通过将根据所公开的发明的半导体器件应用到集成电路板上等，可实现高速电路操作。进一步，通过将根据所公开的发明的半导体器件应用到显示部分313，可显示高质量图像。通过将根据所公开的发明的半导体器件应用到上述个人数字助理(PDA)，可提供高性能的个人数字助理(PDA)。FIG. 23B shows a personal digital assistant (PDA) including any semiconductor device according to the above embodiments. The main body 311 is provided with a display portion 313, an external interface 315, operation keys 314, and the like. In addition, a stylus 312 is provided as an accessory for operation. The semiconductor device according to the disclosed invention is integrated, mounted on a circuit board or the like, and incorporated into the main body 311 . Furthermore, the semiconductor device according to the present invention can be applied to the display portion 313 . High-speed circuit operation can be realized by applying the semiconductor device according to the disclosed invention to an integrated circuit board or the like. Further, by applying the semiconductor device according to the disclosed invention to the display portion 313, high-quality images can be displayed. By applying the semiconductor device according to the disclosed invention to the above-mentioned personal digital assistant (PDA), a high-performance personal digital assistant (PDA) can be provided.

图23C示出电子书320作为包括根据以上实施例的任意的半导体器件的电子纸的示例。电子书320包括两个外壳，外壳321和外壳323。外壳321和外壳323通过枢纽337组合，从而该电子书320可使用枢纽337为轴打开和关闭。利用这种结构，电子书320可像纸书一样使用。FIG. 23C shows an electronic book 320 as an example of electronic paper including any semiconductor device according to the above embodiments. The electronic book 320 includes two shells, a shell 321 and a shell 323 . The housing 321 and the housing 323 are combined by a hinge 337 so that the e-book 320 can be opened and closed using the hinge 337 for the shaft. With this structure, the electronic book 320 can be used like a paper book.

外壳321包括显示部分325，而外壳323包括显示部分327。根据所公开的发明的半导体器件被集成、安装在电路板等之上，且被结合至外壳323或外壳321中。根据本发明的半导体器件可被应用于显示部分327。显示部分325和显示部分327可显示连续图像或不同图像。用于显示不同图像的结构能使文本在右显示部分(图23C中的显示部分325)上显示、并且能使图像在左显示部分(图23C中的显示部分327)上显示。通过将根据所公开的发明的半导体器件应用到集成电路板上等，可实现高速电路操作。通过将根据所公开的发明的半导体器件应用到显示部分327，可显示高质量图像。Housing 321 includes a display portion 325 , and housing 323 includes a display portion 327 . The semiconductor device according to the disclosed invention is integrated, mounted on a circuit board or the like, and incorporated into the case 323 or the case 321 . The semiconductor device according to the present invention can be applied to the display portion 327 . The display part 325 and the display part 327 can display successive images or different images. The structure for displaying different images enables text to be displayed on the right display portion (display portion 325 in FIG. 23C ) and images to be displayed on the left display portion (display portion 327 in FIG. 23C ). High-speed circuit operation can be realized by applying the semiconductor device according to the disclosed invention to an integrated circuit board or the like. By applying the semiconductor device according to the disclosed invention to the display portion 327, high-quality images can be displayed.

图23C示出其中外壳321被提供有操作部分等的示例。例如，外壳321设置有电源开关331、操作键333、扬声器335等。操作键333允许翻页。注意，可在与显示部分同一侧的外壳的那一侧上设置键盘、指向装置等。进一步，外部连接端子(耳机端子、USB端子、可连接到AC适配器或诸如USB电缆之类的各种电缆的端子等)、记录介质插入部分等可设置在外壳的背面或侧表面上。电子书320还可用作电子词典。FIG. 23C shows an example in which the casing 321 is provided with an operation section and the like. For example, the casing 321 is provided with a power switch 331, operation keys 333, a speaker 335, and the like. The operation keys 333 allow page turning. Note that a keyboard, a pointing device, etc. may be provided on the same side of the housing as the display portion. Further, an external connection terminal (earphone terminal, USB terminal, terminal connectable to an AC adapter or various cables such as a USB cable, etc.), a recording medium insertion portion, etc. may be provided on the rear or side surface of the case. The electronic book 320 can also be used as an electronic dictionary.

此外，电子书320可无线地发送并接收信息。通过无线通信，可从电子书服务器购买和下载想要的图书数据等。In addition, e-book 320 can transmit and receive information wirelessly. Through wireless communication, desired book data and the like can be purchased and downloaded from an electronic book server.

注意，电子纸可被用于所有领域的电子设备，只要它们显示数据。例如，为了显示数据，除了电子书外，可将电子纸应用于海报、诸如火车等车辆中的广告、诸如信用卡之类的多种卡、等。通过将根据所公开的发明的半导体器件应用到上述电子书，可提供高性能的电子书。Note that electronic paper can be used for electronic devices in all fields as long as they display data. For example, in order to display data, electronic paper can be applied to posters, advertisements in vehicles such as trains, various cards such as credit cards, etc. in addition to electronic books. By applying the semiconductor device according to the disclosed invention to the above-mentioned electronic book, a high-performance electronic book can be provided.

图23D示出包括根据上述实施例中的任意的半导体器件的蜂窝电话。该蜂窝电话包括两个外壳——外壳340和外壳341。外壳341包括显示面板342、扬声器343、话筒344、指向设备346、摄像机透镜347、外部连接端子348等。外壳340包括用于对该蜂窝电话充电的太阳能电池349、外部存储槽350等。天线被结合到外壳341中。根据所公开的发明的半导体器件被集成、安装在电路板等之上，且被结合至外壳340或外壳341中。FIG. 23D shows a cellular phone including the semiconductor device according to any of the above-described embodiments. The cellular phone includes two housings - housing 340 and housing 341 . The housing 341 includes a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, and the like. The housing 340 includes a solar cell 349 for charging the cellular phone, an external storage slot 350, and the like. An antenna is incorporated into the housing 341 . The semiconductor device according to the disclosed invention is integrated, mounted on a circuit board or the like, and incorporated into the case 340 or the case 341 .

显示面板342具有触摸面板功能。显示为图像的多个操作键345在图23D中用虚线示出。根据所公开的发明的半导体器件可被应用于显示面板342。通过将根据所公开的发明的半导体器件应用到显示面板342，可显示高质量图像。注意，该蜂窝电话包括用于将从太阳能电池349输出的电压增加到每一个电路所需的电压的升压电路。除了上述结构外，蜂窝电话可能具有其中形成非接触式IC芯片、小型记录设备等的结构。The display panel 342 has a touch panel function. A plurality of operation keys 345 displayed as images are shown by dotted lines in FIG. 23D. A semiconductor device according to the disclosed invention may be applied to the display panel 342 . By applying the semiconductor device according to the disclosed invention to the display panel 342, high-quality images can be displayed. Note that this cellular phone includes a booster circuit for increasing the voltage output from the solar cell 349 to a voltage required by each circuit. In addition to the above-mentioned structure, a cellular phone may have a structure in which a non-contact IC chip, a small recording device, and the like are formed.

显示面板342根据应用模式而适当地变化显示的取向。此外，相机镜头347设置在与显示面板342相同的一侧上，从而该蜂窝电话可被用作视频电话。可将扬声器343和话筒344用作语音呼叫，以及视频呼叫、录音、播放声音等。此外，可滑动处于发展为图23D所示的状态中的外壳340和341，以使一个重叠在另一个上。因此，可减小蜂窝电话的尺寸，这使得蜂窝电话适于携带。The display panel 342 appropriately changes the orientation of the display according to the application mode. In addition, the camera lens 347 is disposed on the same side as the display panel 342, so that the cellular phone can be used as a video phone. The speaker 343 and the microphone 344 can be used for voice calls, as well as video calls, recording, playing sound, and the like. Furthermore, the casings 340 and 341 in the state developed as shown in FIG. 23D can be slid so as to overlap one on the other. Therefore, the size of the cellular phone can be reduced, which makes the cellular phone suitable for portability.

外部连接端子348可连接到AC适配器或诸如USB电缆之类的各种电缆，从而可对蜂窝电话充电、或者该蜂窝电话可进行数据通信。此外，蜂窝电话可通过将记录介质插入外部存储槽350来存储和转移更大量的数据。此外，除了上述功能外，可提供红外通信功能、电视接收功能等。通过将根据所公开的发明的半导体器件应用到蜂窝电话，可提供高性能的蜂窝电话。The external connection terminal 348 can be connected to an AC adapter or various cables such as a USB cable so that the cellular phone can be charged, or the cellular phone can perform data communication. In addition, the cellular phone can store and transfer a larger amount of data by inserting a recording medium into the external storage slot 350 . Furthermore, in addition to the above functions, an infrared communication function, a television reception function, and the like may be provided. By applying the semiconductor device according to the disclosed invention to a cellular phone, a high-performance cellular phone can be provided.

图23E示出包括根据上述实施例中的任意的半导体器件的数码相机。数字照相机包括主体361，显示部分A367、目镜363、操作开关364、显示部分B365、电池366等。根据本发明的半导体器件可被应用于显示部分A367或显示部分B365。通过将根据所公开的发明的半导体器件应用到显示部分A367或显示部分B365，可显示高质量图像。通过将根据所公开的发明的半导体器件应用到上述数码相机，可提供高性能的数码相机。FIG. 23E shows a digital camera including the semiconductor device according to any of the above-described embodiments. The digital camera includes a main body 361, a display portion A367, an eyepiece 363, operation switches 364, a display portion B365, a battery 366, and the like. The semiconductor device according to the present invention can be applied to the display portion A367 or the display portion B365. By applying the semiconductor device according to the disclosed invention to the display portion A367 or the display portion B365, high-quality images can be displayed. By applying the semiconductor device according to the disclosed invention to the above-mentioned digital camera, a high-performance digital camera can be provided.

图23F示出包括根据上述实施例中的任意的半导体器件的电视机。在电视机370中，显示部分373结合在外壳371中。可在显示部分373上显示图像。这里，外壳371由支架375支承。通过将根据所公开的发明的半导体器件应用于显示部分373，可实现开关元件的高速操作且可实现显示部分373的面积的增加。FIG. 23F shows a television including the semiconductor device according to any of the above-described embodiments. In the television 370 , a display portion 373 is incorporated in a casing 371 . Images can be displayed on the display portion 373 . Here, the case 371 is supported by a bracket 375 . By applying the semiconductor device according to the disclosed invention to the display portion 373, high-speed operation of the switching element can be realized and an increase in the area of the display portion 373 can be realized.

可由包括在外壳371中的操作开关或遥控器380操作电视机370。可通过遥控器380中所包括的控制键379来控制频道和音量，并且由此可控制显示部分373上所显示的图像。此外，遥控器380可设置有用于显示从遥控器380输出的数据的显示部分377。The television 370 can be operated by an operation switch included in the housing 371 or a remote controller 380 . The channel and the volume can be controlled through the control key 379 included in the remote controller 380, and thus the image displayed on the display part 373 can be controlled. In addition, the remote controller 380 may be provided with a display part 377 for displaying data output from the remote controller 380 .

注意，电视机370优选包括接收器、调制解调器等。接收器允许电视机370接收一般的电视广播。此外，当电视机370通过经由调制解调器的有线或无线连接被连接至通信网络时，能单向(从发射器到接收器)或双向(发射器与接收器之间、接收器之间等)数据通信。通过将根据所公开的发明的半导体器件应用到上述电视机，可提供高性能的电视机。Note that the television set 370 preferably includes a receiver, a modem, and the like. The receiver allows the television 370 to receive general television broadcasts. In addition, when the television 370 is connected to a communication network through a wired or wireless connection via a modem, data can be unidirectional (from transmitter to receiver) or bidirectional (between transmitter and receiver, between receivers, etc.) communication. By applying the semiconductor device according to the disclosed invention to the above-mentioned television, a high-performance television can be provided.

本实施例中描述的结构、方法等可与其他实施例中描述的任一结构、方法等适当地组合。The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

本申请基于2009年12月4日向日本特许厅提交的日本专利申请系列号2009-276334，该申请的全部内容通过引用结合于此。This application is based on Japanese Patent Application Serial No. 2009-276334 filed with the Japan Patent Office on December 4, 2009, the entire contents of which are hereby incorporated by reference.

Claims (21)

Translated fromChinese

1.一种半导体器件，包括：1. A semiconductor device, comprising:在绝缘表面上的包括结晶区的氧化物半导体层；an oxide semiconductor layer including a crystalline region on an insulating surface;与所述氧化物半导体层电接触的源电极层和漏电极层；a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer;覆盖所述氧化物半导体层的栅绝缘层；以及a gate insulating layer covering the oxide semiconductor layer; and位于所述栅绝缘层上的栅电极层，a gate electrode layer on the gate insulating layer,其中所述栅电极层与所述结晶区交叠，wherein the gate electrode layer overlaps the crystalline region,其中所述氧化物半导体层的氢浓度为5x10¹⁹/cm³或更小，wherein the hydrogen concentration of the oxide semiconductor layer is 5×^{10 19} /cm³ or less,其中所述结晶区包括其c-轴与垂直于所述氧化物半导体层的表面的方向对齐的晶体，以及wherein the crystalline region includes a crystal whose c-axis is aligned with a direction perpendicular to the surface of the oxide semiconductor layer, and其中所述晶体具有层叠包括铟的层与包括镓或锌的层的结构。Wherein the crystal has a structure in which a layer including indium and a layer including gallium or zinc are stacked.2.如权利要求1所述的半导体器件，其特征在于，在与所述栅电极层交迭的区域中，所述氧化物半导体层的表面的高度差为1nm或更少。2. The semiconductor device according to claim 1, wherein, in a region overlapping with the gate electrode layer, a difference in height of the surface of the oxide semiconductor layer is 1 nm or less.3.如权利要求1所述的半导体器件，其特征在于，所述栅绝缘层覆盖所述源电极层和所述漏电极层。3. The semiconductor device according to claim 1, wherein the gate insulating layer covers the source electrode layer and the drain electrode layer.4.一种半导体器件，包括：4. A semiconductor device, comprising:在绝缘表面之上的第一栅电极层；a first gate electrode layer over the insulating surface;覆盖所述第一栅电极层的第一栅绝缘层；a first gate insulating layer covering the first gate electrode layer;在所述第一栅绝缘层上的包括结晶区的氧化物半导体层；an oxide semiconductor layer including a crystalline region on the first gate insulating layer;与所述氧化物半导体层电接触的源电极层和漏电极层；a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer;覆盖所述氧化物半导体层的第二栅绝缘层；以及a second gate insulating layer covering the oxide semiconductor layer; and位于所述第二栅绝缘层上的第二栅电极层，a second gate electrode layer on the second gate insulating layer,其中所述第二栅电极层与所述结晶区交叠，wherein the second gate electrode layer overlaps the crystalline region,其中所述氧化物半导体层的氢浓度为5x10¹⁹/cm³或更小，wherein the hydrogen concentration of the oxide semiconductor layer is 5×^{10 19} /cm³ or less,其中所述结晶区包括其c-轴与垂直于所述氧化物半导体层的表面的方向对齐的晶体，wherein the crystalline region includes crystals whose c-axis is aligned with a direction perpendicular to the surface of the oxide semiconductor layer,其中所述晶体具有层叠包括铟的层与包括镓或锌的层的结构。Wherein the crystal has a structure in which a layer including indium and a layer including gallium or zinc are stacked.5.如权利要求4所述的半导体器件，其特征在于，所述第二栅绝缘层覆盖所述源电极层和所述漏电极层。5. The semiconductor device according to claim 4, wherein the second gate insulating layer covers the source electrode layer and the drain electrode layer.6.如权利要求1或4所述的半导体器件，其特征在于，所述氧化物半导体层包括凹入部分。6. The semiconductor device according to claim 1 or 4, wherein the oxide semiconductor layer includes a concave portion.7.如权利要求1或4所述的半导体器件，其特征在于，还包括，分别位于所述源电极层和所述漏电极层上的，具有与所述源电极层和所述漏电极层一样的形状的绝缘层。7. The semiconductor device according to claim 1 or 4, further comprising, on the source electrode layer and the drain electrode layer respectively, a Insulation layer of the same shape.8.如权利要求1或4所述的半导体器件，其特征在于，所述源电极层和所述漏电极层的与所述氧化物半导体层接触的部分包括选自氮化钛、氮化钨和铂中的材料。8. The semiconductor device according to claim 1 or 4, wherein the portion of the source electrode layer and the drain electrode layer that is in contact with the oxide semiconductor layer comprises a compound selected from titanium nitride, tungsten nitride and materials in platinum.9.如权利要求1或4所述的半导体器件，其特征在于，在所述氧化物半导体层中所述结晶区以外的区域具有非晶结构。9. The semiconductor device according to claim 1 or 4, wherein a region other than the crystalline region in the oxide semiconductor layer has an amorphous structure.10.如权利要求1或4所述的半导体器件，其特征在于，所述半导体器件是选自以下组中的一个：个人计算机、个人数字助理、电子书、蜂窝电话、数字照相机、和电视机。10. The semiconductor device according to claim 1 or 4, wherein the semiconductor device is one selected from the group consisting of a personal computer, a personal digital assistant, an electronic book, a cellular phone, a digital camera, and a television .11.如权利要求1或4所述的半导体器件，其特征在于，当漏电压为+1V或+10V且栅电压被设置为从-5V到-20V时，所述半导体器件的截止态电流为1x10^-13A或更小。11. The semiconductor device according to claim 1 or 4, wherein when the drain voltage is +1V or +10V and the gate voltage is set from -5V to -20V, the off-state current of the semiconductor device is 1x10^-13 A or less.12.一种半导体器件的制造方法，包括：12. A method of manufacturing a semiconductor device, comprising:在绝缘表面上形成氧化物半导体层；forming an oxide semiconductor layer on the insulating surface;在所述氧化物半导体层上形成导电层；forming a conductive layer on the oxide semiconductor layer;通过蚀刻所述导电层而形成源电极层和漏电极层；forming a source electrode layer and a drain electrode layer by etching the conductive layer;通过执行热处理在所述氧化物半导体层中形成结晶区，从而所述结晶区的c-轴对齐于垂直于所述氧化物半导体层的表面的方向；forming a crystallized region in the oxide semiconductor layer by performing heat treatment such that a c-axis of the crystallized region is aligned with a direction perpendicular to a surface of the oxide semiconductor layer;形成栅绝缘层来覆盖所述氧化物半导体层；以及forming a gate insulating layer to cover the oxide semiconductor layer; and在所述栅绝缘层上与结晶区相交迭的区域中形成栅电极层，forming a gate electrode layer in a region overlapping the crystalline region on the gate insulating layer,其中所述氧化物半导体层的氢浓度为5x10¹⁹/cm³或更小，以及wherein the hydrogen concentration of the oxide semiconductor layer is 5×^{10 19} /cm³ or less, and其中所述结晶区包含晶体，该晶体具有层叠包括铟的层与包括镓或锌的层的结构。Wherein the crystalline region includes a crystal having a structure in which a layer including indium and a layer including gallium or zinc are stacked.13.如权利要求12所述的半导体器件的制造方法，其特征在于，所述栅绝缘层覆盖所述源电极层和所述漏电极层。13. The method for manufacturing a semiconductor device according to claim 12, wherein the gate insulating layer covers the source electrode layer and the drain electrode layer.14.一种半导体器件的制造方法，包括：14. A method of manufacturing a semiconductor device, comprising:在绝缘表面上形成第一栅电极层；forming a first gate electrode layer on the insulating surface;形成第一栅绝缘层从而覆盖该第一栅电极层；forming a first gate insulating layer so as to cover the first gate electrode layer;在所述第一栅绝缘层上形成氧化物半导体层；forming an oxide semiconductor layer on the first gate insulating layer;在所述氧化物半导体层上形成导电层；forming a conductive layer on the oxide semiconductor layer;通过蚀刻所述导电层而形成源电极层和漏电极层；forming a source electrode layer and a drain electrode layer by etching the conductive layer;通过执行热处理在所述氧化物半导体层中形成结晶区，从而所述结晶区的c-轴对齐于垂直于所述氧化物半导体层的表面的方向；forming a crystallized region in the oxide semiconductor layer by performing heat treatment such that a c-axis of the crystallized region is aligned with a direction perpendicular to a surface of the oxide semiconductor layer;形成第二栅绝缘层来覆盖所述氧化物半导体层；以及forming a second gate insulating layer to cover the oxide semiconductor layer; and在所述第二栅绝缘层上与所述结晶区相交迭的区域中形成第二栅电极层，forming a second gate electrode layer in a region overlapping the crystalline region on the second gate insulating layer,其中所述氧化物半导体层的氢浓度为5x10¹⁹/cm³或更小，以及wherein the hydrogen concentration of the oxide semiconductor layer is 5×^{10 19} /cm³ or less, and其中所述结晶区包含晶体，该晶体具有层叠包括铟的层与包括镓或锌的层的结构。Wherein the crystalline region includes a crystal having a structure in which a layer including indium and a layer including gallium or zinc are stacked.15.如权利要求14所述的半导体器件的制造方法，其特征在于，所述第二栅绝缘层覆盖所述源电极层和所述漏电极层。15. The method for manufacturing a semiconductor device according to claim 14, wherein the second gate insulating layer covers the source electrode layer and the drain electrode layer.16.如权利要求12或14所述的半导体器件的制造方法，其特征在于，在高于或等于550℃且低于或等于850℃的温度下执行所述热处理。16. The method of manufacturing a semiconductor device according to claim 12 or 14, wherein the heat treatment is performed at a temperature higher than or equal to 550°C and lower than or equal to 850°C.17.如权利要求12或14所述的半导体器件的制造方法，其特征在于，当所述导电层被蚀刻时，所述氧化物半导体层的一部分被移除。17. The method of manufacturing a semiconductor device according to claim 12 or 14, wherein when the conductive layer is etched, a part of the oxide semiconductor layer is removed.18.如权利要求12或14所述的半导体器件的制造方法，其特征在于，还包括，分别在所述源电极层和所述漏电极层上，形成具有与所述源电极层和所述漏电极层一样的形状的绝缘层的步骤。18. The manufacturing method of a semiconductor device according to claim 12 or 14, further comprising: forming a layer having a structure corresponding to the source electrode layer and the drain electrode layer on the source electrode layer and the drain electrode layer respectively. Insulation layer steps in the same shape as the drain electrode layer.19.如权利要求12或14所述的半导体器件的制造方法，其特征在于，所述源电极层和所述漏电极层的与所述氧化物半导体层接触的部分使用选自氮化钛、氮化钨和铂中的材料形成。19. The method for manufacturing a semiconductor device according to claim 12 or 14, wherein the parts of the source electrode layer and the drain electrode layer that are in contact with the oxide semiconductor layer are made of titanium nitride, Materials formed in tungsten nitride and platinum.20.如权利要求12或14所述的半导体器件的制造方法，其特征在于，形成具有非晶结构的氧化物半导体层作为所述氧化物半导体层，且所述非晶结构保留在所述结晶区以外的区域。20. The method for manufacturing a semiconductor device according to claim 12 or 14, wherein an oxide semiconductor layer having an amorphous structure is formed as the oxide semiconductor layer, and the amorphous structure remains in the crystal areas outside the area.21.如权利要求12或14所述的半导体器件的制造方法，其特征在于，当漏电压为+1V或+10V且栅电压被设置为从-5V到-20V时，所述半导体器件的截止态电流为1x10^-13A或更小。21. The manufacturing method of a semiconductor device as claimed in claim 12 or 14, wherein when the drain voltage is +1V or +10V and the gate voltage is set from -5V to -20V, the cut-off of the semiconductor device The state current is 1x10^-13 A or less.