CN102637602A - Method for reducing grid-induction drain leakage of semiconductor device - Google Patents

Abstract

The invention discloses a method for reducing grid-induction drain leakage of a semiconductor device. The method includes steps: growing a side-wall film on a substrate with completed two-side shallow trench isolation; etching the side-wall film, guiding etching plasma to advance towards an incident point of a source electrode, forming a certain angle between the etching plasma and the vertical direction, forming a side wall on a grid electrode of the semiconductor device, reducing the width of the etched side-wall source electrode, and widening a drain electrode; and realizing heavy doping for the source electrode and the drain electrode and an annealing process. By the aid of the method, the intensity of a longitudinal electric field on a leaked end is reduced under the condition of keeping the effective lengths of trenches unchanged, and accordingly grid-caused leakage current of the drain electrode of the semiconductor device is reduced.

Description

Translated fromChinese

一种减小半导体器件栅诱导漏极泄漏的方法A Method for Reducing Gate-Induced Drain Leakage of Semiconductor Devices

技术领域technical field

本发明涉及半导体制备技术领域，尤其涉及一种减小半导体器件栅诱导漏极泄漏的方法。The invention relates to the technical field of semiconductor preparation, in particular to a method for reducing gate-induced drain leakage of semiconductor devices.

背景技术Background technique

栅致漏极泄漏（GIDL，Gate-Induced Drain Leakage）是指，当器件在关断（off-state）的情况下（即Vg=0），若漏极与Vdd相连（即Vd=Vdd），由于栅极和漏极之间的交叠，在栅极和漏极之间的交叠区域会存在强电场，载流子会在强电场作用下发生带带隧穿效应（Band-to-band Tunneling），从而引起漏极到栅极之间的漏电流。Gate-Induced Drain Leakage (GIDL, Gate-Induced Drain Leakage) means that when the device is off-state (ie Vg=0), if the drain is connected to Vdd (ie Vd=Vdd), Due to the overlap between the gate and the drain, there will be a strong electric field in the overlapping region between the gate and the drain, and the carriers will undergo band-to-band tunneling under the action of the strong electric field. Tunneling), causing leakage current from drain to gate.

栅致漏极泄漏电流已经成为影响小尺寸MOS器件可靠性、功耗等方面的主要原因之一，它同时也对EEPROM等存储器件的擦写操作有重要影响。当工艺进入超深亚微米时代后，由于器件尺寸日益缩小，GIDL电流引发的众多可靠性问题变得愈加严重。The gate-induced-drain leakage current has become one of the main reasons affecting the reliability and power consumption of small-sized MOS devices, and it also has an important impact on the erasing and writing operations of memory devices such as EEPROM. When the process enters the ultra-deep submicron era, due to the shrinking device size, many reliability problems caused by GIDL current become more and more serious.

中国专利CN 101350301A公开了一种半导体器件及其制造方法，该制造方法可以包括：在半导体衬底上选择性地形成氧化层图样，在相同的衬底上形成绝缘层图样以覆盖该氧化层图样的边缘部分，蚀刻该氧化层图样和该衬底以形成凹槽和相应于该氧化层图样边缘部分的第一和第二氧化层图样，在凹槽中的衬底上形成第三氧化层图样以产生包括第一、第二和第三氧化层图样的栅极绝缘层，以及在该凹槽中形成栅极图样。该方法工艺较为复杂。Chinese patent CN 101350301A discloses a semiconductor device and its manufacturing method, which may include: selectively forming an oxide layer pattern on a semiconductor substrate, and forming an insulating layer pattern on the same substrate to cover the oxide layer pattern The edge portion of the oxide layer pattern and the substrate are etched to form a groove and the first and second oxide layer patterns corresponding to the edge portion of the oxide layer pattern, and a third oxide layer pattern is formed on the substrate in the groove to generate a gate insulating layer including the first, second and third oxide layer patterns, and form a gate pattern in the groove. The process of this method is relatively complicated.

通常工艺中，侧墙刻蚀工艺如图1A~1C所示，首先是在具有栅极3的衬底0表面进行侧墙薄膜1沉积，沉积后器件的截面如图1A所示；接下来采用各向异性的干法刻蚀，刻蚀后源漏极上方的侧墙2成对称结构，如图1B所示；然后是源漏重掺杂以及退火工艺，源漏形成的掺杂离子分布如图1C所示，掺杂离子距离器件沟道的距离，由侧墙2的宽度所决定。In the usual process, the sidewall etching process is shown in Figures 1A to 1C. First, thesidewall film 1 is deposited on the surface of thesubstrate 0 with thegate 3, and the cross section of the device after deposition is shown in Figure 1A; Anisotropic dry etching, after etching, thesidewall 2 above the source and drain forms a symmetrical structure, as shown in Figure 1B; then the source and drain are heavily doped and annealed, and the dopant ion distribution formed by the source and drain is as follows As shown in FIG. 1C , the distance between the dopant ions and the channel of the device is determined by the width of thespacer 2 .

发明内容Contents of the invention

针对上述存在的问题，本发明的目的是提供一种减小半导体器件栅诱导漏极泄漏的方法，在保持沟道有效长度（Effective Channel Length）不变的情况下，降低了漏端的纵向电场强度，从而减小了半导体器件栅致漏极泄漏电流，工艺简单。In view of the above existing problems, the object of the present invention is to provide a method for reducing gate-induced drain leakage of semiconductor devices, which reduces the vertical electric field intensity at the drain end while keeping the effective channel length (Effective Channel Length) constant. , thereby reducing the gate-induced-drain leakage current of the semiconductor device, and the process is simple.

本发明的目的是通过下述技术方案实现的：The purpose of the present invention is achieved through the following technical solutions:

一种减小半导体器件栅诱导漏极泄漏的方法，其中，包括下列步骤：A method for reducing gate-induced drain leakage of a semiconductor device, comprising the following steps:

在一已完成两侧浅沟槽隔离工艺的衬底上生长一层侧墙薄膜；growing a layer of sidewall film on a substrate that has completed the shallow trench isolation process on both sides;

对侧墙薄膜进行刻蚀，引入的刻蚀等离子体从朝向于源极的入射点进行并与竖直方向形成一定角度，在半导体器件的栅极上形成侧墙，并使得刻蚀后的侧墙源极的宽度减小，漏极的宽度增大；Etching the side wall film, the introduced etching plasma is carried out from the incident point towards the source and forms a certain angle with the vertical direction, forming a side wall on the gate of the semiconductor device, and making the etched side wall The width of the wall source decreases and the width of the drain increases;

进行源漏重掺杂以及退火工艺。Perform source and drain heavy doping and annealing processes.

在本发明的又一个实施例中，在45nm CMOS器件工艺中，引入的刻蚀等离子体入射方向与竖直方向成15度。In yet another embodiment of the present invention, in the 45nm CMOS device process, the incident direction of the introduced etching plasma is 15 degrees from the vertical direction.

在本发明的另一个实施例中，在衬底源极与栅极的交界处、以及漏极与栅极的交界处分别具有低掺杂源漏区。In another embodiment of the present invention, there are low-doped source and drain regions at the junction of the source and the gate of the substrate, and at the junction of the drain and the gate, respectively.

在本发明的又一个实施例中，所述侧墙薄膜为氧化硅或者氮化硅薄膜。In yet another embodiment of the present invention, the sidewall film is a silicon oxide or silicon nitride film.

在本发明的另一个实施例中，对侧墙薄膜进行的刻蚀是采用干法刻蚀。In another embodiment of the present invention, the etching of the sidewall film is performed by dry etching.

与已有技术相比，本发明的有益效果在于：Compared with prior art, the beneficial effect of the present invention is:

1、不增加现有的MOS器件制造工艺步骤。1. The existing MOS device manufacturing process steps are not added.

2、通过斜角侧墙刻蚀工艺，增加了刻蚀后漏端的侧墙宽度，减小了刻蚀后源端得侧墙宽度。2. Through the bevel sidewall etching process, the sidewall width of the drain end after etching is increased, and the sidewall width of the source end after etching is reduced.

3、在漏端，由于重掺杂离子与沟道间的距离被拉远，当栅极关断而漏极接Vdd时，在栅极与漏端交叠区域的电场强度减弱，从而降低了载流子的带带隧穿效应，减小了半导体器件栅致漏极泄漏电流。3. At the drain end, since the distance between the heavily doped ions and the channel is pulled away, when the gate is turned off and the drain is connected to Vdd, the electric field strength in the overlapping area of the gate and drain ends is weakened, thereby reducing the The band-band tunneling effect of carriers reduces the gate-induced-drain leakage current of semiconductor devices.

4、在漏端的掺杂离子与沟道的距离被拉远的同时，源端的掺杂离子与沟道的距离被拉近，因此器件的有效沟道长度基本保持不变，器件的其他性能得以保持。4. While the distance between the dopant ions at the drain end and the channel is shortened, the distance between the dopant ions at the source end and the channel is shortened, so the effective channel length of the device remains basically unchanged, and other performances of the device can be improved. Keep.

附图说明Description of drawings

图1A、图1B和图1C是传统工艺的侧墙刻蚀工艺步骤示意图；FIG. 1A, FIG. 1B and FIG. 1C are schematic diagrams of sidewall etching process steps in a conventional process;

图2是本发明减小半导体器件栅诱导漏极泄露的方法的流程示意图；2 is a schematic flow chart of a method for reducing gate-induced drain leakage of a semiconductor device according to the present invention;

图3A、图3B和图3C是本发明减小半导体器件栅诱导漏极泄漏的方法步骤示意图。Fig. 3A, Fig. 3B and Fig. 3C are schematic diagrams of the steps of the method for reducing gate-induced drain leakage of a semiconductor device according to the present invention.

具体实施方式Detailed ways

下面结合原理图和具体操作实施例对本发明作进一步说明。The present invention will be further described below in combination with principle diagrams and specific operation examples.

参看图2所示，本发明减小半导体器件栅诱导漏极泄漏的方法具体包括下列步骤：Referring to Figure 2, the method for reducing the gate-induced drain leakage of a semiconductor device in the present invention specifically includes the following steps:

如图3A所示，在一已完成两侧浅沟槽隔离工艺（STI）4的衬底0上生长一层侧墙薄膜1，侧墙薄膜1可以为氧化硅或者氮化硅薄膜，在衬底源极与栅极的交界处、以及漏极与栅极的交界处分别具有低掺杂源漏区（LDD）8。对侧墙薄膜1进行干法刻蚀，具体地，对侧墙薄膜1进行的是采用具有各向异性的等离子体干法刻蚀，引入的刻蚀等离子体5从朝向于源极7的入射点进行并与竖直方向形成一定角度α，在半导体器件的栅极3上形成侧墙2，并使得刻蚀后的侧墙2源极的宽度减小，漏极的宽度增大，完成后的效果图如图3B所示。在本发明的一个具体实施例中，在45nm CMOS器件工艺中，引入的刻蚀等离子体5入射方向与竖直方向成15度。As shown in FIG. 3A, a layer ofsidewall film 1 is grown on asubstrate 0 that has completed shallow trench isolation (STI) 4 on both sides. Thesidewall film 1 can be a silicon oxide or silicon nitride film. The junctions between the bottom source and the gate, and the junctions between the drain and the gate respectively have a low-doped source-drain region (LDD) 8 . Thesidewall film 1 is dry-etched, specifically, thesidewall film 1 is dry-etched using anisotropic plasma, and the introducedetching plasma 5 is incident on thesource electrode 7. point and form a certain angle α with the vertical direction to form aspacer 2 on thegate 3 of the semiconductor device, and reduce the width of the source of theetched spacer 2 and increase the width of the drain. After completion The effect diagram is shown in Figure 3B. In a specific embodiment of the present invention, in the 45nm CMOS device process, the incident direction of the introducedetching plasma 5 is 15 degrees from the vertical direction.

刻蚀后的侧墙源极6的宽度减小，漏极7的宽度增大，最后进行源漏重掺杂以及退火工艺，最终完成后的半导体截面图如图3C所示。由于掺杂离子与器件沟道的距离由侧墙2的宽度所决定，因此掺杂后，源端的掺杂离子与器件沟道的距离被拉近，漏极7的掺杂离子与器件沟道的距离被拉远，但由于源漏侧墙的宽度之和保持不变，所以源漏重掺杂离子之间的距离保持不变。After etching, the width of thesidewall source 6 is reduced, and the width of thedrain 7 is increased. Finally, source and drain heavy doping and annealing process are performed. The final cross-sectional view of the semiconductor is shown in FIG. 3C . Since the distance between the dopant ions and the device channel is determined by the width of thesidewall 2, after doping, the distance between the dopant ions at the source end and the device channel is shortened, and the dopant ions at thedrain 7 are closer to the device channel. The distance is pulled away, but since the sum of the widths of the source and drain sidewalls remains unchanged, the distance between the source and drain heavily doped ions remains unchanged.

在漏极7，由于重掺杂离子与沟道间的距离被拉远，当栅极3关断而漏极7接Vdd时，在栅极3与漏极7交叠区域的电场强度减弱，从而降低了载流子的带带隧穿效应，减小了半导体器件栅致漏极泄漏电流。此外，由于在漏极7的重掺杂离子与沟道的距离被拉远的同时，源极6的重掺杂离子与沟道的距离被拉近，总的源漏重掺杂离子之间的距离保持不变，因此器件的有效沟道长度基本保持不变，器件的其他性能得以保持，工艺简单。At thedrain 7, since the distance between the heavily doped ions and the channel is pulled away, when thegate 3 is turned off and thedrain 7 is connected to Vdd, the electric field strength in the overlapping region of thegate 3 and thedrain 7 is weakened, Therefore, the band-band tunneling effect of the carriers is reduced, and the gate-induced-drain leakage current of the semiconductor device is reduced. In addition, since the distance between the heavily doped ions of thedrain 7 and the channel is pulled away, the distance between the heavily doped ions of thesource 6 and the channel is shortened, and the total source-drain heavily doped ions The distance remains unchanged, so the effective channel length of the device remains basically unchanged, other properties of the device are maintained, and the process is simple.

以上对本发明的具体实施例进行了详细描述，但本发明并不限制于以上描述的具体实施例，其只是作为范例。对于本领域技术人员而言，任何等同修改和替代也都在本发明的范畴之中。因此，在不脱离本发明的精神和范围下所作出的均等变换和修改，都应涵盖在本发明的范围内。The specific embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments described above, which are only examples. For those skilled in the art, any equivalent modifications and substitutions also fall within the scope of the present invention. Therefore, all equivalent changes and modifications made without departing from the spirit and scope of the present invention shall fall within the scope of the present invention.

Claims (5)

1. one kind reduces the method that semiconductor device gate is induced drain leakage, it is characterized in that, comprises the following steps:

Accomplished growth one deck side wall film on the substrate of both sides shallow ditch groove separation process one;

The side wall film is carried out etching; The etching plasma of introducing carries out and forms certain angle with vertical direction from the incidence point toward source electrode; On the grid of semiconductor device, form side wall, and make the width of the side wall source electrode after the etching reduce, the width of drain electrode increases;

Carry out the source and leak heavy doping and annealing process.

2. the semiconductor device gate that reduces as claimed in claim 1 is induced the method that drains and reveal, and it is characterized in that, in 45nm cmos device technology, the etching plasma incident direction of introducing becomes 15 degree with vertical direction.

3. the semiconductor device gate that reduces as claimed in claim 1 is induced the method that drains and reveal, and it is characterized in that having the low doping source drain region respectively at the intersection of substrate source electrode and grid and the intersection of drain electrode and grid.

4. induce the method that drains and reveal like any described semiconductor device gate that reduces in the claim 1 to 3, it is characterized in that said side wall film is silica or silicon nitride film.

5. induce the method that drains and reveal like any described semiconductor device gate that reduces in the claim 1 to 3, it is characterized in that the etching that the side wall film is carried out is to adopt dry etching.

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