技术领域technical field
本发明涉及显示技术领域，具体地，涉及一种阵列基板及其制造方法和显示装置。The present invention relates to the field of display technology, in particular, to an array substrate, a manufacturing method thereof, and a display device.
背景技术Background technique
在薄膜晶体管液晶显示器(Thin Film Transistor Liquid CrystalDisplay，TFT-LCD)的生产领域，液晶面板的开口率是一个重要的产品指标。液晶面板中的数据线、扫描线和薄膜晶体管，通常采用设置在彩膜层中的黑矩阵遮挡，黑矩阵区域不能透光，液晶面板的开口率是指光线通过的那一部分的面积与液晶面板整体的面积之间的比值，开口率越高，光线通过的效率越高，同时，液晶面板的高开口率对于提高液晶面板的清晰度、亮度以及节省能源等方面都具有重要意义。In the production field of Thin Film Transistor Liquid Crystal Display (TFT-LCD), the aperture ratio of the liquid crystal panel is an important product index. The data lines, scanning lines and thin film transistors in the liquid crystal panel are usually blocked by the black matrix arranged in the color filter layer. The black matrix area cannot transmit light. The aperture ratio of the liquid crystal panel refers to the area of the part through which the light passes and the area of the liquid crystal panel. The ratio between the overall areas, the higher the aperture ratio, the higher the efficiency of light passing through. At the same time, the high aperture ratio of the LCD panel is of great significance for improving the clarity, brightness and energy saving of the LCD panel.
现有技术中，液晶面板通常包括阵列基板、彩膜基板和液晶层，液晶层对盒封装在阵列基板和彩膜基板之间。其中，彩膜基板上包括透明基板黑矩阵、彩膜层和公共电极，阵列基板依次包括基板、扫描线、数据线、薄膜晶体管和像素电极。将阵列基板和彩膜基板对盒封装之后，彩膜基板上的黑矩阵与阵列基板上的薄膜晶体管、扫描线和数据线对应设置，以遮挡从阵列基板上的薄膜晶体管、扫描线和数据线位置处的漏光。然而，由于实际生产中的设备精度和工艺条件的限制，彩膜基板上的黑矩阵与阵列基板上的薄膜晶体管、扫描线、数据线很难精确对应，或者在使用液晶面板的时候，外力的冲击也可能造成彩膜基板上的黑矩阵与阵列基板上的薄膜晶体管、扫描线、数据线之间的偏离，都可能导致漏光；现有技术中，可以通过增大黑矩阵的面积来避免阵列基板上的薄膜晶体管、扫描线、数据线位置处的漏光产生的缺陷，但是，增大黑矩阵的面积将导致液晶面板的开口率减小，液晶面板的显示亮度低。In the prior art, a liquid crystal panel usually includes an array substrate, a color filter substrate and a liquid crystal layer, and the liquid crystal layer is packaged between the array substrate and the color filter substrate. Wherein, the color filter substrate includes a transparent substrate black matrix, a color filter layer and a common electrode, and the array substrate sequentially includes a substrate, scanning lines, data lines, thin film transistors and pixel electrodes. After the array substrate and the color filter substrate are packaged in a box, the black matrix on the color filter substrate is arranged corresponding to the thin film transistors, scanning lines and data lines on the array substrate, so as to shield the thin film transistors, scanning lines and data lines on the array substrate. Light leaks at the location. However, due to the limitations of equipment precision and process conditions in actual production, it is difficult to accurately correspond between the black matrix on the color filter substrate and the thin film transistors, scanning lines, and data lines on the array substrate, or when using a liquid crystal panel, the external force The impact may also cause the deviation between the black matrix on the color filter substrate and the thin film transistors, scanning lines, and data lines on the array substrate, which may cause light leakage; in the prior art, the area of the black matrix can be increased to avoid array Defects caused by light leakage at the positions of thin film transistors, scan lines, and data lines on the substrate, however, increasing the area of the black matrix will result in a decrease in the aperture ratio of the liquid crystal panel, and the display brightness of the liquid crystal panel is low.
并且，阵列基板也是OLED显示面板，电子纸显示面板等显示面板的必要组成部分，当这些显示面板需要在上基板(指与阵列基板相对设置的另一基板)上设置黑矩阵时，同样存在上述黑矩阵造成的问题。Moreover, the array substrate is also an essential part of display panels such as OLED display panels and electronic paper display panels. Problems caused by black matrix.
发明内容Contents of the invention
为解决上述问题，本发明提供一种阵列基板及其制造方法和显示装置，用于解决现有技术中液晶面板等显示面板的开口率小、显示亮度低的问题。In order to solve the above problems, the present invention provides an array substrate and its manufacturing method and display device, which are used to solve the problems of small aperture ratio and low display brightness of display panels such as liquid crystal panels in the prior art.
为此，本发明提供一种阵列基板，包括基板，以及在所述基板上形成的薄膜晶体管、扫描线、数据线、像素电极和钝化层，所述薄膜晶体管的栅极和源极分别与所述扫描线和数据线连接，所述薄膜晶体管的漏极与所述像素电极连接，其特征在于，所述阵列基板还包括：To this end, the present invention provides an array substrate, including a substrate, and thin film transistors, scan lines, data lines, pixel electrodes and passivation layers formed on the substrate, the gate and source of the thin film transistors are respectively connected to The scanning line is connected to the data line, and the drain of the thin film transistor is connected to the pixel electrode, wherein the array substrate further includes:
黑矩阵，所述黑矩阵与所述薄膜晶体管、扫描线和数据线对应设置。A black matrix, the black matrix is arranged corresponding to the thin film transistors, scanning lines and data lines.
其中，所述黑矩阵设置在所述钝化层上。Wherein, the black matrix is disposed on the passivation layer.
其中，所述黑矩阵设置在所述钝化层与所述基板之间。Wherein, the black matrix is disposed between the passivation layer and the substrate.
其中，所述黑矩阵和所述像素电极交错设置。Wherein, the black matrix and the pixel electrodes are arranged alternately.
进一步地，所述阵列基板还包括公共电极，其中，所述公共电极位于所述像素电极的上方或者下方，所述公共电极和所述像素电极中位于上方的为狭缝状。此时为ADS型阵列基板。Further, the array substrate further includes a common electrode, wherein the common electrode is located above or below the pixel electrode, and the upper one of the common electrode and the pixel electrode is in the shape of a slit. In this case, it is an ADS type array substrate.
本发明还提供一种显示装置，其中包括上述的阵列基板。The present invention also provides a display device, which includes the above-mentioned array substrate.
本发明还提供一种阵列基板的制造方法，包括在基板上制备薄膜晶体管、扫描线、数据线、像素电极和钝化层，其中，所述制造方法还包括：The present invention also provides a method for manufacturing an array substrate, including preparing thin film transistors, scan lines, data lines, pixel electrodes, and a passivation layer on the substrate, wherein the manufacturing method further includes:
在所述基板的上方制备黑矩阵，所述黑矩阵与所述扫描线、数据线和薄膜晶体管对应设置。A black matrix is prepared above the substrate, and the black matrix is arranged corresponding to the scanning lines, data lines and thin film transistors.
其中，所述在所述基板上方制备黑矩阵包括：Wherein, the preparation of a black matrix above the substrate includes:
步骤1、在制备栅极、栅绝缘层、有源层、源/漏电极和数据线的基板上沉积钝化层、黑矩阵层和光刻胶层；其中，所述黑矩阵层和所述光刻胶层为具有相同光感应特性的光刻胶材料；Step 1, depositing a passivation layer, a black matrix layer and a photoresist layer on the substrate for preparing gate, gate insulating layer, active layer, source/drain electrodes and data lines; wherein, the black matrix layer and the The photoresist layer is a photoresist material with the same photosensitive characteristics;
步骤2、通过灰色调掩膜板或半色调掩膜板对完成步骤1的基板进行构图工艺以得到过孔，然后灰化去除像素电极区域上的光刻胶和黑矩阵层，同时在基板的其余位置保留预设厚度的光刻胶层；Step 2. Patterning the substrate completed in step 1 through a gray-tone mask or a half-tone mask to obtain via holes, and then ashing to remove the photoresist and black matrix layer on the pixel electrode area. Retain a photoresist layer with a preset thickness in the rest of the positions;
步骤3、在完成步骤2的基板上沉积透明导电层，利用离地剥离(lift off)工艺剥离掉保留的光刻胶层以及其上的透明导电层，形成像素电极的图形并露出黑矩阵。Step 3, depositing a transparent conductive layer on the substrate completed in step 2, peeling off the remaining photoresist layer and the transparent conductive layer thereon by using a lift off process, forming a pattern of pixel electrodes and exposing the black matrix.
其中，所述步骤2包括：Wherein, said step 2 includes:
步骤21、利用灰色调掩膜板或半色调掩膜板对所述黑矩阵层和光刻胶层进行曝光和显影处理，形成光刻胶半保留区、光刻胶完全去除区和光刻胶完全保留区，其中，光刻胶半保留区对应像素电极区域，光刻胶完全去除区对应过孔区域，光刻胶完全保留区对应黑矩阵层区域，所述光刻胶半保留区域的光刻胶被完全去除，所述光刻胶完全去除区的光刻胶和黑矩阵被完全去除；Step 21: Exposing and developing the black matrix layer and the photoresist layer using a gray tone mask or a halftone mask to form photoresist semi-retained areas, photoresist completely removed areas and photoresist The fully reserved area, wherein, the photoresist semi-reserved area corresponds to the pixel electrode area, the photoresist completely removed area corresponds to the via hole area, the photoresist completely reserved area corresponds to the black matrix layer area, and the light in the photoresist semi-reserved area corresponds to the via hole area. The resist is completely removed, and the photoresist and black matrix in the photoresist complete removal area are completely removed;
步骤22、刻蚀所述光刻胶完全去除区的钝化层形成过孔的图形；Step 22, etching the passivation layer in the photoresist completely removed region to form a via hole pattern;
步骤23、对完成步骤22的基板进行灰化处理，控制灰化处理时间以去除像素电极区域上的黑矩阵层，同时在基板的其余位置保留预设厚度的光刻胶层。Step 23: Perform ashing treatment on the substrate completed in step 22, and control the ashing treatment time to remove the black matrix layer on the pixel electrode area, while retaining a photoresist layer with a preset thickness on the rest of the substrate.
其中，所述黑矩阵层和所述光刻胶层为具有相同光感应特性的光刻胶材料，具体为：Wherein, the black matrix layer and the photoresist layer are photoresist materials with the same photosensitive characteristics, specifically:
所述黑矩阵层和光刻胶层均为负性光刻胶材料沉积得到。Both the black matrix layer and the photoresist layer are obtained by depositing negative photoresist materials.
其中，所所述在所述基板上方制备黑矩阵包括：Wherein, said preparing black matrix above said substrate comprises:
在所述阵列基板的基板和钝化层之间的任意位置沉积黑矩阵层；Depositing a black matrix layer at any position between the substrate and the passivation layer of the array substrate;
对所述黑矩阵层进行光刻以得到黑矩阵。Photolithography is performed on the black matrix layer to obtain a black matrix.
其中，所述阵列基板的制造方法还包括：Wherein, the manufacturing method of the array substrate further includes:
在完成所述步骤3的基板上形成公共电极，所述公共电极为狭缝状。A common electrode is formed on the substrate after the step 3, and the common electrode is in the shape of a slit.
本发明具有下述有益效果：The present invention has following beneficial effect:
本发明提供的阵列基板和显示装置，通过将黑矩阵设置在阵列基板上，并将黑矩阵与薄膜晶体管、扫描线和数据线对应设置，避免了设置在彩膜基板上的黑矩阵与阵列基板上的薄膜晶体管、数据线和扫描线之间发生的偏离，解决了由于上述偏离造成的漏光现象，同时也有利于降低黑矩阵的面积，增大液晶面板等显示面板的开口率，提高液晶面板等显示面板的亮度。In the array substrate and display device provided by the present invention, by arranging the black matrix on the array substrate, and correspondingly arranging the black matrix and the thin film transistors, scanning lines and data lines, the black matrix and the array substrate arranged on the color filter substrate are avoided. The deviation between the thin film transistors, data lines and scanning lines on the upper surface solves the light leakage phenomenon caused by the above deviation, and also helps to reduce the area of the black matrix, increase the aperture ratio of the display panel such as the liquid crystal panel, and improve the liquid crystal panel. Wait for the brightness of the display panel.
本发明提供的阵列基板的制造方法，通过3次掩膜工艺就可以制备得到设置有黑矩阵阵列基板，黑矩阵与薄膜晶体管、扫描线和数据线对应设置，不仅避免了设置在彩膜基板上的黑矩阵与阵列基板上的薄膜晶体管、数据线和扫描线之间发生偏离而造成的漏光现象，有利于降低黑矩阵的面积，增大液晶面板等显示面板的开口率，提高液晶面板等显示面板的亮度，同时也减少了制备的工艺步骤，提高了制约生产效率的曝光机的利用率，降低了生产成本。The method for manufacturing an array substrate provided by the present invention can prepare an array substrate provided with a black matrix through three masking processes, and the black matrix is arranged correspondingly to the thin film transistors, scanning lines and data lines, which not only avoids being arranged on the color filter substrate The light leakage phenomenon caused by the deviation between the black matrix and the thin film transistors, data lines and scanning lines on the array substrate is conducive to reducing the area of the black matrix, increasing the aperture ratio of the display panel such as the liquid crystal panel, and improving the display of the liquid crystal panel. The brightness of the panel also reduces the manufacturing process steps, improves the utilization rate of the exposure machine that restricts the production efficiency, and reduces the production cost.
附图说明Description of drawings
图1为本发明一种阵列基板实施例的俯视图；FIG. 1 is a top view of an embodiment of an array substrate of the present invention;
图2为图1中A-A方向的切面图；Fig. 2 is the sectional view of A-A direction in Fig. 1;
图3为本发明液晶面板实施例的结构示意图；3 is a schematic structural view of an embodiment of a liquid crystal panel of the present invention;
图4为本发明阵列基板的一种制造方法实施例的流程图；FIG. 4 is a flowchart of an embodiment of a manufacturing method of an array substrate of the present invention;
图5为本实施例中第一产品的结构示意图；Fig. 5 is the structural representation of the first product in the present embodiment;
图6为本实施例中第二产品的结构示意图；Fig. 6 is the structural representation of the second product in the present embodiment;
图7为本实施例中第三产品的结构示意图；Fig. 7 is the structural representation of the 3rd product in the present embodiment;
图8为本实施例中第四产品的结构示意图；Fig. 8 is the structural representation of the fourth product in the present embodiment;
图9为本实施例中第五产品的结构示意图；Fig. 9 is a schematic structural view of the fifth product in this embodiment;
图10为本实施例中第六产品的结构示意图；Fig. 10 is the structural representation of the sixth product in the present embodiment;
图11为本实施例中第七产品的结构示意图。Fig. 11 is a schematic structural diagram of the seventh product in this embodiment.
具体实施方式Detailed ways
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的阵列基板及其制造方法和显示装置进行详细描述。In order for those skilled in the art to better understand the technical solution of the present invention, the array substrate, its manufacturing method and display device provided by the present invention will be described in detail below with reference to the accompanying drawings.
本发明实施例提供一种阵列基板，包括基板，以及在基板上形成的薄膜晶体管、扫描线、数据线、像素电极和钝化层，薄膜晶体管的栅极和源极分别与扫描线和数据线连接，薄膜晶体管的漏极与像素电极连接。该阵列基板还包括：黑矩阵，该黑矩阵与薄膜晶体管、扫描线和数据线对应设置。其中，对应设置，主要指黑矩阵覆盖薄膜晶体管、扫描线和数据线。下面，以一个典型的实施例具体介绍本发明实施例的阵列基板结构：An embodiment of the present invention provides an array substrate, including a substrate, and a thin film transistor, a scan line, a data line, a pixel electrode, and a passivation layer formed on the substrate. The gate and source of the thin film transistor are connected to the scan line and the data line respectively. connected, the drain of the thin film transistor is connected to the pixel electrode. The array substrate also includes: a black matrix, which is arranged corresponding to the thin film transistors, scanning lines and data lines. Wherein, the corresponding setting mainly refers to the black matrix covering the thin film transistors, scanning lines and data lines. In the following, a typical embodiment is used to specifically introduce the structure of the array substrate of the embodiment of the present invention:
图1为本发明一种阵列基板实施例的俯视图，图2为图1中A-A方向的切面图。如图1和图2所示，本实施例中阵列基板包括基板101、薄膜晶体管、像素电极110、扫描线111和数据线112，薄膜晶体管包括栅极102、栅绝缘层103、有源层104a、欧姆接触层104b、源极105、漏极106。具体地，在基板101上制备有栅极102、栅绝缘层103、有源层104a、欧姆接触层104b、源极105、漏极106、钝化层107、像素电极110、扫描线111和数据线112；其中，栅绝缘层103覆盖在栅极102上，有源层104a设置在栅绝缘层103上，有源层104a通过欧姆接触层104b分别与源极105和漏极106连接，像素电极110通过过孔109与漏极106相连，在源极105和漏极106上覆盖一层具有保护作用的钝化层107，栅极102与扫描线111连接，源极105与数据线112连接；本实施例阵列基板的钝化层107上还覆盖一层黑矩阵108，黑矩阵108与薄膜晶体管、扫描线111和数据线112对应设置。考虑连接像素电极的需要，薄膜晶体管的过孔区域没有覆盖黑矩阵。FIG. 1 is a top view of an embodiment of an array substrate of the present invention, and FIG. 2 is a sectional view along the A-A direction in FIG. 1 . As shown in Figures 1 and 2, the array substrate in this embodiment includes a substrate 101, a thin film transistor, a pixel electrode 110, a scanning line 111, and a data line 112, and the thin film transistor includes a gate 102, a gate insulating layer 103, and an active layer 104a. , ohmic contact layer 104b, source 105, and drain 106. Specifically, a gate 102, a gate insulating layer 103, an active layer 104a, an ohmic contact layer 104b, a source 105, a drain 106, a passivation layer 107, a pixel electrode 110, a scan line 111 and a data line 112; wherein, the gate insulating layer 103 is covered on the gate 102, the active layer 104a is arranged on the gate insulating layer 103, the active layer 104a is respectively connected to the source electrode 105 and the drain electrode 106 through the ohmic contact layer 104b, and the pixel electrode 110 is connected to the drain 106 through the via hole 109, and a protective passivation layer 107 is covered on the source 105 and the drain 106, the gate 102 is connected to the scanning line 111, and the source 105 is connected to the data line 112; In this embodiment, the passivation layer 107 of the array substrate is also covered with a layer of black matrix 108 , and the black matrix 108 is arranged corresponding to thin film transistors, scanning lines 111 and data lines 112 . Considering the need to connect the pixel electrodes, the via hole area of the thin film transistor does not cover the black matrix.
由图2得知，本实施例中的黑矩阵108和像素电极110设置阵列基板的顶层，黑矩阵108位于像素电极110相邻的两侧，其中，黑矩阵108在基板101上的投影将完全覆盖住薄膜晶体管、扫描线111和数据线112在基板101上的投影，同时确保黑矩阵108与像素电极110之间交错设置(即，二者图形互补或近似互补的设置)，以使黑矩阵108既能阻挡除像素电极110之外区域的漏光，又不妨碍像素电极110的透光。当光线从基板101垂直入射时，光线将从透明的像素电极110出射，而经过薄膜晶体管、扫描线111和数据线112的光线将被黑矩阵108遮挡住，从而确保光线只从像素电极110出射。It can be known from FIG. 2 that the black matrix 108 and the pixel electrode 110 in this embodiment are arranged on the top layer of the array substrate, and the black matrix 108 is located on both sides adjacent to the pixel electrode 110, wherein the projection of the black matrix 108 on the substrate 101 will be completely Cover the projections of the thin film transistors, scan lines 111 and data lines 112 on the substrate 101, while ensuring that the black matrix 108 and the pixel electrode 110 are arranged alternately (that is, the two graphics are complementary or approximately complementary), so that the black matrix 108 can not only block light leakage in areas other than the pixel electrode 110 , but also not hinder the light transmission of the pixel electrode 110 . When the light is vertically incident on the substrate 101, the light will emerge from the transparent pixel electrode 110, and the light passing through the thin film transistor, the scanning line 111 and the data line 112 will be blocked by the black matrix 108, so as to ensure that the light only exits from the pixel electrode 110 .
由图1得知，I区域对应阵列基板的像素电极110，II区域对应钝化层107中的过孔109，III区域对应阵列基板的黑矩阵108。It can be known from FIG. 1 that the I region corresponds to the pixel electrode 110 of the array substrate, the II region corresponds to the via hole 109 in the passivation layer 107 , and the III region corresponds to the black matrix 108 of the array substrate.
在实际应用中，可以将黑矩阵108设置在基板101和钝化层107之间的任何位置，只要确保黑矩阵108在基板101上的投影将完全覆盖住薄膜晶体管、扫描线111和数据线112在基板101上的投影即可，避免黑矩阵108与薄膜晶体管、扫描线111和数据线112发生偏离。当然，考虑到连接像素电极的需要，薄膜晶体管的过孔区域可以不覆盖黑矩阵；由于漏极金属同样具有遮光作用，因此并不影响黑矩阵的功能发挥。In practical applications, the black matrix 108 can be arranged at any position between the substrate 101 and the passivation layer 107, as long as it is ensured that the projection of the black matrix 108 on the substrate 101 will completely cover the thin film transistors, scan lines 111 and data lines 112 The projection on the substrate 101 is enough to prevent the black matrix 108 from deviating from the thin film transistors, the scan lines 111 and the data lines 112 . Of course, considering the need to connect the pixel electrodes, the via hole area of the thin film transistor may not cover the black matrix; since the drain metal also has a light-shielding function, it does not affect the function of the black matrix.
以上实施例描述的是传统的TN模式的阵列基板。进一步地，本发明的黑矩阵设置方式也可以在ADS等模式的电场中实现，即所述阵列基板可以还包括公共电极，其中，所述公共电极位于所述像素电极的上方或者下方，所述公共电极和所述像素电极中位于上方的为狭缝状。The above embodiments describe a traditional TN mode array substrate. Furthermore, the arrangement of the black matrix of the present invention can also be implemented in an electric field in an ADS mode, that is, the array substrate can further include a common electrode, wherein the common electrode is located above or below the pixel electrode, and the The upper one of the common electrode and the pixel electrodes is in the shape of a slit.
本发明实施例还提供一种显示装置，使用了上述的阵列基板。所述显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。下面以液晶面板为例进行阐释：An embodiment of the present invention also provides a display device using the above-mentioned array substrate. The display device may be any product or component with a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal TV, a liquid crystal display, a digital photo frame, a mobile phone, and a tablet computer. Let's take the LCD panel as an example to illustrate:
图3为本发明液晶面板实施例的结构示意图。如图3所示，本实施例液晶面板包括阵列基板、彩膜基板20和液晶层30，其中，阵列基板采用上述任意一种阵列基板，阵列基板上的黑矩阵108与薄膜晶体管、扫描线111和数据线112对应设置。在本实施例中，阵列基板采用图1、2所示的结构，由于阵列基板上已经设置有防止漏光的黑矩阵层，所以本实施例中的彩膜层30中不需要设置黑矩阵。FIG. 3 is a schematic structural diagram of an embodiment of a liquid crystal panel of the present invention. As shown in FIG. 3 , the liquid crystal panel of this embodiment includes an array substrate, a color filter substrate 20 and a liquid crystal layer 30, wherein the array substrate adopts any of the above-mentioned array substrates, and the black matrix 108 on the array substrate, the thin film transistors, and the scanning lines 111 Corresponding to the data line 112. In this embodiment, the array substrate adopts the structure shown in FIGS. 1 and 2 . Since a black matrix layer for preventing light leakage is already provided on the array substrate, the color filter layer 30 in this embodiment does not need to be provided with a black matrix.
本实施例液晶面板中，将黑矩阵设置在阵列基板上，并将黑矩阵与薄膜晶体管、扫描线和数据线对应设置，避免了设置在彩膜基板上的黑矩阵与阵列基板上的薄膜晶体管、数据线和扫描线之间发生的偏离，解决了由于上述偏离造成的漏光现象，同时也有利于降低黑矩阵的面积，增大液晶面板的开口率，提高液晶面板的亮度。In the liquid crystal panel of this embodiment, the black matrix is arranged on the array substrate, and the black matrix and the thin film transistor, the scanning line and the data line are arranged correspondingly, avoiding the black matrix arranged on the color filter substrate and the thin film transistor on the array substrate. , The deviation between the data line and the scanning line solves the light leakage phenomenon caused by the above deviation, and also helps to reduce the area of the black matrix, increase the aperture ratio of the liquid crystal panel, and improve the brightness of the liquid crystal panel.
本发明实施例提供的显示装置，由于阵列基板上的黑矩阵与薄膜晶体管、扫描线和数据线对应设置，避免了将黑矩阵设置在彩膜基板时，由于彩膜基板与阵列基板的对位不精确而导致黑矩阵与阵列基板上的薄膜晶体管、扫描线和数据线发生偏离，防止由于上述偏离造成的漏光现象，同时也有利于降低黑矩阵的面积，增大液晶面板等显示面板的开口率，提高液晶面板等显示面板的亮度。In the display device provided by the embodiment of the present invention, since the black matrix on the array substrate is arranged correspondingly to the thin film transistors, scanning lines, and data lines, it avoids problems caused by the alignment between the color filter substrate and the array substrate when the black matrix is arranged on the color filter substrate. Inaccuracy causes the black matrix to deviate from the thin film transistors, scan lines and data lines on the array substrate, preventing light leakage caused by the above deviation, and also helps to reduce the area of the black matrix and increase the opening of display panels such as liquid crystal panels Ratio, improve the brightness of display panels such as LCD panels.
本发明还提供一种阵列基板的制造方法，包括在基板上制备薄膜晶体管、扫描线、数据线、像素电极和钝化层，其中，还包括在阵列基板上制备一层黑矩阵，黑矩阵与薄膜晶体管、扫描线和数据线对应设置，黑矩阵可以位于阵列基板的顶层，也可以位于基板与钝化层之间的任意位置，只要确保黑矩阵在基板上的投影完全覆盖住薄膜晶体管、扫描线和数据线在基板上的投影即可，当有光线经过基板进入阵列基板时，阵列基板的薄膜晶体管、扫描线和数据线的位置处的光线将被黑矩阵阻挡，因此不会有光线输出，在利用该阵列基板制备的液晶面板时，可以避免光线经过阵列基板的薄膜晶体管、扫描线和数据线的位置输出，从而解决了液晶面板的漏光现象。The present invention also provides a method for manufacturing an array substrate, which includes preparing thin film transistors, scan lines, data lines, pixel electrodes, and a passivation layer on the substrate, and further includes preparing a layer of black matrix on the array substrate, the black matrix and Thin film transistors, scanning lines and data lines are arranged correspondingly. The black matrix can be located on the top layer of the array substrate, or at any position between the substrate and the passivation layer, as long as the projection of the black matrix on the substrate completely covers the thin film transistors, scanning Lines and data lines can be projected on the substrate. When light passes through the substrate and enters the array substrate, the light at the positions of the thin film transistors, scan lines and data lines on the array substrate will be blocked by the black matrix, so there will be no light output , when using the liquid crystal panel prepared by the array substrate, the output of light through the position of the thin film transistor, the scanning line and the data line of the array substrate can be avoided, thereby solving the light leakage phenomenon of the liquid crystal panel.
图4为本发明阵列基板的一种制造方法实施例的流程图，图5为本实施例中第一产品的结构示意图，图6为本实施例中第二产品的结构示意图，图7为本实施例中第三产品的结构示意图，图8为本实施例中第四产品的结构示意图，图9为本实施例中第五产品的结构示意图，图10为本实施例中第六产品的结构示意图，图11为本实施例中第七产品的结构示意图。如图4所示，本实施例阵列基板的制造方法具体包括如下步骤：Fig. 4 is a flowchart of an embodiment of a manufacturing method of an array substrate according to the present invention, Fig. 5 is a schematic structural diagram of the first product in this embodiment, Fig. 6 is a schematic structural diagram of a second product in this embodiment, and Fig. 7 is a schematic diagram of this embodiment The structure diagram of the third product in the embodiment, Fig. 8 is the structure diagram of the fourth product in the present embodiment, Fig. 9 is the structure diagram of the fifth product in the present embodiment, and Fig. 10 is the structure of the sixth product in the present embodiment Schematic diagram, Figure 11 is a schematic structural diagram of the seventh product in this embodiment. As shown in FIG. 4, the manufacturing method of the array substrate in this embodiment specifically includes the following steps:
步骤401、在基板上制备栅极。Step 401 , preparing a gate on the substrate.
在本步骤中，如图5所示并参阅图1和2，在基板101上沉积一金属层和光刻胶层，然后通过掩膜工艺得到栅极102、扫描线111和公共电极(图中未示出)，掩膜工艺包括对光刻胶进行曝光和显影的光刻工艺，以得到在光刻胶层中形成的栅极102、扫描线和公共电极的光刻胶图案，然后利用光刻胶图案作为遮挡层对金属层进行刻蚀工艺，从而得到栅极102、扫描线和公共电极，然后进入步骤402。In this step, as shown in FIG. 5 and referring to FIGS. 1 and 2, a metal layer and a photoresist layer are deposited on the substrate 101, and then the gate 102, the scanning line 111 and the common electrode (in the figure) are obtained through a mask process. not shown), the masking process includes a photolithography process of exposing and developing the photoresist to obtain the photoresist pattern of the gate 102, scanning lines and common electrodes formed in the photoresist layer, and then use photoresist The resist pattern is used as a shielding layer to etch the metal layer, so as to obtain the gate 102 , scan lines and common electrodes, and then go to step 402 .
步骤402、在完成上述步骤的基板上制备栅绝缘层、有源层、源电极和漏电极。Step 402 , preparing a gate insulating layer, an active layer, a source electrode and a drain electrode on the substrate after the above steps.
本步骤中，如图6所示并参阅图1和2，在完成上述步骤401的基板401依次沉积栅绝缘层103、半导体材料层、金属层和光刻胶层，然后对光刻胶层进行光刻以得到光刻胶图案，然后利用光刻胶图案作为遮挡层对半导体材料层和金属层进行刻蚀，以在半导体材料层中得到有源层104a，在金属层中得到源极105、漏极106和数据线112，其中，半导体材料层可以由a-Si、p-Si、IGZO(In-Ga-Zn-O)等半导体材料沉积得到。在实际应用中，为了增大有源层140a与源极105和漏极106欧姆接触，可以在沉积半导体材料层之后，对半导体材料层进行离子注入以得到欧姆接触层104b。In this step, as shown in FIG. 6 and referring to FIGS. 1 and 2, a gate insulating layer 103, a semiconductor material layer, a metal layer and a photoresist layer are sequentially deposited on the substrate 401 that has completed the above step 401, and then the photoresist layer is processed. Photolithography to obtain a photoresist pattern, and then use the photoresist pattern as a shielding layer to etch the semiconductor material layer and the metal layer to obtain the active layer 104a in the semiconductor material layer, and obtain the source electrode 105, The drain electrode 106 and the data line 112, wherein the semiconductor material layer can be obtained by depositing a-Si, p-Si, IGZO (In-Ga-Zn-O) and other semiconductor materials. In practical applications, in order to increase the ohmic contact between the active layer 140 a and the source 105 and drain 106 , after depositing the semiconductor material layer, ion implantation can be performed on the semiconductor material layer to obtain the ohmic contact layer 104 b.
在基板上制备栅绝缘层103、有源层104a、源电极105和漏电极106之后，进入步骤403。After preparing the gate insulating layer 103 , the active layer 104 a , the source electrode 105 and the drain electrode 106 on the substrate, go to step 403 .
步骤403、在完成上述步骤的基板上制备钝化层、黑矩阵和像素电极。Step 403 , preparing a passivation layer, a black matrix and pixel electrodes on the substrate after the above steps.
在本步骤中，如图7所示，在完成上述步骤的基板上依次沉积钝化层107、黑矩阵108和光刻胶层119，其中，黑矩阵层108和光刻胶层119为具有相同光感应特性的光刻胶材料；优选地，黑矩阵108和光刻胶层119均为负性光刻胶材料，未被曝光的负性光刻胶可以被显影液去除。In this step, as shown in FIG. 7 , a passivation layer 107, a black matrix 108 and a photoresist layer 119 are sequentially deposited on the substrate after the above steps, wherein the black matrix layer 108 and the photoresist layer 119 have the same A photoresist material with photosensitive properties; preferably, both the black matrix 108 and the photoresist layer 119 are negative photoresist materials, and the unexposed negative photoresist can be removed by a developer.
如图8所示并参阅图1，利用灰色调掩膜板或半色调掩膜板对光刻胶层119进行曝光，基板101上的I区域对应灰色调掩膜板或半色调掩膜板的半曝光区域，II区域对应灰色调掩膜板或半色调掩膜板的未曝光区域，III区域对应灰色调掩膜板或半色调掩膜板的完全曝光区域，对经过曝光的黑矩阵108和光刻胶层119进行显影之后，I区域上的光刻胶层被去除但该区域的黑矩阵层则被保留，II区域上的光刻胶层和黑矩阵层被完全去除，III区域上的光刻胶层119和黑矩阵108被保留，从而得到光刻胶层图案和黑矩阵层图案。As shown in FIG. 8 and referring to FIG. 1, the photoresist layer 119 is exposed using a gray-tone mask or a half-tone mask, and the I region on the substrate 101 corresponds to the gray-tone mask or the half-tone mask. In the half-exposed area, the II area corresponds to the unexposed area of the gray-tone mask or the half-tone mask, and the III area corresponds to the fully exposed area of the gray-tone mask or the half-tone mask. For the exposed black matrix 108 and After the photoresist layer 119 is developed, the photoresist layer on the I region is removed but the black matrix layer in this region is retained, the photoresist layer and the black matrix layer on the II region are completely removed, and the photoresist layer and the black matrix layer on the III region are completely removed. The photoresist layer 119 and the black matrix 108 are retained, thereby obtaining a photoresist layer pattern and a black matrix layer pattern.
如图9所示，利用图8中得到的光刻胶层图案和黑矩阵层图案作为遮挡层刻蚀钝化层107以得到过孔109的图形。As shown in FIG. 9 , the passivation layer 107 is etched using the photoresist layer pattern and the black matrix layer pattern obtained in FIG. 8 as a shielding layer to obtain a pattern of via holes 109 .
如图10所示，对图9中的基板上的光刻胶119和黑矩阵108进行灰化处理，控制灰化处理的时间，将I区域上的黑矩阵108全部去除，同时将III区域上的光刻胶层119部分去除，使III区域上仍然保留一定厚度的光刻胶层119。As shown in FIG. 10, the photoresist 119 and the black matrix 108 on the substrate in FIG. Part of the photoresist layer 119 is removed, so that a certain thickness of the photoresist layer 119 remains on the III region.
如图11所示，在图10所示的基板上沉积一层透明导电材料层120以制备像素电极，透明导电材料层120可以为铟锡氧化物(ITO)等。由于III区域上的黑矩阵108和光刻胶层119的厚度较高，因此III区域上的光刻胶层119的顶层距离过孔109的底部较高，所以在沉积厚度较小的透明导电材料层120时，透明导电材料层120在过孔109靠近III区域的侧壁处发生断裂，导致I区域上的透明导电材料层与III区域上的透明导电材料层相互独立；参阅图2，利用离地剥离(Lift Off)工艺剥离光刻胶层119，离地剥离工艺就是利用剥离液来剥离掉光刻胶层119，同时剥离液对黑矩阵108无剥离作用，本实施例在采用剥离液来剥离III区域上的光刻胶层119时，由于I区域和III区域上的透明导电材料层相互独立，III区域上光刻胶层119上的透明导电材料层也将随着光刻胶层119而脱离阵列基板，从而露出黑矩阵108，而沉积在I区域上的透明导电材料层则形成像素电极110，从而得到包括有黑矩阵108的阵列基板，阵列基板如图1或2所示。As shown in FIG. 11 , a transparent conductive material layer 120 is deposited on the substrate shown in FIG. 10 to prepare pixel electrodes. The transparent conductive material layer 120 may be indium tin oxide (ITO) or the like. Since the thickness of the black matrix 108 and the photoresist layer 119 on the III region is relatively high, the top layer of the photoresist layer 119 on the III region is relatively high from the bottom of the via hole 109, so the transparent conductive material with a small thickness is deposited layer 120, the transparent conductive material layer 120 breaks at the sidewall of the via hole 109 close to the III region, causing the transparent conductive material layer on the I region and the transparent conductive material layer on the III region to be independent of each other; referring to FIG. The lift off (Lift Off) process strips the photoresist layer 119, and the lift off process uses the stripping liquid to peel off the photoresist layer 119, and the stripping liquid has no stripping effect on the black matrix 108. In this embodiment, the stripping liquid is used to remove the photoresist layer 119 When peeling off the photoresist layer 119 on the III region, since the transparent conductive material layers on the I region and the III region are independent of each other, the transparent conductive material layer on the photoresist layer 119 on the III region will also follow the photoresist layer 119 The black matrix 108 is exposed from the array substrate, and the transparent conductive material layer deposited on the I region forms the pixel electrode 110, thereby obtaining an array substrate including the black matrix 108, as shown in FIG. 1 or 2 .
以上工艺步骤，实现了典型的TN模式的阵列基板的制造。The above process steps realize the manufacture of a typical TN mode array substrate.
进一步地，在完成上述步骤后，还包括：在完成上述步骤的基板上形成公共电极，所述公共电极为狭缝状。这样就形成了一种典型的ADS模式的阵列基板结构。本领域的技术人员可以理解，上述形成ADS的公共电极的步骤，还可能包括形成绝缘层的步骤，其与现有技术无异，此处不赘。当然，形成公共电极的步骤也可以根据实际设计安排在上述各个步骤的某些步骤之间，以形成不同类型的ADS结构。Further, after the above steps are completed, the method further includes: forming a common electrode on the substrate after the above steps, and the common electrode is in the shape of a slit. In this way, a typical ADS mode array substrate structure is formed. Those skilled in the art can understand that the above step of forming the common electrode of the ADS may also include the step of forming an insulating layer, which is the same as the prior art and will not be repeated here. Certainly, the step of forming the common electrode can also be arranged between certain steps of the above-mentioned steps according to actual design, so as to form different types of ADS structures.
在实际应用中，也可以将黑矩阵设置在基板和钝化层之间的任意位置，只要确保黑矩阵的介电常数符合阵列基板的电学要求即可，在此不再赘述。In practical applications, the black matrix can also be arranged at any position between the substrate and the passivation layer, as long as the dielectric constant of the black matrix meets the electrical requirements of the array substrate, and details will not be repeated here.
本实施例中，通过3次掩膜工艺就可以制备得到设置有黑矩阵阵列基板(针对TN模式，制作ADS模式需相应增加掩摸工艺)，黑矩阵与薄膜晶体管、扫描线和数据线对应设置，不仅避免了设置在彩膜基板上的黑矩阵与阵列基板上的薄膜晶体管、数据线和扫描线之间发生偏离而造成的漏光现象，有利于降低黑矩阵的面积，增大液晶面板的开口率，提高液晶面板等显示面板的亮度，同时也减少了制备的工艺步骤，提高了制约生产效率的曝光机的利用率，降低了生产成本。In this embodiment, a substrate with a black matrix array can be prepared through three masking processes (for the TN mode, the ADS mode needs to increase the masking process accordingly), and the black matrix is set correspondingly to the thin film transistors, scanning lines and data lines , which not only avoids the light leakage caused by the deviation between the black matrix arranged on the color filter substrate and the thin film transistors, data lines and scanning lines on the array substrate, but also helps to reduce the area of the black matrix and increase the opening of the liquid crystal panel The efficiency is improved, the brightness of display panels such as liquid crystal panels is improved, and the process steps of preparation are also reduced, the utilization rate of exposure machines that restricts production efficiency is improved, and production costs are reduced.
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210094046.5ACN102629608B (en) | 2012-03-31 | 2012-03-31 | Array substrate, a manufacturing method thereof and display device |
| PCT/CN2012/086403WO2013143321A1 (en) | 2012-03-31 | 2012-12-12 | Array substrate and manufacturing method thereof, and display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210094046.5ACN102629608B (en) | 2012-03-31 | 2012-03-31 | Array substrate, a manufacturing method thereof and display device |
| Publication Number | Publication Date |
|---|---|
| CN102629608A CN102629608A (en) | 2012-08-08 |
| CN102629608Btrue CN102629608B (en) | 2014-12-17 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210094046.5AExpired - Fee RelatedCN102629608B (en) | 2012-03-31 | 2012-03-31 | Array substrate, a manufacturing method thereof and display device |
| Country | Link |
|---|---|
| CN (1) | CN102629608B (en) |
| WO (1) | WO2013143321A1 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102629608B (en)* | 2012-03-31 | 2014-12-17 | 京东方科技集团股份有限公司 | Array substrate, a manufacturing method thereof and display device |
| CN102981306B (en)* | 2012-12-07 | 2016-03-30 | 京东方科技集团股份有限公司 | A kind of method for making of colored filter |
| CN103838044B (en)* | 2014-02-26 | 2017-08-29 | 京东方科技集团股份有限公司 | Substrate and its manufacture method, display device |
| CN104360529B (en)* | 2014-11-26 | 2017-05-10 | 深圳市华星光电技术有限公司 | TFT (thin film transistor) substrate and manufacturing method thereof |
| CN104714347B (en)* | 2015-04-03 | 2018-09-18 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN105655292B (en)* | 2016-01-05 | 2019-03-15 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, array substrate and manufacturing method thereof |
| US10312228B2 (en)* | 2017-01-25 | 2019-06-04 | Innolux Corporation | Display device |
| CN214505500U (en)* | 2020-09-15 | 2021-10-26 | 信利半导体有限公司 | Display panel and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3024592B2 (en)* | 1997-05-02 | 2000-03-21 | 日本電気株式会社 | Liquid crystal display device and method of manufacturing the same |
| KR101177720B1 (en)* | 2005-09-20 | 2012-08-28 | 엘지디스플레이 주식회사 | LCD and Method of fabricating of the same |
| KR101331901B1 (en)* | 2006-06-30 | 2013-11-22 | 엘지디스플레이 주식회사 | Liquid crystal display device and method for fabricating the same |
| CN101825815B (en)* | 2009-03-06 | 2013-02-13 | 北京京东方光电科技有限公司 | TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array baseplate and manufacturing method thereof |
| CN102012590B (en)* | 2009-09-04 | 2012-02-29 | 京东方科技集团股份有限公司 | FFS type TFT-LCD array substrate and manufacturing method thereof |
| CN102629608B (en)* | 2012-03-31 | 2014-12-17 | 京东方科技集团股份有限公司 | Array substrate, a manufacturing method thereof and display device |
| Publication number | Publication date |
|---|---|
| CN102629608A (en) | 2012-08-08 |
| WO2013143321A1 (en) | 2013-10-03 |
| Publication | Publication Date | Title |
|---|---|---|
| CN102629608B (en) | Array substrate, a manufacturing method thereof and display device | |
| CN106876386B (en) | Thin film transistor, preparation method thereof, array substrate and display panel | |
| CN103681693B (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN101825814B (en) | TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array baseplate and manufacturing method thereof | |
| CN105137672B (en) | Array substrate and its manufacturing method | |
| CN103117248B (en) | Array substrate and manufacture method thereof and display device | |
| CN102629584B (en) | Array substrate and manufacturing method thereof and display device | |
| CN104157696B (en) | Thin film transistor and preparation method thereof, as well as array baseplate and liquid crystal display device | |
| TW201418855A (en) | Array substrate of display panel and manufacturing method thereof | |
| CN210325749U (en) | Array substrate and display panel | |
| CN106298646B (en) | The production method of TFT substrate | |
| CN109494257B (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| CN102779783B (en) | Pixel structure, as well as manufacturing method and display device thereof | |
| TWI464787B (en) | Array substrate for edge electric field switching type liquid crystal display panel and manufacturing method thereof | |
| CN106353944A (en) | Array base plate, manufacturing method of array base plate, display panel and display device | |
| CN103681514B (en) | Array base palte and preparation method thereof, display unit | |
| WO2017140058A1 (en) | Array substrate, manufacturing method therefor, display panel and display apparatus | |
| CN103413784B (en) | Array substrate, preparing method thereof and display device | |
| CN102723309A (en) | Array substrate and manufacturing method thereof as well as display device | |
| CN104576526B (en) | A kind of array substrate and preparation method thereof and display device | |
| WO2021097995A1 (en) | Array substrate and preparation method therefor | |
| CN103165530B (en) | Thin film transistor (TFT) array substrate and manufacture method and display device thereof | |
| CN103838047B (en) | Array substrate, manufacturing method thereof and display device | |
| CN104714347A (en) | Array substrate and preparation method thereof and display device | |
| US8900938B2 (en) | Manufacturing method of array substrate, array substrate and LCD device |
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | Granted publication date:20141217 Termination date:20210331 | |
| CF01 | Termination of patent right due to non-payment of annual fee |