技术领域technical field
本发明涉及一种半导体集成电路用器件，特别涉及一种分裂栅结构的纳米线场效应晶体管。The invention relates to a semiconductor integrated circuit device, in particular to a nanowire field effect transistor with a split gate structure.
背景技术Background technique
集成电路工业对更高速度、更高集成度、更低功耗的追求推动着半导体技术向前发展，半导体器件的特征尺寸越来越小。由于在纳米尺寸下传统场效应晶体管受到短沟道效应等限制，性能下降。新的器件结构被提出，包括绝缘体上硅、双栅、三栅和纳米线场效应晶体管。其中纳米线场效应晶体管能提供高的电流开关比，同时受短沟道效应和漏致势垒降低效应影响较小。在现有纳米线场效应晶体管的基础上进一步提高电流开关比，改善尺寸缩小性能对制造高速度、低功耗的半导体集成电路有重要意义。The integrated circuit industry's pursuit of higher speed, higher integration, and lower power consumption is driving the development of semiconductor technology, and the feature size of semiconductor devices is getting smaller and smaller. Due to the limitation of short channel effect and other limitations of traditional field effect transistors at nanometer size, the performance is degraded. New device structures have been proposed, including silicon-on-insulator, double-gate, triple-gate, and nanowire field-effect transistors. Among them, the nanowire field effect transistor can provide a high current switching ratio, and is less affected by the short channel effect and the leakage-induced barrier lowering effect. On the basis of existing nanowire field effect transistors, it is of great significance to further increase the current switching ratio and improve the size reduction performance for the manufacture of high-speed, low-power semiconductor integrated circuits.
发明内容Contents of the invention
本发明的目的是提供一种分裂栅结构的纳米线场效应晶体管器件。The object of the present invention is to provide a nanowire field effect transistor device with a split gate structure.
本发明提供的分裂栅结构的纳米线场效应晶体管，是由分裂栅电极、源区、漏区、沟道区和栅介质层组成；The nanowire field effect transistor with a split gate structure provided by the present invention is composed of a split gate electrode, a source region, a drain region, a channel region and a gate dielectric layer;
其中，所述沟道区呈柱状，所述沟道区位于所述纳米线场效应晶体管的中心，构成所述沟道区的材料为半导体材料；所述栅介质层同轴全包围所述沟道区；所述分裂栅电极位于所述栅介质层之外，并同轴全包围所述栅介质层，构成所述分裂栅电极的材料为两种不同的材料；所述源区和漏区分别位于所述沟道区的两侧。Wherein, the channel region is columnar, the channel region is located at the center of the nanowire field effect transistor, and the material constituting the channel region is a semiconductor material; the gate dielectric layer coaxially completely surrounds the trench The channel region; the split gate electrode is located outside the gate dielectric layer and coaxially surrounds the gate dielectric layer, and the materials constituting the split gate electrode are two different materials; the source region and the drain region respectively located on both sides of the channel region.
上述纳米线场效应晶体管中，构成所述栅介质层的材料为氧化硅。构成该晶体管分裂栅电极结构的长度和厚度均可调，构成该晶体管分裂栅电极结构的材料可调，分裂的两个栅电极掺杂类型和浓度可调。构成靠近源区的分裂栅电极的材料的功函数高于靠近漏区的分裂栅电极的材料的功函数。所述分裂栅电极的直径为10-50纳米，优选20纳米，厚度为5-20纳米，优选10纳米；优选的，构成所述分裂栅电极的材料为硼掺杂浓度为7×1012cm-3的多晶硅或磷掺杂浓度为5×1013cm-3的多晶硅，所述分裂栅电极的功函数为4.40-4.77伏特，具体可为4.40伏特或4.77伏特。所述源区的厚度为10-50纳米，优选30纳米；所述漏区的厚度为10-50纳米，优选30纳米；所述沟道区的半径为5-25纳米，优选10纳米，长度为20-100纳米，优选30纳米；所述栅介质层的厚度为1.0-3.0纳米，优选1.5纳米。沟道区的掺杂类型和浓度可调，如可为硼掺杂浓度为1×1011cm-3的硅，源、漏两端的半导体材料、掺杂类型和浓度均可调，如可均为磷掺杂浓度为1×1020m-3的硅。In the above nanowire field effect transistor, the material constituting the gate dielectric layer is silicon oxide. The length and thickness of the split gate electrode structure of the transistor can be adjusted, the material constituting the split gate electrode structure of the transistor can be adjusted, and the doping type and concentration of the two split gate electrodes can be adjusted. The work function of the material constituting the split gate electrode near the source region is higher than the work function of the material of the split gate electrode near the drain region. The diameter of the split gate electrode is 10-50 nanometers, preferably 20 nanometers, and the thickness is 5-20 nanometers, preferably 10 nanometers; preferably, the material constituting the split gate electrode has a boron doping concentration of 7×1012 cm-3 polysilicon or polysilicon with phosphorus doping concentration of 5×1013 cm−3 , the work function of the split gate electrode is 4.40-4.77 volts, specifically 4.40 volts or 4.77 volts. The thickness of the source region is 10-50 nanometers, preferably 30 nanometers; the thickness of the drain region is 10-50 nanometers, preferably 30 nanometers; the radius of the channel region is 5-25 nanometers, preferably 10 nanometers, the length 20-100 nm, preferably 30 nm; the gate dielectric layer has a thickness of 1.0-3.0 nm, preferably 1.5 nm. The doping type and concentration of the channel region can be adjusted. For example, it can be silicon with a boron doping concentration of 1×1011 cm-3 . The semiconductor material, doping type and concentration at both ends of the source and drain can be adjusted. It is silicon with phosphorus doping concentration of 1×1020 m-3 .
本发明提供的分裂栅结构的纳米线场效应晶体管，与传统的纳米线晶体管相比，在相同的沟道材料和掺杂浓度，源漏区材料和掺杂浓度、栅绝缘层材料和厚度，相同的沟道区长度、沟道区半径的条件下，引入分裂栅结构后可以有效的提高器件的开态电流，同时保持较小的关态电流，因而提高器件的电流开关比和工作速度。同时分裂栅结构的引入能使纳米线场效应晶体管受短沟道效应和漏致势垒降低效应引起的阈值电压漂移减小，热载流子效应也得到有效的抑制，改善了器件尺寸缩小的性能。本发明为纳米线场效应晶体管器件性能优化，结构优化指明了一个新的方向，尤其适用于低功耗高速度的集成电路使用。Compared with the traditional nanowire transistor, the nanowire field effect transistor with split gate structure provided by the present invention has the same channel material and doping concentration, source and drain region material and doping concentration, gate insulating layer material and thickness, Under the same channel region length and channel region radius, the introduction of the split gate structure can effectively increase the on-state current of the device while maintaining a small off-state current, thereby improving the current switching ratio and operating speed of the device. At the same time, the introduction of the split gate structure can reduce the threshold voltage drift caused by the short channel effect and the leakage-induced barrier lowering effect of the nanowire field effect transistor, and the hot carrier effect is also effectively suppressed, which improves the device size reduction. performance. The invention points out a new direction for performance optimization and structure optimization of the nanowire field effect transistor device, and is especially suitable for use in integrated circuits with low power consumption and high speed.
附图说明Description of drawings
图1为本发明提供的分裂栅结构的纳米线场效应晶体管的截面示意图。FIG. 1 is a schematic cross-sectional view of a nanowire field effect transistor with a split gate structure provided by the present invention.
图2为固定晶体管其他参数分裂栅结构对晶体管沟道区电场分布的影响。Figure 2 shows the influence of the split gate structure on the electric field distribution in the channel region of the transistor by fixing other parameters of the transistor.
图3为固定晶体管其他参数分裂栅结构对晶体管开态电流的影响。Figure 3 shows the effect of the split gate structure on the on-state current of the transistor with other parameters of the fixed transistor.
图4为固定晶体管其他参数分裂栅结构对晶体管关态电流的影响。Figure 4 shows the effect of the split gate structure on the off-state current of the transistor with other parameters of the fixed transistor.
图5为固定晶体管其他参数分裂栅结构对晶体管沟道区电势分布的影响。Fig. 5 shows the influence of the split gate structure on the potential distribution of the channel region of the transistor by fixing other parameters of the transistor.
图6为固定晶体管其他参数改变分裂栅结构两部分栅材料的长度对晶体管在不同沟道长度下的漏致势垒降低效应比较。Fig. 6 is a comparison of the drain-induced barrier lowering effect of transistors with different channel lengths when other parameters of the transistor are fixed and the lengths of the gate materials of the two parts of the split gate structure are changed.
具体实施方式Detailed ways
下面结合具体实施例对本发明作进一步阐述，但本发明并不限于以下实施例。所述方法如无特别说明均为常规方法。所述材料如无特别说明均能从公开商业途径而得。The present invention will be further described below in conjunction with specific examples, but the present invention is not limited to the following examples. The methods are conventional methods unless otherwise specified. The materials can be obtained from public commercial sources unless otherwise specified.
实施例1、分裂栅结构的纳米线场效应晶体管及其性能检测Embodiment 1. Nanowire Field Effect Transistor with Split Gate Structure and Its Performance Testing
该分裂栅结构的纳米线场效应晶体管的结构示意图如图1所示，该晶体管由分裂栅电极1和2、源区3、漏区4、沟道区5和栅介质层6组成；其中，沟道区5呈柱状，位于该纳米线场效应晶体管的中心；栅介质层6同轴全包围沟道区5；分裂栅电极1和2位于栅介质层6之外并同轴全包围沟道区5，构成分裂栅电极1和2的材料为两种不同的材料；分裂栅电极1和2外接相同的电偏置；源区3和漏区4分别位于沟道区5的两侧。The structure schematic diagram of the nanowire field effect transistor of this split gate structure is shown in Figure 1, and this transistor is made up of split gate electrode 1 and 2, source region 3, drain region 4, channel region 5 and gate dielectric layer 6; Wherein, The channel region 5 is columnar and located at the center of the nanowire field effect transistor; the gate dielectric layer 6 coaxially surrounds the channel region 5; the split gate electrodes 1 and 2 are located outside the gate dielectric layer 6 and coaxially completely surrounds the channel In region 5, the materials constituting split gate electrodes 1 and 2 are two different materials; split gate electrodes 1 and 2 are externally connected to the same electrical bias; source region 3 and drain region 4 are located on both sides of channel region 5 respectively.
分裂栅电极1和2的直径均为20纳米，厚度均为10纳米，其中，构成分裂栅电极1的材料为硼掺杂浓度为7×1012cm-3的多晶硅，其功函数为4.77伏特，构成分裂栅电极2的材料为磷掺杂浓度为5×1013cm-3的多晶硅，功函数为4.40伏特。构成源区3和漏区4的材料均为磷掺杂浓度为1×1020cm-3的硅，源区和漏区的长度均为30纳米。构成沟道区5的材料为硼掺杂浓度为1×1011cm-3的硅，该沟道区的半径为10nm，长度为30纳米。构成栅介质层6的材料为氧化硅，该栅介质层的厚度为1.5nm。Both split gate electrodes 1 and 2 have a diameter of 20 nanometers and a thickness of 10 nanometers. Among them, the material constituting split gate electrode 1 is polysilicon with a boron doping concentration of 7×1012 cm-3 , and its work function is 4.77 volts. , the material constituting the split gate electrode 2 is polysilicon with phosphorus doping concentration of 5×1013 cm−3 , and the work function is 4.40 volts. The materials constituting the source region 3 and the drain region 4 are both silicon with a phosphorus doping concentration of 1×1020 cm−3 , and the lengths of the source region and the drain region are both 30 nanometers. The material constituting the channel region 5 is silicon with a boron doping concentration of 1×1011 cm−3 , the radius of the channel region is 10 nm, and the length is 30 nm. The material constituting the gate dielectric layer 6 is silicon oxide, and the thickness of the gate dielectric layer is 1.5 nm.
该晶体管按照现有方法进行制备，制备流程简述如下：The transistor is prepared according to the existing method, and the preparation process is briefly described as follows:
1)在硅圆片上用圆形氮化硅硬掩模刻蚀出硅柱；1) Etching silicon pillars with a circular silicon nitride hard mask on the silicon wafer;
2)高温氧化、腐蚀减小硅柱直径达到设定值；热生长栅介质层；2) High-temperature oxidation and corrosion reduce the diameter of the silicon pillar to the set value; thermally grow the gate dielectric layer;
3)淀积多晶硅，硼掺杂形成分裂栅电极1；淀积多晶硅，磷掺杂形成分裂栅电极2；大角度注入磷并退火，制备源漏区3和4；3) Depositing polysilicon, doping boron to form split gate electrode 1; depositing polysilicon, doping phosphorus to form split gate electrode 2; implanting phosphorus at a large angle and annealing to prepare source and drain regions 3 and 4;
4)标准CMOS工艺完成电极制备。4) The standard CMOS process completes the electrode preparation.
下面对该分裂栅结构的纳米线场效应晶体管的性能及影响因素进行检测：The performance and influencing factors of the nanowire field effect transistor with the split gate structure are detected as follows:
1)分裂栅结构对晶体管沟道区电场分布的影响1) The influence of the split gate structure on the electric field distribution in the channel region of the transistor
如图2所示，分裂栅结构的引入使得晶体管沟道区表面电场从原来的单峰值分布变为双峰值分布，新的峰值出现在两种栅材料的分界处。双峰值分布提高了靠近源端沟道区电场分布，从而使得载流子在该区域能够得到足够的加速，整个沟道区载流子平均速度也因此提高。载流子平均速度的增加决定了沟道电流的增大。同时，靠近漏极的电场峰值减小，这减弱了热载流子效应的影响。As shown in Figure 2, the introduction of the split gate structure makes the surface electric field in the channel region of the transistor change from the original single-peak distribution to a double-peak distribution, and a new peak appears at the boundary of the two gate materials. The double-peak distribution improves the electric field distribution in the channel region near the source, so that the carriers can be sufficiently accelerated in this region, and the average carrier velocity in the entire channel region is also increased. The increase of the average carrier velocity determines the increase of the channel current. At the same time, the peak value of the electric field near the drain decreases, which weakens the influence of the hot carrier effect.
2)分裂栅结构对器件电流开关比的影响2) The effect of the split gate structure on the current switching ratio of the device
如图3所示，分裂栅结构增加了器件的开态电流。虽然对传统纳米线场效应晶体管来说，减小栅材料功函数(相当于增大栅极电压)也能增大器件的开态电流，但同时器件的关态电流也显著增大，如图4所示，且增加幅度比开态电流的增加幅度大得多。这导致器件的电流开关比从1010陡然下降到105。因此利用分裂栅结构增加器件的开态电流从而提高器件工作速度的方法效果更好。As shown in Figure 3, the split gate structure increases the on-state current of the device. Although for traditional nanowire field effect transistors, reducing the work function of the gate material (equivalent to increasing the gate voltage) can also increase the on-state current of the device, but at the same time the off-state current of the device also increases significantly, as shown in Fig. 4, and the increase is much larger than that of the on-state current. This results in a steep drop in the device's current-to-switch ratio from 1010 to 105 . Therefore, it is more effective to use the split gate structure to increase the on-state current of the device to improve the working speed of the device.
3)分裂栅结构对晶体管沟道区电势分布的影响3) The effect of the split gate structure on the potential distribution of the transistor channel region
如图5所示，分裂栅结构的引入使得晶体管沟道区表面电势分布出现了一个明显的阶梯转折点，这个转折点正好在两种栅材料的分界处下方。从图上可以看出，当漏极偏压上升时，位于分裂栅电极1下方的沟道区表面电势分布基本不变，增加的漏极偏压主要被分裂栅电极2下方的沟道区所吸收。因此，分裂栅结构提供了屏蔽效应，将分裂栅电极1下方的沟道区屏蔽起来，不受到漏极偏压改变的影响，从而抑制了漏致势垒降低效应。As shown in Figure 5, the introduction of the split gate structure makes the surface potential distribution of the channel region of the transistor have an obvious step turning point, which is just below the boundary between the two gate materials. It can be seen from the figure that when the drain bias voltage increases, the surface potential distribution of the channel region below the split gate electrode 1 basically remains unchanged, and the increased drain bias voltage is mainly caused by the channel region below the split gate electrode 2 absorb. Therefore, the split gate structure provides a shielding effect, shielding the channel region below the split gate electrode 1 from being affected by changes in the drain bias voltage, thereby suppressing the drain-induced barrier lowering effect.
4)不同沟道长度下改变分裂栅结构两部分栅材料的长度对器件漏致势垒降低效应的影响4) The effect of changing the length of the two part gate materials of the split gate structure on the drain-induced barrier lowering effect of the device under different channel lengths
将该晶体管的沟道区的长度改为30-50纳米，间隔为5纳米，半径不变，仍为10nm。对应每个沟道长度的晶体管，分裂栅电极1和2的长度分别为2∶1、1∶1和1∶2。如图6所示，分裂栅结构抑制了漏致势垒降低效应，且靠近漏区4的分裂栅电极2的相对长度越大，漏致势垒降低效应引起的阈值电压减小越小。靠近源区3的分裂栅电极1的相对长度大小对器件开态电流影响较大，因此分裂栅电极1又被称为“控制栅”，调节器件电流大小；分裂栅电极2被称为“屏蔽栅”，提供屏蔽作用。The length of the channel region of the transistor is changed to 30-50 nanometers, the interval is 5 nanometers, and the radius remains unchanged, which is still 10 nm. The lengths of the split gate electrodes 1 and 2 are 2:1, 1:1 and 1:2 for each channel length of the transistor. As shown in FIG. 6 , the split gate structure suppresses the drain-induced barrier lowering effect, and the greater the relative length of the split gate electrode 2 near the drain region 4 , the smaller the decrease in threshold voltage caused by the drain-induced barrier lowering effect. The relative length of the split gate electrode 1 close to the source region 3 has a great influence on the on-state current of the device, so the split gate electrode 1 is also called a "control gate" to adjust the current of the device; the split gate electrode 2 is called a "shielding gate". grid" to provide shielding.
由上可知，本发明提供的分裂栅结构的纳米线场效应晶体管，可以提高传统纳米线场效应晶体管的开态电流，加快器件工作速度，提高电流开关比；同时该器件还可以更有效地抑制短沟道效应，抑制漏致势垒降低效应，改善器件尺寸缩小的性能。As can be seen from the above, the nanowire field effect transistor with split gate structure provided by the present invention can increase the on-state current of the traditional nanowire field effect transistor, accelerate the device operating speed, and improve the current switching ratio; at the same time, the device can also more effectively suppress The short channel effect suppresses the leakage-induced barrier lowering effect and improves the performance of device size reduction.
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