CN102540217A - System for rapidly acquiring GLONASS satellite signals in field programmable gate array (FPGA) - Google Patents

Abstract

The invention provides a system for rapidly acquiring GLONASS satellite signals in a field programmable gate array (FPGA), which filters and down-sampling data after down-conversion, stores the data and samples and stores local codes by utilizing a high-speed clock to drive the whole acquisition circuit. After the data is stored, a control unit controls data output in a data storage and a local code storage, and relevance and accumulation of the data is finished through a partial matching filtering unit. A fast fourier transform (FFT) unit takes charge of carrying out spectrum analysis on the data after partial matched filtering, a threshold is acquired by calculating operation results of FFT, a doppler frequency shift and a code phase corresponding to an output peak value after detection of the peak value are acquired, and then rapid acquisition of the GLONASS signals is finished. The system for rapidly acquiring the GLONASS satellite signals in the FPGA has the advantages of being fast in acquisition speed, few in occupied resource, and suitable for rapid acquisition of the satellite signals by means of a GLONASS receiver under a highly dynamic environment.

Description

A kind of quick capture systems of in FPGA, realizing the GLONASS satellite-signal

Technical field

The present invention relates to the satellite navigation field, particularly a kind of quick capture systems of in FPGA, realizing the GLONASS satellite-signal.

Background technology

In countries such as America and Europes, the research and development of receiver is ripe relatively, and is just constantly perfect aspect pursuit high-performance, diversified receiver, constantly improves at aspects such as searching for, shorten start-up time such as Detection of Weak Signals, signal fast.In recent years, the research of GLONASS constantly heats up.From in Dec, 1996, State Bureau of Surveying and Mapping formally provides the precise ephemeris data of GLONASS to society.Aspect receiver research, mainly concentrate on the requirement how GLONASS satisfies vehicle, weapon, aviation, navigation, personal handhold navigator.It to catching of GLONASS signal one of core technology of GLONASS receiver.To different applications, the acquisition algorithm that has lays particular emphasis on has higher acquisition sensitivity, and what have then lays particular emphasis on the speed of catching.

FPGA grows up on the basis of special-purpose ASIC, and it has overcome the shortcoming of special-purpose ASIC underaction.FPGA has very strong dirigibility, and promptly its inner concrete logic function can dispose as required, is convenient to the modification and the maintenance of circuit.At present, the capacity of FPGA has striden across 1,000,000 gate leves, makes FPGA become one of important selection scheme of resolution system and design.Modern a lot of FPGA are inner integrated PLL, DLL, DSP arithmetic element and a large amount of ram in slice storage blocks.Because the series of characteristics of FPGA, and the demand for development of navigation neceiver technology make it in the navigation neceiver base band signal process, to have obtained to use widely.

For the dynamic application scenario of height, very high to the satellite signal acquisition rate request, it directly has influence on the primary positioning time of receiver, warm start time, indexs such as recapturing unlocked time.It is few that the sliding correlation method of sampling usually takies resource, but must be correlated with to the phase place of each frequency, and search time is long, is not suitable under high dynamic environment, using.The matching wave filter capture method, search speed is fast, but takies very big hardware resource, in FPGA, implements comparatively difficulty.Frequency domain FFT parallel capture method also is a kind of catching method fast, but the FFT that need repeatedly count greatly, the hardware resource that IFFT takies is also many.

Summary of the invention

The present invention provide realize among a kind of FPGA of being based on the GLONASS satellite-signal is carried out quick capture systems, it is few to have the resource of taking, acquisition speed is fast, is easy to advantages such as realization, is applicable on the carrier of high-speed motion the GLONASS signal is caught fast.

In order to realize the foregoing invention purpose, the present invention provides following technical scheme:

A kind of quick capture systems of in FPGA, realizing the GLONASS satellite-signal comprises down-converter unit, the FIR filter cell; Sampling and data storage cell; Part matched filtering unit, FFT unit, peak detection unit; Local code generator unit, local code sampling storage unit and acquisition control unit;

Said down-converter unit is used for digital medium-frequency signal is carried out down-converted, obtains I, the data of Q two-way zero intermediate frequency;

Said FIR filter cell is used for I, and the data of Q two-way zero intermediate frequency are carried out filtering, filtering out-of-band noise and high-frequency signal;

Said sampling and data storage cell carry out down-sampling to data-signal, and data are stored, and the data sampling time is 3ms;

Said part matched filtering unit, the coherent accumulation of completion local code and zero intermediate frequency data;

Said FFT unit is accomplished the data after the matched filtering is carried out spectrum analysis;

Said peak detection unit is used to accomplish to catching the detection of peak value, and judges whether acquisition success;

Said local code generator unit, the cycle 1ms bit rate that produces GLONASS is the PR ranging code of 511kbps;

Said local code sampling storage unit is used for local code is sampled, and the sampled data of local code is stored, and the sampling time is 2ms;

Said acquisition control unit is used to produce the timing control signal of the whole trapping module work of control.

Wherein, described down-converter unit adopts high-frequency clock to produce local carrier, and under high-frequency clock drives, accomplishes down coversion.

Wherein, described data storage cell uses the two-stage memory construction, and the first order after first order data storage is full, all exports the data in the first order buffer memory to second level primary memory as metadata cache again.

Wherein, described matched filtering unit uses the shift memory structure to realize the relative slip between zero intermediate frequency sampled data and the local code sampled data, and uses many group correlators to accomplish the coherent accumulation of data fast.

Wherein, described peak detection unit is added up through all operation results to prime FFT, accomplishes thresholding and sets, and peak value detects, and calculates the frequency shift value of pairing Doppler shift of this peak value and local code phase place.

Wherein, described acquisition control unit produces the necessary control signal after catching startup command arrival, coordinate other and respectively catch orderly work.

Wherein, this peak detection unit also comprises the noise power statistics function, in order to produce adaptive detection threshold, can adjust threshold value automatically according to the noise size.

Said local code generator unit comprises a shift register of being made up of 9 registers, is the PR ranging code of 511kbps in order to the cycle 1ms bit rate that produces GLONASS;

Said local code sampling storage unit is used for local code is sampled, and the sampled data of local code is stored, and the sampling time is 2ms.

Said acquisition control unit is used to produce the timing control signal of the whole trapping module work of control;

Can find out from technique scheme; The present invention is through carrying out a 3ms sampling to intermediate frequency data; Read the intermediate frequency data and the local code data of storage through high-frequency clock, use many group correlators to accomplish the related operation between intermediate frequency data and the local code fast then, realize the relative slip between intermediate frequency data and the local code through using shift memory; Use FFT to find out the Doppler frequency-shift of intermediate frequency data, reach the purpose of catching the GLONASS satellite-signal fast with respect to local carrier.

To through the frequency of the The data 1.022MHz behind the FIR filter filtering data being sampled, each sampled data is represented with 4bit, and then storage among the present invention.Respectively store 3ms for I, Q two paths of signals, use the FPGA on-chip memory of 24576bit approximately.Correlator also only needs 32 groups.Therefore the FPGA resource that takies is less.

Description of drawings

Fig. 1 catches the overall plan schematic diagram fast for the GLONASS that the embodiment of the invention provides;

The local code generator unit schematic diagram that Fig. 2 provides for the embodiment of the invention;

The part matched filtering unit schematic diagram that Fig. 3 provides for the embodiment of the invention;

The peak detection unit schematic diagram that Fig. 4 provides for the embodiment of the invention.

Embodiment

Technical scheme is for a better understanding of the present invention described embodiment provided by the invention in detail below in conjunction with accompanying drawing.

The embodiment of the invention provides a kind of and based on what realize among the FPGA the GLONASS satellite-signal is carried out quick capture systems.This capture systems is used for GLONASS DVB Base-Band Processing; Can handle the digital medium-frequency signal after the A/D conversion; Calculate the Doppler shift of this intermediate-freuqncy signal fast with respect to local carrier, and with respect to the code phase offset of local code generator.

One of its core content is sampling and data storage cell and part matched filtering unit, through special data storage method and data move operation, realizes sliding relatively fast between data and the local code.

Like Fig. 1, this harvesting policy is a kind of capture systems based on FFT.What GLONASS adopted is the FDMA modulation system, and what every satellite used is identical ranging code, is modulated on the different frequencies.The local gap sign indicating number that localcode generator unit 108 produces all is identical for every satellite.The frequency that only needs to change the local carrier in the down-converter unit 101 of catching for different satellites gets final product.Afteracquisition control unit 107 receives and catches startup command; Root need be caught defends asterisk; The local carrier frequency of down-converter unit 101 is set; The digital intermediate frequency of input is realized down coversion after multiplying each other with local carrier, the data after 102 pairs of down coversions of FIR filter unit are carried out LPF, filtering high frequency and out-of-band noise signal then.It is the local ranging code C sign indicating number of 511kbps that localcode generator unit 108 produces bit rate, sends into local code sampling storage unit 109.Serial/parallel conversion after in local codesampling storage unit 109, earlier local code being sampled with the speed 1.022MHz that doubles local code, per 32 sampled values are stored in the storer as a word successively, stop sampling operation behind 64 words of sampling altogether.

Sampling anddata storage cell 103 start with local codesampling storage unit 109 simultaneously, and total sampled data memory space is 3ms, and whereindata storage cell 103 is stored 1ms, shift memory storage 2ms in the part matched filtering unit 104.Data storage cell 103 adopts the two-stage storer; The first order is as metadata cache; After second level storer is filled with, start first order storer immediately, simultaneously the data in the storer of the second level are all outputed in the shift memory in the part matched filtering unit 104.After the data that shift memory in part matchedfiltering unit 104 has been stored data and the 3ms of 2ms deposited the second level storer in thedata storage cell 103 in, data sampling stopped.

After the data acquisition in 103 and 109 stops; Part matchedfiltering unit 104 begins to carry out the related operation between local code and the sampled data; Each clock period is accomplished the coherent accumulation of I, each 32 sampling number certificate of Q two paths of data;Data FFT unit 105 after adding up carries out 64 FFT computings, and the FFT unit adopts The pipeline design, and per 64 clock period are accomplished the relevant computing of 1 code phase.The operation result of FFT is sent intopeak detection unit 106 at last, carries out peak value and detects and catch result's judgement.

The present invention implements also to provide the circuit theory of a kind of local ranging code and code phase generation thereof, is applied in the localcode generator unit 108, and like Fig. 2, this circuit theory comprises with the lower part:

201, the counter of a 0-510, count value is represented the phase place of local ranging code.Reach asserts signal of output in 510 o'clock at counting, all d type flip flops in 202 are set to " 1 ";

202, a shift register group of being made up of 9 d type flip flops is used to produce local ranging code.

The present invention implements also to provide and produces the method for sliding relatively between a kind of Rapid Realization data and the local code, is applied in part matchedfiltering unit 104, and like Fig. 3, this method mainly comprises with the lower part:

301, selector unit, the input data that are used to select shift memory unit 302 are from sampling anddata storage cell 103 extracts or extract from the output of selecting shift memory unit 302 self;

302, shift memory unit is used to realize moving of data, has 32 tap output datas;

303, multiplier group unit is used for local code and shift memory unit 302 output datas multiply each other;

304, adder unit is used for the output of multiplier group unit 303 is realized the phase add operation through multistage totalizer.

The present invention implements the method that a kind of peak value detects and detection threshold produces also is provided, and like Fig. 4, this method mainly comprises with the lower part:

401, maximum detection unit is used to detect the maximal value of data;

402, accumulator element adds up all data;

403, thresholding generation unit is used for the data ofaccumulator element 402 output are carried out the convergent-divergent of some ratios, obtains suitable detection threshold value;

404, comparing unit compares the data ofmaximum detection unit 401 withaccumulator element 403 outputs, to determine whether acquisition success;

405, code phase counting unit is used to write down the corresponding code phase of current FFT data;

406, frequency storage unit is preserved the corresponding Doppler shift of maximal value in themaximum detection unit 401;

407, code phase storage unit is preserved the input intermediate-freuqncy signal of the maximal value correspondence in themaximum detection unit 401 and the relocatable code phase pushing figure between the local code.

More than to realizing among a kind of FPGA that the embodiment of the invention provided that the quick capture systems of GLONASS satellite-signal under high dynamic environment carried out detailed introduction; Thought according to the embodiment of the invention; Part all can change on embodiment and range of application; In sum, this description should not be construed as limitation of the present invention.

Claims (6)

1. quick capture systems of in FPGA, realizing the GLONASS satellite-signal, it is characterized in that: described system comprises down-converter unit, the FIR filter cell; Sampling and data storage cell; Part matched filtering unit, FFT unit, peak detection unit; Local code generator unit, local code sampling storage unit and acquisition control unit;

Said down-converter unit is used for digital medium-frequency signal is carried out down-converted, obtains I, the data of Q two-way zero intermediate frequency;

Said FIR filter cell is used for I, and the data of Q two-way zero intermediate frequency are carried out filtering, filtering out-of-band noise and high-frequency signal;

Said sampling and data storage cell carry out down-sampling to data-signal, and data are stored, and the data sampling time is 3ms;

Said part matched filtering unit, the coherent accumulation of completion local code and zero intermediate frequency data;

Said FFT unit is accomplished the data after the matched filtering is carried out spectrum analysis;

Said peak detection unit is used to accomplish to catching the detection of peak value, and judges whether acquisition success;

Said local code generator unit, the cycle 1ms bit rate that produces GLONASS is the PR ranging code of 511kbps;

Said local code sampling storage unit is used for local code is sampled, and the sampled data of local code is stored, and the sampling time is 2ms;

Said acquisition control unit is used to produce the timing control signal of the whole trapping module work of control.

2. a kind of quick capture systems of in FPGA, realizing the GLONASS satellite-signal according to claim 1 is characterized in that described down-converter unit adopts high-frequency clock to produce local carrier, and under high-frequency clock drives, accomplishes down coversion.

3. a kind of quick capture systems of in FPGA, realizing the GLONASS satellite-signal according to claim 1; It is characterized in that; Described data storage cell uses the two-stage memory construction; The first order after first order data storage is full, all exports the data in the first order buffer memory to second level primary memory as metadata cache again.

4. a kind of quick capture systems of in FPGA, realizing the GLONASS satellite-signal according to claim 1; It is characterized in that; Described matched filtering unit uses the shift memory structure to realize the relative slip between zero intermediate frequency sampled data and the local code sampled data, and uses many group correlators to accomplish the coherent accumulation of data fast.

5. a kind of quick capture systems of in FPGA, realizing the GLONASS satellite-signal according to claim 1; It is characterized in that; Described peak detection unit is added up through all operation results to prime FFT; The completion thresholding is set, and peak value detects, and calculates the frequency shift value of pairing Doppler shift of this peak value and local code phase place.

6. a kind of quick capture systems of in FPGA, realizing the GLONASS satellite-signal according to claim 1; It is characterized in that; Described acquisition control unit produces the necessary control signal after catching startup command arrival, coordinate other and respectively catch orderly work.

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