CN102521190A - Hierarchical bus system applied to real-time data processing - Google Patents
Hierarchical bus system applied to real-time data processingDownload PDFInfo
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明涉及集成电路中片上系统技术领域，尤其涉及一种片上系统的应用于实时数据处理的多级总线系统。The invention relates to the technical field of on-chip systems in integrated circuits, in particular to a multi-level bus system for real-time data processing of the on-chip system.
背景技术Background technique
片上系统(System on Chip)是集成电路技术发展的必然趋势，随着半导体特征尺寸的缩小，芯片集成度的提高，越来越多的功能被集成到一个芯片中。芯片功能不断的丰富，集成的IP核(Intellectual Property，IP)不断的增加，使得片上系统的架构也越来越复杂。特别是在实时数据处理领域，设计具有实时性和高数据带宽的总线系统是当前的研究热点。System on Chip (System on Chip) is an inevitable trend in the development of integrated circuit technology. With the reduction of semiconductor feature size and the improvement of chip integration, more and more functions are integrated into a chip. The continuous enrichment of chip functions and the continuous increase of integrated IP cores (Intellectual Property, IP) make the architecture of the system on a chip more and more complex. Especially in the field of real-time data processing, designing a bus system with real-time and high data bandwidth is a current research hotspot.
在实时数据处理领域，总线系统要尽可能简单，因为片上系统的互联总线的拓扑结构不能过于复杂，以致影响响应的实时性。其次，总线系统的拓扑结构要能反映各互联模块在系统中的地位，如果所有的互联模块在总线系统中均处于同一地位，则将导致重要模块无法发起请求，而低速模块占有总线而无总线请求的情况。最后，总线系统要有较大的灵活性，因为片上系统的目标是以最小的物理代价来实现各模块的互联，总线系统需要在不同的应用场景下均可以满足要求。片上系统的总线系统虽然具备以上特有要求，但与个人电脑中的总线系统在功能和拓扑结构上有很多相同点，因此个人电脑中的总线系统的发展可以为片上系统的总线系统提供借鉴。In the field of real-time data processing, the bus system should be as simple as possible, because the topology of the interconnection bus of the system on chip cannot be too complex, so as to affect the real-time response. Secondly, the topology of the bus system should reflect the status of each interconnected module in the system. If all the interconnected modules are in the same position in the bus system, important modules will not be able to initiate requests, while low-speed modules occupy the bus without a bus. The situation of the request. Finally, the bus system must have greater flexibility, because the goal of the system on a chip is to realize the interconnection of various modules with the minimum physical cost, and the bus system needs to meet the requirements in different application scenarios. Although the bus system of the system on a chip has the above-mentioned special requirements, it has many similarities with the bus system in the personal computer in terms of function and topology. Therefore, the development of the bus system in the personal computer can provide a reference for the bus system of the system on a chip.
基于以上原则，当前比较流行的总线系统是单总线系统。如图1所示，采用一条总线连接所有的接口设备，造成各模块的运行速度无法匹配，总线的带宽由于木桶效应会影响实时处理模块的数据吞吐速度。图2为采用嵌入式处理器的总线系统，其具有较高的灵活性，处理速度较快的数据处理模块可以独立于总线以较高的速度运行，总线和数据处理模块的速度匹配通过同步逻辑来完成。该系统较好的解决了运行速度不一致的模块之间运行速度失配问题，但是该总线系统不具有扩展性，当模块增多时，同步逻辑难以在各模块的运行速度上取得平衡，从而导致系统的性能随模块的增加而显著降低。Based on the above principles, the current popular bus system is the single bus system. As shown in Figure 1, a bus is used to connect all the interface devices, resulting in that the running speed of each module cannot match, and the bandwidth of the bus will affect the data throughput speed of the real-time processing module due to the barrel effect. Figure 2 is a bus system using an embedded processor, which has high flexibility. The data processing module with a faster processing speed can run at a higher speed independently of the bus. The speed matching of the bus and the data processing module is passed through the synchronization logic. To be done. This system better solves the problem of running speed mismatch between modules with inconsistent running speeds, but the bus system is not scalable. When the number of modules increases, it is difficult for the synchronization logic to balance the running speeds of each module, resulting in system The performance of the module decreases significantly with the increase of modules.
综上所述，当前的应用于实时数据处理的总线系统在扩展性方面和系统性能方面还存在问题。To sum up, the current bus system applied to real-time data processing still has problems in terms of scalability and system performance.
发明内容Contents of the invention
(一)要解决的技术问题(1) Technical problems to be solved
本发明所要解决的技术问题是如何使总线系统的扩展更具灵活性，同时解决不同模块之间的性能失配问题。The technical problem to be solved by the invention is how to make the expansion of the bus system more flexible and at the same time solve the problem of performance mismatch between different modules.
(二)技术方案(2) Technical solutions
本发明的多级总线系统包括实时高速总线、非实时高速总线、非实时低速总线、高速存储器、实时总线输入输出模块、实时总线数据处理模块、非实时高速总线输入输出模块、非实时低速总线输入输出模块、高速总线互联模块和低速总线互联模块；其中实时高速总线，用于实时大数据量的传送和处理；非实时高速总线，用于非实时性的大数据量传送和处理；非实时低速总线，用于小数据量的传送和处理；高速存储器，用于满足总线系统上各模块的数据存储要求；实时高速总线输入输出模块，用于控制高速输入输出口的接收和发送，并进行协议解析，数据缓冲，实现跨时钟域的数据同步；实时高速总线数据处理模块，用于对输入的数据进行特征提取，编码格式转换，特效呈现和噪声过滤，完成数据的运算密集型处理；非实时高速总线输入输出模块，用于与实时高速总线输入输出模块配合，进行非实时数据的高速传送；非实时低速总线输入输出模块，用于小数据量的低速传送；高速总线互联模块，用来完成非实时高速总线和实时高速总线之间的数据交互；低速总线互联模块，用来完成非实时低速总线和非实时高速总线之间的数据交互。The multilevel bus system of the present invention comprises real-time high-speed bus, non-real-time high-speed bus, non-real-time low-speed bus, high-speed memory, real-time bus input and output module, real-time bus data processing module, non-real-time high-speed bus input and output module, non-real-time low-speed bus input Output module, high-speed bus interconnection module and low-speed bus interconnection module; Among them, real-time high-speed bus is used for real-time large data transmission and processing; non-real-time high-speed bus is used for non-real-time large data transmission and processing; non-real-time low-speed Bus, used for transmission and processing of small data volume; high-speed memory, used to meet the data storage requirements of each module on the bus system; real-time high-speed bus input and output module, used to control the receiving and sending of high-speed input and output ports, and perform protocol Analysis, data buffering, realizing data synchronization across clock domains; real-time high-speed bus data processing module, used for feature extraction of input data, encoding format conversion, special effect rendering and noise filtering, to complete the calculation-intensive processing of data; non-real-time The high-speed bus input and output module is used to cooperate with the real-time high-speed bus input and output module for high-speed transmission of non-real-time data; the non-real-time low-speed bus input and output module is used for low-speed transmission of small data volumes; the high-speed bus interconnection module is used to complete The data interaction between the non-real-time high-speed bus and the real-time high-speed bus; the low-speed bus interconnection module is used to complete the data interaction between the non-real-time low-speed bus and the non-real-time high-speed bus.
(三)有益效果(3) Beneficial effects
本发明提供了一种新的实时数据处理系统总线系统，可以实现多模块实时处理的同时，支持低速设备的集成，并保证系统具有灵活的扩展性，同时不牺牲系统的整体性能。The invention provides a new real-time data processing system bus system, which can realize multi-module real-time processing, support the integration of low-speed devices, and ensure the flexible scalability of the system without sacrificing the overall performance of the system.
附图说明Description of drawings
图1为传统的实时数据处理系统总线系统的示意图；Fig. 1 is the schematic diagram of traditional real-time data processing system bus system;
图2为传统的基于嵌入式处理器的总线系统的示意图；Fig. 2 is the schematic diagram of the bus system based on traditional embedded processor;
图3为本发明的一个实施例的多级总线系统的示意图；Fig. 3 is the schematic diagram of the multistage bus system of an embodiment of the present invention;
图4为对模块数目进行扩展的多级总线系统的实施例示意图；Fig. 4 is the schematic diagram of the embodiment of the multilevel bus system that the number of modules is expanded;
图5为对总线级数进行扩展的多级总线系统的实施例示意图。Fig. 5 is a schematic diagram of an embodiment of a multi-level bus system that expands the number of bus levels.
具体实施方式Detailed ways
为使本发明的目的、技术方案和有点更加清晰，下面将结合本发明中的附图，对本发明中的技术方案进行详细、完整的描述。In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the present invention will be described in detail and completely below in conjunction with the accompanying drawings in the present invention.
本发明提供了一种多级总线系统，包括：实时高速总线，用于实时大数据量的传送和处理；非实时高速总线，用于非实时性的大数据量传送和处理；非实时低速总线，用于小数据量的传送和处理；以及高速存储器、实时总线输入输出模块、实时总线数据处理模块、非实时高速总线输入输出模块、非实时低速总线输入输出模块、高速总线互联模块和低速总线互联模块。该多级总线系统可以有效平衡各请求发起模块的总线占用时间，实现对大数据集进行实时传送和处理。The invention provides a multi-level bus system, including: a real-time high-speed bus, used for the transmission and processing of large amounts of real-time data; a non-real-time high-speed bus, used for the transmission and processing of non-real-time large amounts of data; a non-real-time low-speed bus , for transmission and processing of small amounts of data; and high-speed memory, real-time bus input and output modules, real-time bus data processing modules, non-real-time high-speed bus input and output modules, non-real-time low-speed bus input and output modules, high-speed bus interconnection modules and low-speed buses interconnected modules. The multi-level bus system can effectively balance the bus occupation time of each request initiating module, and realize real-time transmission and processing of large data sets.
实时高速总线，是实时响应且高数据带宽的总线，用于实现对多模块的仲裁，并提供不同时钟域的数据同步和不同位宽的数据对齐；Real-time high-speed bus is a bus with real-time response and high data bandwidth, which is used to realize the arbitration of multiple modules, and provide data synchronization of different clock domains and data alignment of different bit widths;
非实时高速总线，是提供高数据带宽的总线，允许对各模块发起的操作延迟响应，以进行操作调度和重排序；The non-real-time high-speed bus is a bus that provides high data bandwidth, allowing delayed response to operations initiated by each module for operation scheduling and reordering;
高速存储器，是大容量的数据存储体，用于满足总线系统上各模块的数据存储要求，并工作在实时总线时钟域内；High-speed memory is a large-capacity data storage body, used to meet the data storage requirements of each module on the bus system, and work in the real-time bus clock domain;
实时高速总线输入输出模块，控制高速输入输出口的接收和发送，并进行协议解析，数据缓冲，实现跨时钟域的数据同步；The real-time high-speed bus input and output module controls the receiving and sending of high-speed input and output ports, and performs protocol analysis and data buffering to realize data synchronization across clock domains;
实时高速总线数据处理模块，对输入的数据进行特征提取，编码格式转换，特效呈现和噪声过滤，完成数据的运算密集型处理；The real-time high-speed bus data processing module performs feature extraction, encoding format conversion, special effect rendering and noise filtering on the input data, and completes the calculation-intensive processing of data;
非实时高速总线输入输出模块，与实时高速总线输入输出模块配合，进行非实时数据的高速传送；The non-real-time high-speed bus input and output module cooperates with the real-time high-speed bus input and output module to perform high-speed transmission of non-real-time data;
非实时低速总线输入输出模块，用于小数据量的低速传送；Non-real-time low-speed bus input and output module, used for low-speed transmission of small data volume;
高速总线互联模块，用于非实时高速总线和实时高速总线之间的数据交互；High-speed bus interconnection module, used for data interaction between non-real-time high-speed bus and real-time high-speed bus;
低速总线互联模块，用于非实时低速总线和非实时高速总线之间的数据交互。The low-speed bus interconnection module is used for data interaction between the non-real-time low-speed bus and the non-real-time high-speed bus.
图3为本发明的应用于实时数据处理的多级总线系统的一个具体实施例，该多级总线系统包括实时高速总线、非实时高速总线、非实时低速总线、嵌入式处理器、高速存储器、实时高速总线输入输出模块、后处理模块、以太网模块、非实时低速总线输入输出模块、低速总线互联模块和高速总线互联模块。Fig. 3 is a specific embodiment of the multilevel bus system that is applied to real-time data processing of the present invention, and this multilevel bus system comprises real-time high-speed bus, non-real-time high-speed bus, non-real-time low-speed bus, embedded processor, high-speed memory, Real-time high-speed bus input and output module, post-processing module, Ethernet module, non-real-time low-speed bus input and output module, low-speed bus interconnection module and high-speed bus interconnection module.
实时高速总线输入输出模块、实时总线数据处理模块和高速存储器通过实时高速总线接口与实时高速总线相连；嵌入式处理器、以太网模块通过非实时高速总线接口与非实时高速总线相连；非实时低速总线输入输出模块通过非实时低速总线接口与非实时低速总线相连；非实时低速总线通过低速总线互联模块与非实时高速总线相连，非实时高速总线通过高速总线互联模块与实时高速总线相连。Real-time high-speed bus input and output module, real-time bus data processing module and high-speed memory are connected with real-time high-speed bus through real-time high-speed bus interface; embedded processor and Ethernet module are connected with non-real-time high-speed bus through non-real-time high-speed bus interface; non-real-time low-speed The bus input and output module is connected to the non-real-time low-speed bus through the non-real-time low-speed bus interface; the non-real-time low-speed bus is connected to the non-real-time high-speed bus through the low-speed bus interconnection module, and the non-real-time high-speed bus is connected to the real-time high-speed bus through the high-speed bus interconnection module.
实时高速总线与有实时性要求的设备相连，用于完成对连接到实时高速总线上设备的请求仲裁并响应其读写请求，将读写请求发送到高速存储器。实时高速总线可以是AXI总线，但本发明并不限于此，也可以是其它具备实时性响应的总线。如果是其它总线实现，则连接到实时高速总线上的设备接口需要做相应转换，将各设备的AXI接口转换为其它总线接口。该适应性变换的实现可以是与设备集成在一起的软核形式，也可以是一个独立的实体部件。The real-time high-speed bus is connected to devices with real-time requirements, and is used to complete the request arbitration of the devices connected to the real-time high-speed bus, respond to its read and write requests, and send the read and write requests to the high-speed memory. The real-time high-speed bus may be an AXI bus, but the present invention is not limited thereto, and may also be other buses with real-time response. If it is implemented by other buses, the device interfaces connected to the real-time high-speed bus need to be converted accordingly, and the AXI interfaces of each device are converted to other bus interfaces. The realization of the adaptive transformation can be in the form of a soft core integrated with the device, or it can be an independent physical component.
非实时高速总线与数据吞吐量大并且实时性要求不高的设备相连，用于完成对连接到非实时高速总线上设备的请求仲裁并响应其读写请求，将读写请求通过高速总线互联模块发送到实时高速总线，经实时高速总线最终发送到高速存储器。非实时高速总线可以是AXI总线(工作频率低于实时高速总线)，但本发明并不限于此，也可以是其它具备支持大数据吞吐量的总线。如果是其它总线实现，则连接到非实时高速总线上的设备接口需要做相应转换，将各设备的AXI接口转换为其它总线接口。该适应性变换的实现可以是与设备集成在一起的软核形式，也可以是一个独立的实体部件。The non-real-time high-speed bus is connected to devices with large data throughput and low real-time requirements, and is used to complete the request arbitration for devices connected to the non-real-time high-speed bus and respond to its read and write requests, and connect the read and write requests through the high-speed bus interconnection module Send to the real-time high-speed bus, and finally send to the high-speed memory through the real-time high-speed bus. The non-real-time high-speed bus may be an AXI bus (working frequency is lower than that of a real-time high-speed bus), but the present invention is not limited thereto, and may also be other buses capable of supporting large data throughput. If it is implemented by other buses, the device interfaces connected to the non-real-time high-speed bus need to be converted accordingly, and the AXI interfaces of each device are converted to other bus interfaces. The realization of the adaptive transformation can be in the form of a soft core integrated with the device, or it can be an independent physical component.
非实时低速总线与数据吞吐量小且实时性要求不高的设备相连，用于完成对连接到非实时低速总线上设备的请求仲裁并响应其读写请求，将读写请求通过低速总线互联模块发送到非实时高速总线，经非实时高速总线发送到嵌入式处理器，或经高速总线互联模块发送到实时高速总线，经实时高速总线发送到高速存储器。非实时低速总线可以是AHB总线，但本发明并不限于此，也可以是其它具备支持小数据吞吐量的总线。如果是其它总线实现，则连接到非实时高速总线上的设备接口需要做相应转换，将各设备的AHB接口转换为其它总线接口。该适应性变换的实现可以是与设备集成在一起的软核形式，也可以是一个独立的实体部件。The non-real-time low-speed bus is connected to devices with small data throughput and low real-time requirements, and is used to complete the request arbitration for devices connected to the non-real-time low-speed bus and respond to their read and write requests, and connect the read and write requests through the low-speed bus interconnection module Send to the non-real-time high-speed bus, send to the embedded processor through the non-real-time high-speed bus, or send to the real-time high-speed bus through the high-speed bus interconnection module, and send to the high-speed memory through the real-time high-speed bus. The non-real-time low-speed bus may be an AHB bus, but the present invention is not limited thereto, and may also be other buses capable of supporting small data throughput. If it is implemented by other buses, the device interfaces connected to the non-real-time high-speed bus need to be converted accordingly, and the AHB interfaces of each device are converted to other bus interfaces. The realization of the adaptive transformation can be in the form of a soft core integrated with the device, or it can be an independent physical component.
嵌入式处理器与非实时高速总线相连，用于对实时高速总线输入输出模块进行工作模式的配置和启动控制，配置后处理模块的滤波系数。并且根据用户的要求，调节后处理的处理模式，控制以太网的启动，响应低速总线互联模块的输入输出请求。嵌入式处理器可以是兼容ARM和/或MIPS指令集的嵌入式处理器，也可以是其它指令集的嵌入式处理器。The embedded processor is connected with the non-real-time high-speed bus, and is used for configuring and starting control of the working mode of the real-time high-speed bus input and output modules, and configuring the filter coefficient of the post-processing module. And according to the user's requirements, adjust the processing mode of the post-processing, control the start of the Ethernet, and respond to the input and output requests of the low-speed bus interconnection module. The embedded processor may be an embedded processor compatible with ARM and/or MIPS instruction sets, or an embedded processor with other instruction sets.
实时高速总线输入和输出模块，一端与实时高速总线相连，另一端与一标准接口相连(图中未示出)，用于接收从该标准接口传送来的视频和音频信息，并实时的写入到高速存储器中。并且，根据嵌入式处理器的配置参数，实时高速总线输入输出模块读取存储在高速存储器中的原始视频及音频或经过后处理模块处理过的优化视频和音频，以相应的分辨率和刷新率发送到标准接口的发送端。该实时高速总线输入和输出模块可以是支持HDMI标准的输入输出模块，与之相连的标准接口可以是HDMI接口，但本发明并不限于此，也可以是DVI标准接口或其它视频标准接口。The real-time high-speed bus input and output module, one end is connected to the real-time high-speed bus, and the other end is connected to a standard interface (not shown in the figure), used to receive video and audio information transmitted from the standard interface, and write in real time to high-speed memory. And, according to the configuration parameters of the embedded processor, the real-time high-speed bus input and output module reads the original video and audio stored in the high-speed memory or the optimized video and audio processed by the post-processing module, and uses the corresponding resolution and refresh rate Send to the sender of the standard interface. The real-time high-speed bus input and output module can be an input and output module supporting the HDMI standard, and the standard interface connected thereto can be an HDMI interface, but the present invention is not limited thereto, and can also be a DVI standard interface or other video standard interfaces.
高速存储器可以是DDR3 SDRAM，也可以是DDR2 SDRAM等其它类型的高速存储器，用于存储输入的视频信息和处理后的视频信息等。The high-speed memory can be DDR3 SDRAM or other types of high-speed memory such as DDR2 SDRAM, which are used to store input video information and processed video information.
后处理模块是实时高速总线数据处理模块，其与实时高速总线相连，用于读取存储在高速存储器中的视频图像数据，根据视频图像信息，对视频图像数据进行隔行扫描与逐行扫描间的转化；根据嵌入式处理器配置的滤波系数，启动相应滤波器对视频图像数据进行实时处理，以优化视频或特效生成；根据后处理工作模式，决策是否对视频图像数据进行色度空间的转换；将最终的处理后视频图像数据写回到高速存储器中。后处理模块可以是芯片形式的实现，也可以是软核的形式实现。The post-processing module is a real-time high-speed bus data processing module, which is connected with the real-time high-speed bus and used to read the video image data stored in the high-speed memory, and perform interlaced scanning and progressive scanning on the video image data according to the video image information. Transformation; according to the filter coefficient configured by the embedded processor, start the corresponding filter to process the video image data in real time to optimize the generation of video or special effects; according to the post-processing working mode, decide whether to convert the video image data to the chromaticity space; Write the final processed video image data back into the high-speed memory. The post-processing module can be implemented in the form of a chip or in the form of a soft core.
以太网模块与非实时高速总线相连，是一种非实时高速总线输入输出模块，用来完成本发明的多级总线系统与远程用户端(图3中未示出)的交互，远程用户可以通过以太网远程向以太网模块发送各种指令，控制图3所述本发明的多级总线系统的启动以及工作模式，并将该系统的响应或处理结果通过以太网返回到远程用户端。该以太网模块可以是千兆以太网模块，或者万兆以太网模块。Ethernet module is connected with non-real-time high-speed bus, is a kind of non-real-time high-speed bus input and output module, is used for completing the interaction of multilevel bus system of the present invention and remote client (not shown in Fig. 3), remote user can pass through The Ethernet remotely sends various instructions to the Ethernet module to control the start and working mode of the multi-level bus system of the present invention as shown in Figure 3, and returns the response or processing results of the system to the remote client through the Ethernet. The Ethernet module may be a Gigabit Ethernet module or a 10 Gigabit Ethernet module.
非实时低速总线输入输出模块可以是AHB、GPIO(通用输入输出)和UART(通用异步接收机)，用来实现图3所述系统的系统调试和外部中断。The non-real-time low-speed bus input and output modules can be AHB, GPIO (general-purpose input and output) and UART (universal asynchronous receiver), which are used to realize system debugging and external interrupt of the system described in FIG. 3 .
低速总线互联模块一端与非实时低速总线相连，另一端与非实时高速总线相连，用来完成非实时低速总线和非实时高速总线之间的数据交互。该低速总线互联模块可以是完成工作在不同工作频率的相同总线协议之间的互联，也可以是完成不同总线协议之间的互联。低速总线互连模块可以通过配置寄存器实现软件可编程，以适应不同应用场景。One end of the low-speed bus interconnection module is connected to the non-real-time low-speed bus, and the other end is connected to the non-real-time high-speed bus to complete data interaction between the non-real-time low-speed bus and the non-real-time high-speed bus. The low-speed bus interconnection module can complete the interconnection between the same bus protocols working at different operating frequencies, or complete the interconnection between different bus protocols. The low-speed bus interconnection module can realize software programming through configuration registers to adapt to different application scenarios.
高速总线互联模块一端与非实时高速总线相连，另一端与实时高速总线相连，用来完成非实时高速总线和实时高速总线之间的数据交互。该低速总线互联模块可以是完成工作在不同工作频率的相同总线协议之间的互联，也可以是完成不同总线协议之间的互联。高速总线互连模块可以通过配置寄存器实现软件可编程，以适应不同应用场景。One end of the high-speed bus interconnection module is connected to the non-real-time high-speed bus, and the other end is connected to the real-time high-speed bus to complete the data interaction between the non-real-time high-speed bus and the real-time high-speed bus. The low-speed bus interconnection module can complete the interconnection between the same bus protocols working at different operating frequencies, or complete the interconnection between different bus protocols. The high-speed bus interconnection module can realize software programming through configuration registers to adapt to different application scenarios.
作为本发明的一个优选实施例，在基于图3所示的多级总线系统中，实时高速总线AXI-1(为与非实时高速总线AXI区分，加标号-1)、HDMI接收和发送模块、后处理模块工作在150MHz，高速存储器为DDR3SDRAM工作在300MHz，非实时高速总线AXI-2(为与实时高速总线AXI区分，加标号-2)、嵌入式处理器、以太网模块工作在125MHz，非实时低速总线AHB、GPIO和UART模块工作在75MHz。As a preferred embodiment of the present invention, in the multilevel bus system based on Fig. 3, real-time high-speed bus AXI-1 (in order to distinguish with non-real-time high-speed bus AXI, plus label-1), HDMI receiving and sending module, The post-processing module works at 150MHz, the high-speed memory is DDR3SDRAM at 300MHz, the non-real-time high-speed bus AXI-2 (in order to distinguish it from the real-time high-speed bus AXI, add the label -2), the embedded processor, and the Ethernet module work at 125MHz, and the non-real-time high-speed bus AXI-2 Real-time low-speed bus AHB, GPIO and UART modules work at 75MHz.
图4显示了本发明的另一实施例的示意图，其是基于图3的多级总线系统所连的模块数目进行扩展的多级总线系统。该多级总线系统包括每级总线所连的处理模块、扩展处理模块1、扩展处理模块2、…、扩展处理模块n等。相对与图3所示的多级总线系统，该扩展多级总线系统扩展了该系统每一级总线的连接模块数目，使得具有同等处理速度和带宽需求的多个处理模块可以集成到同一级总线中。例如在实时高速总线上，除图3所示的实施方式外，还可以集成DVI的输入和输出模块，VGA的输入和输出模块等，使得多级总线系统在总线级数不变的情况下，集成更多的功能模块。FIG. 4 shows a schematic diagram of another embodiment of the present invention, which is a multilevel bus system expanded based on the number of modules connected to the multilevel bus system in FIG. 3 . The multilevel bus system includes a processing module connected to each level of bus, an extended processing module 1, an extended processing module 2, . . . , an extended processing module n, and the like. Compared with the multi-level bus system shown in Figure 3, the extended multi-level bus system expands the number of connection modules of each level bus in the system, so that multiple processing modules with the same processing speed and bandwidth requirements can be integrated into the same level bus middle. For example, on the real-time high-speed bus, in addition to the implementation shown in Figure 3, the input and output modules of DVI, the input and output modules of VGA, etc. can also be integrated, so that the multi-level bus system can Integrate more functional modules.
图5显示了本发明的又一实施例，其是基于图3的多级总线系统的级数进行扩展的多级总线系统。该多级总线系统包括实时高速总线、非实时高速总线、非实时低速总线、扩展总线1、扩展总线2、…、扩展总线n等，还包括多个扩展总线互联模块。各扩展总线通过所述扩展总线互联模块相互连接，并且与非实时低速总线相连。FIG. 5 shows another embodiment of the present invention, which is a multi-level bus system extended based on the number of stages of the multi-level bus system in FIG. 3 . The multilevel bus system includes a real-time high-speed bus, a non-real-time high-speed bus, a non-real-time low-speed bus, an expansion bus 1, an expansion bus 2, ..., an expansion bus n, etc., and a plurality of expansion bus interconnection modules. Each expansion bus is connected to each other through the expansion bus interconnection module, and is also connected to the non-real-time low-speed bus.
相对于图3所示的多级总线系统，该扩展多级总线系统进一步扩展了总线的级数，使得该系统可以支持更丰富的处理模块。当系统越来越复杂时，各种处理模块的处理速度和带宽需求的不同，使得简单的统一到图3所示的三级总线系统中较为困难，扩展总线的级数可以在不改变图3所述的系统性能和基本架构的前提下，集成更多的功能，使系统更具有竞争力。Compared with the multilevel bus system shown in FIG. 3 , the extended multilevel bus system further expands the number of bus levels, so that the system can support more abundant processing modules. As the system becomes more and more complex, the processing speed and bandwidth requirements of various processing modules are different, making it difficult to simply unify into the three-level bus system shown in Figure 3. The number of stages of the expansion bus can be changed without changing Figure 3 On the premise of the above system performance and basic architecture, more functions are integrated to make the system more competitive.
图3所示的多级总线系统的运行过程如下：The operation process of the multilevel bus system shown in Figure 3 is as follows:
1)系统上电后，嵌入式处理器读取boot指令，完成嵌入式处理器的初始化。根据boot指令对总线各处理模块的进行配置，并启动各处理模块，执行应用程序。1) After the system is powered on, the embedded processor reads the boot command to complete the initialization of the embedded processor. Configure each processing module of the bus according to the boot command, start each processing module, and execute the application program.
2)以太网以web服务器的方式接收远程用户端的指令，通过嵌入式处理器实时的调节各处理模块的运行模式以及运行参数等。并将需要反馈的数据通过以太网返回到远程用户端，并可以通过显示器显示。2) The Ethernet receives the instructions from the remote client in the form of a web server, and adjusts the operating mode and operating parameters of each processing module in real time through the embedded processor. And the data that needs to be fed back is returned to the remote client through Ethernet, and can be displayed on the display.
3)输入输出模块启动后，输入模块接收输入的视频图像，根据处理器的配置参数，将视频图像数据写入到高速存储器的相应地址，输出模块读取高速存储器中相应地址的图像信息，经HDMI线缆，实时发送到显示器或电视机等外部显示设备上。3) After the input and output module is started, the input module receives the input video image, and writes the video image data into the corresponding address of the high-speed memory according to the configuration parameters of the processor, and the output module reads the image information of the corresponding address in the high-speed memory. HDMI cable, real-time sending to external display devices such as monitors or TVs.
4)后处理模块启动后，从高速存储器中的相应地址读取待处理的视频信息，以配置好的工作模式和滤波系数对视频图像进行滤波操作或多种滤波组合操作，实现图像质量优化或特效生成，根据需要完成视频图像的色度空间转换、隔行扫描和逐行扫描模式间转换等。最后将处理好的视频图像信息写回到高速存储器中。4) After the post-processing module is started, it reads the video information to be processed from the corresponding address in the high-speed memory, performs filtering operation or multiple filtering combination operations on the video image with the configured working mode and filtering coefficients, and realizes image quality optimization or Generate special effects, complete video image chromaticity space conversion, interlaced scanning and progressive scanning mode conversion, etc. as required. Finally, the processed video image information is written back to the high-speed memory.
5)输入输出模块或后处理器模块工作进入异常时，嵌入式处理器会将异常信息以相应的编码方式通过GPIO显示出来，用户可以通过UART模块进行嵌入式处理器的断点调试。5) When the input and output module or the post-processor module is abnormal, the embedded processor will display the abnormal information through GPIO in the corresponding encoding mode, and the user can debug the breakpoint of the embedded processor through the UART module.
本发明在现场可编程门阵列(Field Programmable Gate Array，FPGA)开发平台上经过验证，能够满足多通道大数据量的实时数据采集，特效生成，视频优化和实时显示。The present invention has been verified on a field programmable gate array (Field Programmable Gate Array, FPGA) development platform, and can satisfy real-time data collection of multi-channel large data volume, generation of special effects, video optimization and real-time display.
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
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