CN102468856A - High speed parallel concatenated code coder decoder - Google Patents

Abstract

Translated fromChinese

本发明公开了一种高速并行级联码编码译码器，它被广泛应用于卫星通信、深空通信等系统，包括编码器和译码器，所述编码器包括分路变换器、第一至第四RS编码器、第一至第四插帧器、第一至第四交织器组和第一至第四卷积码编码器；所述译码器包括相位变换器、第一至第四卷积码译码器、第一至第四搜帧器、第一至第四解交织器和第一至第四RS译码器。本发明中编码器采用高速并行技术对高速串行数据直接进行级联码编码，并将编码后数据以并行的方式传输给调制设备；译码器对解调器输出的具有相位模糊度的并行数据直接进行级联码译码，并可以纠正由于AD采样时刻的随机性带来的并行数据次序随机性，及并行数据的随机不对齐性等问题。

The invention discloses a high-speed parallel concatenated code codec, which is widely used in systems such as satellite communication and deep space communication, and includes a coder and a decoder. The coder includes a shunt converter, a first to the fourth RS encoder, the first to the fourth frame interpolator, the first to the fourth interleaver group and the first to the fourth convolutional code encoder; the decoder includes a phase converter, the first to the fourth Four convolutional code decoders, first to fourth frame searchers, first to fourth deinterleavers and first to fourth RS decoders. In the present invention, the encoder uses high-speed parallel technology to directly perform concatenated code encoding on the high-speed serial data, and transmits the encoded data to the modulation device in parallel; The data is directly decoded by the concatenated code, and can correct the randomness of the parallel data sequence and the random misalignment of the parallel data due to the randomness of the AD sampling time.

Description

Translated fromChinese

高速并行级联码编码译码器High Speed Parallel Concatenated Codec

技术领域technical field

本发明涉及通信领域中的一种高速并行级联码编码译码器，特别适用于高信息速率信道编码译码装置。The invention relates to a high-speed parallel concatenated code codec in the communication field, and is especially suitable for high information rate channel codec devices.

背景技术Background technique

传统的级联码编码译码器多采用串行结构完成级联码编码译码码功能，资源占用量少、结构简单是其突出优点，特别适合低速率数据进行级联码编译码。当它用于高速率数据级联码编码译码时存在一个突出的缺陷：信息速率的提高，需要编码译码器对数据的处理速度也要相应提高，当编码译码器处理速度达到一定程度时，由于受到芯片处理速度及实现复杂度因素的制约，在工程中将很难实现。因此，在高速率数据情况下，串行级联码编码译码器的应用受到了极大的限制。Traditional concatenated codecs mostly use a serial structure to complete the concatenated codec codec function, with less resource usage and simple structure as their outstanding advantages, and are especially suitable for concatenated codec coding and decoding of low-rate data. When it is used for encoding and decoding high-speed data concatenated codes, there is an outstanding defect: the improvement of the information rate requires a corresponding increase in the processing speed of the codec for data. When the processing speed of the codec reaches a certain level When , due to the constraints of chip processing speed and implementation complexity factors, it will be difficult to realize in engineering. Therefore, in the case of high-speed data, the application of the serial concatenated codec is greatly limited.

发明内容Contents of the invention

本发明的目的在于避免上述背景技术中的不足之处而提供一种全新的高速并行级联码编码译码器。本发明不但具有与传统的串行级联码编码译码器相同的系统性能，而且通过译码器直接消除了由于相位调制带来的数据相位模糊度问题，并且克服了由于数据并行处理带来的译码端并行数据间不同随机延时和并行数据间不同随机次序等问题，还具有集成化程度高、体积小、重量轻、机动性好等特点。The object of the present invention is to provide a brand-new high-speed parallel concatenated code codec to avoid the disadvantages of the above-mentioned background technology. The present invention not only has the same system performance as the traditional serial concatenated code codec, but also directly eliminates the data phase ambiguity problem caused by phase modulation through the decoder, and overcomes the problems caused by data parallel processing. Different random delays between parallel data at the decoding end and different random orders between parallel data, etc., also have the characteristics of high integration, small size, light weight, and good mobility.

本发明的目的是这样实现的：The purpose of the present invention is achieved like this:

高速并行级联码编码译码器，包括编码器和译码器，所述编码器包括分路变换器1、第一至第四RS编码器2-1至2-4、第一至第四插帧器3-1至3-4、第一至第四交织器组4-1至4-4和第一至第四卷积码编码器5-1至5-4；所述译码器包括相位变换器6、第一至第四卷积码译码器7-1至7-4、第一至第四搜帧器8-1至8-4、第一至第四解交织器9-1至9-4和第一至第四RS译码器10-1至10-4；A high-speed parallel concatenated code codec includes an encoder and a decoder, and the encoder includes ashunt converter 1, first to fourth RS encoders 2-1 to 2-4, first to fourth Frame inserters 3-1 to 3-4, first to fourth interleaver groups 4-1 to 4-4 and first to fourth convolutional code encoders 5-1 to 5-4; the decoder Includingphase converter 6, first to fourth convolutional code decoders 7-1 to 7-4, first to fourth frame searchers 8-1 to 8-4, first to fourth deinterleavers 9 -1 to 9-4 and first to fourth RS decoders 10-1 to 10-4;

所述分路变换器1的输入端口1与待编码串行数据输入端口A1相连，分路变换器1的输入端口2与源同步时钟输入端口B1相连，分路变换器1的输出端口3、4、5、6分别与第一至第RS编码器2-1至2-4的输入端口1相连；第一至第RS编码器2-1至2-4的各输出端口2分别与第一至第四插帧器3-1至3-4的输入端口1相连；第一至第四插帧器3-1至3-4的输出端口2分别与第一至第四交织器组4-1至4-4的输入端口1相连；第一至第四交织器组4-1至4-4的输出端口2分别与第一至第四卷积码编码器5-1至5-4输入端口1相连；第一至第四卷积码编码器5-1至5-4的输出端口2、3分别输出已完成的编码数据；Theinput port 1 of theshunt converter 1 is connected to the serial data input port A1 to be encoded, theinput port 2 of theshunt converter 1 is connected to the source synchronous clock input port B1, theoutput port 3 of theshunt converter 1, 4, 5, 6 are respectively connected to theinput port 1 of the first to the first RS encoder 2-1 to 2-4; eachoutput port 2 of the first to the first RS encoder 2-1 to 2-4 is respectively connected to the first Theinput ports 1 to the fourth frame inserters 3-1 to 3-4 are connected; theoutput ports 2 of the first to fourth frame inserters 3-1 to 3-4 are respectively connected to the first to fourth interleaver groups 4- Theinput ports 1 to 4-4 are connected; theoutput ports 2 of the first to fourth interleaver groups 4-1 to 4-4 are input with the first to fourth convolutional code encoders 5-1 to 5-4 respectively Theport 1 is connected; theoutput ports 2 and 3 of the first to fourth convolutional code encoders 5-1 to 5-4 respectively output the completed encoded data;

分路变换器将输入的串行数据进行串并变换处理后得到四路并行数据并分别输出至第一至第四RS编码器，第一至第四RS编码器分别将输入的数据进行RS编码后输出至第一至第四插帧器，第一至第四插帧器将RS编码器产生的最后一位校验位用固定帧头替换并将数据输出给第一至第四交织器，第一至第四交织器将输入数据进行交织处理后出给第一至第四卷积码编码器，第一至第四卷积码编码器对输入数据进行卷积码编码后，分别输出已完成的编码数据；The shunt converter performs serial-to-parallel conversion on the input serial data to obtain four channels of parallel data and outputs them to the first to fourth RS encoders respectively, and the first to fourth RS encoders respectively perform RS encoding on the input data Then output to the first to fourth frame inserters, the first to fourth frame inserters replace the last parity bit generated by the RS encoder with a fixed frame header and output the data to the first to fourth interleavers, The first to fourth interleavers interleave the input data to the first to fourth convolutional code encoders, and the first to fourth convolutional code encoders perform convolutional code encoding on the input data, and output the Completed encoded data;

所述相位变换器6的输入端口1、2、3、4、5、6、7、8分别与解调设备输出的8路待译码并行数据相连，相位变换器6输出端口9、10、11、12、13、14、15、16分别与第一至第四卷积码译码器7-1至7-4的输入端口1、2相连，相位变换器6输入端口17、19、21、23分别与第一至第四卷积码译码器7-1至7-4的输出端口4相连，相位变换器6的输入端口18、20、22、24分别与第一至第四搜帧器8-1至8-4的输出端口3相连；第一至第四卷积码译码器7-1至7-4的输出端口3分别与第一至第四搜帧器8-1至8-4的输入端口1相连；第一至第四搜帧器8-1至8-4的输出端口2分别与第一至第四解交织器9-1至9-4的输入端口1相连，第一至第四搜帧器8-1至8-4的输出端口4分别与第一至第四解交织器9-1至9-4对应的输入端口3相连；第一至第四解交织器9-1至9-4的输出端口2分别与第一至第四RS译码器10-1至10-4的输入端口1相连，第一至第四解交织器9-1至9-4的输出端口4分别与第一至第四RS译码器10-1至10-4的输入端口3相连，第一至第四RS译码器10-1至10-4的输出端口2输出数据即为高速并行级联码译码器最终输出数据，并将传输给相应的后续数据接收设备；Theinput ports 1, 2, 3, 4, 5, 6, 7, and 8 of thephase converter 6 are respectively connected to the 8-way parallel data to be decoded output by the demodulation device, and thephase converter 6output ports 9, 10, 11, 12, 13, 14, 15, 16 are respectively connected to theinput ports 1, 2 of the first to fourth convolutional code decoders 7-1 to 7-4, and thephase converter 6input ports 17, 19, 21 , 23 are respectively connected with theoutput ports 4 of the first to the fourth convolutional code decoders 7-1 to 7-4, and theinput ports 18, 20, 22, 24 of thephase converter 6 are connected with the first to the fourth convolutional code decoders respectively. Theoutput ports 3 of the framers 8-1 to 8-4 are connected; theoutput ports 3 of the first to the fourth convolutional code decoders 7-1 to 7-4 are respectively connected to the first to the fourth frame searchers 8-1 Connect to theinput port 1 of 8-4; Theoutput port 2 of the first to the fourth frame searcher 8-1 to 8-4 is respectively connected with theinput port 1 of the first to the fourth deinterleaver 9-1 to 9-4 connected, theoutput ports 4 of the first to fourth frame searchers 8-1 to 8-4 are respectively connected to thecorresponding input ports 3 of the first to fourth deinterleavers 9-1 to 9-4; the first to fourth Theoutput ports 2 of the deinterleavers 9-1 to 9-4 are respectively connected to theinput ports 1 of the first to fourth RS decoders 10-1 to 10-4, and the first to fourth deinterleavers 9-1 to Theoutput port 4 of 9-4 is connected with theinput port 3 of the first to the fourth RS decoder 10-1 to 10-4 respectively, and the output port of the first to the fourth RS decoder 10-1 to 10-4 2 The output data is the final output data of the high-speed parallel concatenated code decoder, and will be transmitted to the corresponding subsequent data receiving equipment;

相位变换器依据第一至第四卷积码译码器及第一至第四搜帧器提供的反馈控制信号，将解调设备输出的8路待译码并行数据进行自适应处理后，输出给第一至第四卷积码译码器，第一至第四卷积码译码器对输入数据进行卷积码译码后，将其输出给第一至第四搜帧器，第一至第四搜帧器对输入数据进行搜帧，当帧同步后将数据输出给第一至第四解交织器，第一至第四解交织器对输入数据进行解交织处理后，将数据输出给第一至第四RS译码器，第一至第四RS译码器对输入数据进行RS译码后的输出数据即为高速并行级联码译码器最终输出数据，并将传输给相应的后续数据接收设备；According to the feedback control signals provided by the first to fourth convolutional code decoders and the first to fourth frame searchers, the phase converter performs adaptive processing on the 8 channels of parallel data to be decoded output by the demodulation device, and outputs For the first to fourth convolutional code decoders, the first to fourth convolutional code decoders perform convolutional code decoding on the input data, and then output it to the first to fourth frame searchers, the first The fourth frame searcher performs frame search on the input data, and outputs the data to the first to fourth deinterleavers after the frame is synchronized, and the first to fourth deinterleavers perform deinterleaving processing on the input data, and output the data For the first to fourth RS decoders, the output data after the first to fourth RS decoders perform RS decoding on the input data is the final output data of the high-speed parallel concatenated code decoder, and will be transmitted to the corresponding subsequent data receiving equipment;

所述的相位变换器6包括第一至第四可控反相交换器11-1至11-4、第一至第四可控延时器12-1至12-4、可控次序交换器13和数据调整控制器14；第一至第四可控反相交换器11-1至11-4各输入端口1、2分别连接待译码数据，第一至第四可控反相交换器11-1至11-4的输出端口3、4分别与第一至第四可控延时器12-1至12-4的输入端口1、2相连，第一至第四可控延时器12-1至12-4的输出端口3分别与可控次序交换器13输入端口1、3、5、7相连，第一至第四可控延时器12-1至12-4的输出端口5分别与可控次序交换器13输入端口2、4、6、8相连；可控次序交换器13输出端口9、11、13、15分别与第一至第四卷积码译码器7-1至7-4的输入端口1相连，可控次序交换器13输出端口10、12、14、16分别与第一至第四卷积码译码器7-1至7-4的输入端口2相连；数据调整控制器14输入端口3、4、5、6分别与第一至第四卷积码译码器7-1至7-4的输出端口4相连，数据调整控制器14输入端口7、8、9、10脚分别与第一至第四搜帧器8-1至8-4的输出端口3相连，数据调整控制器14输出端口1分别与第一至第四可控反相交换器11-1至11-4输入端口5相连，数据调整控制器14输出端口11、12、13和14分别与第一至第四可控延时器12-1至12-4的输入端口4相连，数据调整控制器14的输出端口2与可控次序交换器13的输入端口17相连；Thephase converter 6 includes first to fourth controllable inverting switches 11-1 to 11-4, first to fourth controllable delays 12-1 to 12-4,controllable sequence switches 13 and adata adjustment controller 14; theinput ports 1 and 2 of the first to fourth controllable inverting switches 11-1 to 11-4 are respectively connected to the data to be decoded, and the first to fourth controllable inverting switches Theoutput ports 3 and 4 of 11-1 to 11-4 are respectively connected to theinput ports 1 and 2 of the first to fourth controllable delayers 12-1 to 12-4, and the first to fourth controllable delayers Theoutput ports 3 of 12-1 to 12-4 are connected to theinput ports 1, 3, 5, and 7 of thecontrollable sequence switch 13 respectively, and the output ports of the first to fourth controllable delayers 12-1 to 12-4 5 are respectively connected to theinput ports 2, 4, 6, 8 of thecontrollable sequence switcher 13; theoutput ports 9, 11, 13, 15 of thecontrollable sequence switcher 13 are respectively connected to the first to fourth convolutional code decoders 7- 1 to 7-4's input port 1 is connected, and theoutput ports 10, 12, 14, 16 of thecontrollable sequence switcher 13 are respectively connected to theinput ports 2 of the first to the fourth convolutional code decoders 7-1 to 7-4 connected;data adjustment controller 14input ports 3, 4, 5, 6 are respectively connected to theoutput port 4 of the first to fourth convolutional code decoders 7-1 to 7-4,data adjustment controller 14input ports 7 . 11-1 to 11-4input port 5 is connected, and theoutput ports 11, 12, 13 and 14 of thedata adjustment controller 14 are respectively connected to theinput port 4 of the first to fourth controllable delay devices 12-1 to 12-4 Connected, theoutput port 2 of thedata adjustment controller 14 is connected with theinput port 17 of thecontrollable sequence switch 13;

第一至第四可控反相交换器依据数据调整控制器输出相应控制信号，将输入数据进行相应反相交换处理后，输出给第一至第四可控延时器，第一至第四可控延时器依据数据调整控制器输出相应控制信号，将数据进行相应延时处理后，将数据输出给可控次序交换器，可控次序交换器依据数据调整控制器输出相应控制信号，将数据进行相应排序后，将数据输出给第一至第四卷积码译码器。The first to fourth controllable inverting converters output corresponding control signals according to the data adjustment controller, and after the input data is subjected to corresponding inverting and exchanging processing, they are output to the first to fourth controllable delayers, and the first to fourth The controllable delayer adjusts the controller to output the corresponding control signal according to the data, and after the data is correspondingly delayed, it outputs the data to the controllable sequence switcher, and the controllable sequence switcher adjusts the controller to output the corresponding control signal according to the data, and the After the data is sorted accordingly, the data is output to the first to fourth convolutional code decoders.

高速并行级联码译码器相位变换器6中并行数据相位模糊度消除算法、并行数据时延消除算法、并行数据随机次序消除算法。The parallel data phase ambiguity elimination algorithm, the parallel data time delay elimination algorithm, and the parallel data random order elimination algorithm in thephase converter 6 of the high-speed parallel concatenated code decoder.

本发明相比背景技术具有如下优点：Compared with background technology, the present invention has the following advantages:

1.本发明中高速并行级联码编码器采用高速并行技术对高速串行数据直接进行级联码编码，并将编码后数据以并行的方式传输给相应调制设备。1. The high-speed parallel concatenated code encoder in the present invention uses high-speed parallel technology to directly perform concatenated code encoding on high-speed serial data, and transmits the encoded data to the corresponding modulation device in parallel.

2.本发明中高速并行级联码译码器对解调器输出的具有相位模糊度的并行数据直接进行级联码译码。2. The high-speed parallel concatenated code decoder in the present invention directly performs concatenated code decoding on the parallel data with phase ambiguity output by the demodulator.

3.本发明高速并行级联码译码器中自动相位变换器，利用卷积码解码器，搜帧器的反馈信息解决了并行数据间数据次序随机性与并行数据间随机不对齐性等问题，这些问题都是由于数据采用并行处理后带来的新问题。3. The automatic phase converter in the high-speed parallel concatenated code decoder of the present invention uses the convolutional code decoder and the feedback information of the frame search device to solve the problems of randomness of data order between parallel data and random misalignment between parallel data. , these problems are all new problems brought about by parallel processing of data.

4.本发明的组成部件采用大规模现场可编程器件制作，因此可通过配置不同的程序灵活地实现对工作参数的修改，使结构大大简化，成本显著降低。4. The components of the present invention are made of large-scale field programmable devices, so the modification of the working parameters can be flexibly implemented by configuring different programs, which greatly simplifies the structure and reduces the cost significantly.

5.本发明集成化程度高，因此体积小，重量轻，性能稳定可靠，维修方便，设备机动能力明显提高。5. The invention has a high degree of integration, so it is small in size, light in weight, stable and reliable in performance, convenient in maintenance, and significantly improves the maneuverability of the equipment.

附图说明Description of drawings

图1是本发明高速并行级联码编码器的电原理图。FIG. 1 is an electrical schematic diagram of a high-speed parallel concatenated code encoder of the present invention.

图2是本发明高速并行级联码译码器的电原理图。Fig. 2 is an electrical principle diagram of the high-speed parallel concatenated code decoder of the present invention.

图3是本发明相位变换器6的电原理图。FIG. 3 is an electrical schematic diagram of thephase converter 6 of the present invention.

具体实施方式Detailed ways

参照图1至图3，本发明编码器中包括分路变换器1、RS编码器组2-1，2-2，2-3，2-4、插帧器组3-1，3-2，3-3，3-4、交织器组4-1，4-2，4-3，4-4、卷积码编码器组5-1，5-2，5-3，5-4；译码器中包括相位变换器6、卷积码译码器组7-1，7-2，7-3，7-4、搜帧器组8-1，8-2，8-3，8-4、解交织器组9-1，9-2，9-3，9-4、RS译码器组10-1，10-2，10-3，10-4；组成。图1是本发明高速并行级联码编码器实施例的实现原理方框图，图2是本发明高速并行级联码译码器实施例的实现原理方框图，实施例按图1，图2连接。1 to 3, the encoder of the present invention includes ashunt converter 1, RS encoder groups 2-1, 2-2, 2-3, 2-4, frame inserter groups 3-1, 3-2 , 3-3, 3-4, interleaver group 4-1, 4-2, 4-3, 4-4, convolutional code encoder group 5-1, 5-2, 5-3, 5-4; The decoder includes aphase converter 6, a convolutional code decoder group 7-1, 7-2, 7-3, 7-4, and a frame searcher group 8-1, 8-2, 8-3, 8 -4. Composition of deinterleaver groups 9-1, 9-2, 9-3, 9-4, and RS decoder groups 10-1, 10-2, 10-3, 10-4. Fig. 1 is the realization principle block diagram of high-speed parallel concatenated code encoder embodiment of the present invention, Fig. 2 is the realization principle block diagram of high-speed parallel concatenation code decoder embodiment of the present invention, embodiment is connected according to Fig. 1, Fig. 2.

所述高速并行级联码编码器中的分路变换器1输入端1脚与待编码串行输入数据相连，输入端2脚与输入数据相对应的源同步时钟相连，其输出端3、4、5、6脚分别与RS编码器组2-1、2-2、2-3、2-4的输入端1脚相连，分路变换器1将输入的串行数据进行串并变换处理后得到四路并行数据，此时每一路并行数据是相对独立的，各路数据速率均为原数据速率的四分之一，RS编码器组2-1、2-2、2-3、2-4均由ISE10.1中提供的RS编码器软核，依照实际工程需要，通过RS编码器软核生成向导进行相应参数设置并生成对应网表，最终在Xilinx原厂生产的FPGA系列产品LXC5V110型号上实现，RS编码器组2-1、2-2、2-3、2-4将输入的数据进行RS编码后由其输出端2脚将各自编码后的数据分别对应输出至插帧器组3-1、3-2、3-3、3-4对应输入1脚，插帧器组3-1、3-2、3-3、3-4的工作原理是利用二选一数据选择器，通过循环计数器产生控制逻辑信号的方法，将RS编码器产生的最后一位校验位用固定帧头替换，其中并行的4路数据所插入的帧头格式是不一致的，各相应帧头数据格式可灵活选择，插帧器组3-1、3-2、3-3、3-4分别通过输出2脚将数据输出给交织器组4-1、4-2、4-3、4-4对应输入1脚，交织器组4-1、4-2、4-3、4-4均由ISE10.1中提供的交织器软核，依照实际工程需要，通过交织器软核生成向导进行相应参数设置并生成对应网表，最终在Xilinx原厂生产的FPGA系列产品LXC5V110型号上实现，交织器组4-1、4-2、4-3、4-4将输入数据进行交织处理后通过交织器组5-1、5-2、5-3、5-4输出2脚输出给卷积码编码器组5-1、5-2、5-3、5-4对应输入1脚，卷积码编码器组5-1、5-2、5-3、5-4均由ISE10.1中提供的卷积码编码器软核，依照实际工程需要，通过卷积码编码器软核生成向导进行相应参数设置并生成对应网表，最终在Xilinx原厂生产的FPGA系列产品LXC5V110型号上实现，卷积码编码器组5-1、5-2、5-3、5-4对输入数据进行卷积码编码后，通过卷积码编码器组5-1、5-2、5-3、5-4输出2、3脚输出，对应的输出信号C1、D1、E1、F1、G1、H1、I1、J1即为最终输出的级联码编码后数据。In the high-speed parallel concatenated code encoder,pin 1 of the input terminal of the shunt converter is connected to the serial input data to be encoded,pin 2 of the input terminal is connected to the source synchronous clock corresponding to the input data, and itsoutput terminals 3, 4 , 5, and 6 pins are respectively connected to theinput pin 1 of the RS encoder group 2-1, 2-2, 2-3, and 2-4, and theshunt converter 1 performs serial-to-parallel conversion processing on the input serial data Four channels of parallel data are obtained. At this time, each channel of parallel data is relatively independent, and the data rate of each channel is 1/4 of the original data rate. RS encoder groups 2-1, 2-2, 2-3, 2- 4 are all provided by the RS encoder soft core provided in ISE10.1. According to the actual project needs, the corresponding parameter settings are set through the RS encoder soft core generation wizard and the corresponding netlist is generated. Finally, the FPGA series product LXC5V110 model produced by Xilinx original factory Realized above, the RS encoder groups 2-1, 2-2, 2-3, 2-4 perform RS encoding on the input data, and then output the encoded data to the frame inserter group by theiroutput pin 2 respectively. 3-1, 3-2, 3-3, 3-4 correspond toinput pin 1, and the working principle of the frame inserter group 3-1, 3-2, 3-3, 3-4 is to use the data selector to select one of the two , through the method of generating the control logic signal through the loop counter, the last parity bit generated by the RS encoder is replaced with a fixed frame header, and the format of the frame header inserted into the parallel 4-way data is inconsistent, and the corresponding frame header data The format can be flexibly selected, and the frame inserter groups 3-1, 3-2, 3-3, 3-4 respectively output data to the interleaver groups 4-1, 4-2, 4-3, 4- 4 corresponds toinput pin 1, interleaver groups 4-1, 4-2, 4-3, 4-4 are all provided by the interleaver soft core provided in ISE10.1, according to actual engineering needs, through the interleaver soft core generation wizard The corresponding parameters are set and the corresponding netlist is generated, and finally implemented on the FPGA series product LXC5V110 model produced by Xilinx. The interleaver groups 4-1, 4-2, 4-3, and 4-4 interleave the input data and pass Interleaver group 5-1, 5-2, 5-3, 5-4output pin 2 output to convolution code encoder group 5-1, 5-2, 5-3, 5-4 corresponding toinput pin 1, volume The product code encoder groups 5-1, 5-2, 5-3, and 5-4 are all generated by the soft core of the convolutional code encoder provided in ISE10.1, according to actual engineering needs. The wizard sets the corresponding parameters and generates the corresponding netlist, which is finally realized on the FPGA series product LXC5V110 model produced by Xilinx, and the convolution code encoder group 5-1, 5-2, 5-3, 5-4 pairs of input data After the convolutional code is encoded,output pins 2 and 3 through the convolutional code encoder group 5-1, 5-2, 5-3, 5-4, and the corresponding output signals C1, D1, E1, F1, G1, H1, I1, and J1 are the final output data encoded by the concatenated code.

所述高速并行级联码译码器中的相位变换器6的输入端1、2、3、4、5、6、7、8脚分别与待译码数据A2、B2、C2、D2、E2、F2、G2、H2相连，相位变换器6输入17、18、19、20、21、22、23、24脚分别与卷积码译码器组7-1，7-2，7-3，7-4输出4脚与搜帧器组8-1，8-2，8-3，8-4输出3脚各对应引脚相连，相位变换器6通过这些反馈信号对输入信号进行自动相位变环、次序交换与相对时延消除，信号经变换处理后分别输出至卷积码译码器组7-1，7-2，7-3，7-4对应输入1脚、2脚，卷积码译码器组7-1，7-2，7-3，7-4均由ISE10.1中提供的卷积码译码器软核，依照实际工程需要及相关编码器设置，通过卷积码编码器软核生成向导进行相应参数设置并生成对应网表，最终在Xilinx原厂生产的FPGA系列产品LXC5V220型号上实现，卷积码译码器组7-1，7-2，7-3，7-4将输入的数据进行卷积码译码后通过其对应输出2脚将各个译码后的数据输出至搜帧器组8-1，8-2，8-3，8-4对应输入1脚，搜帧器组8-1，8-2，8-3，8-4工作原理为，搜帧器将输入数据分为4路，每路数据通过移位寄存器分别与不同帧头进行比较，当某次比对第一次相等时，相应计数器开始计数，若在下一个帧头应该出现时比对也为相等，则认为发现帧头，若此时比对不相等，则计数器清零，帧同步信号格式定义为，当没有帧同步时，为逻辑低电平，若帧同步时，首先为3bit高电平，然后根据相应帧头类别依此为“00”，“01”，“10”，“11”，然后输出高电平，依此周期循环，当帧失步时，信号变为低电平，即该信号若有3bit逻辑低，则表示帧失步，当判断为帧同步后，将对应帧同步路上的数据通过搜帧器组8-1，8-2，8-3，8-4输出2脚分别输出给解交织器组9-1，9-2，9-3，9-4，并通过搜帧器组8-1，8-2，8-3，8-4输出4脚指示帧同步相关起始位置信息，解交织器组9-1，9-2，9-3，9-4均由ISE10.1中提供的卷积码译码器软核，依照实际工程需要及相关编码器设置，通过卷积码编码器软核生成向导进行相应参数设置并生成对应网表，最终在Xilinx原厂生产的FPGA系列产品LXC5V220型号上实现，解交织器组9-1，9-2，9-3，9-4将输入数据进行解交织处理后通过解交织器组9-1，9-2，9-3，9-4对应输出2脚分别输出给RS译码器组10-1，10-2，10-3，10-4相应输入1脚，相应的帧同步信号由解交织器组9-1，9-2，9-3，9-4对应输出4脚输出给RS译码器组10-1，10-2，10-3，10-4输入3脚，RS译码器组10-1，10-2，10-3，10-4均由ISE10.1中提供的RS译码器软核，依照实际工程需要及相关编码器设置，通过RS译码器软核生成向导进行相应参数设置并生成对应网表，最终在Xilinx原厂生产的FPGA系列产品LXC5V220型号上实现，RS译码器组10-1，10-2，10-3，10-4对输入数据进行RS译码后，通过RS译码器组10-1，10-2，10-3，10-4将译码后数据从输出2脚输出即为高速并行级联码译码器最终输出数据，此4路数据进过并串变换，即可实现串行输出。Theinput terminals 1, 2, 3, 4, 5, 6, 7, and 8 pins of thephase converter 6 in the described high-speed parallel concatenated code decoder are respectively connected with the data to be decoded A2, B2, C2, D2, E2 . The 7-4output pin 4 is connected to the corresponding pins of the frame searcher group 8-1, 8-2, 8-3, and 8-4output 3 pins, and thephase converter 6 automatically phase-changes the input signal through these feedback signals. Ring, sequence exchange and relative delay elimination, the signal is transformed and output to the convolutional code decoder group 7-1, 7-2, 7-3, 7-4 corresponding to theinput pin 1,pin 2, convolution Code decoder groups 7-1, 7-2, 7-3, and 7-4 are soft cores of convolutional code decoders provided in ISE10.1. Code encoder soft core generation wizard to set corresponding parameters and generate corresponding netlist, and finally realize it on the FPGA series product LXC5V220 model produced by Xilinx original factory, convolution code decoder group 7-1, 7-2, 7-3 , 7-4 performs convolutional code decoding on the input data and outputs each decoded data to the frame searcher group 8-1, 8-2, 8-3, 8-4 through itscorresponding output pin 2Input pin 1, frame searcher group 8-1, 8-2, 8-3, 8-4 works as follows: the frame searcher divides the input data into 4 channels, and each channel of data is connected to different frame headers through the shift register For comparison, when a certain comparison is equal for the first time, the corresponding counter starts counting. If the comparison is also equal when the next frame header should appear, it is considered that the frame header is found. If the comparison is not equal at this time, the counter is cleared. Zero, the format of the frame synchronization signal is defined as, when there is no frame synchronization, it is a logic low level, if the frame is synchronized, it is first a 3bit high level, and then according to the corresponding frame header category, it is "00", "01", "10", "11", and then output high level, and cycle according to this cycle. When the frame is out of sync, the signal becomes low level, that is, if the signal has a 3-bit logic low, it means that the frame is out of sync. After the frame is synchronized, the data on the corresponding frame synchronization circuit is output to the deinterleaver group 9-1, 9-2, 9 respectively through the frame searcher group 8-1, 8-2, 8-3, 8-4 output pin 2 -3, 9-4, and through the frame searcher group 8-1, 8-2, 8-3, 8-4output 4 pins to indicate frame synchronization related start position information, deinterleaver group 9-1, 9- 2, 9-3, and 9-4 are all provided by the convolutional code decoder soft core provided in ISE10.1. According to the actual project needs and related encoder settings, set the corresponding parameters through the convolutional code encoder soft core generation wizard And generate the corresponding netlist, and finally realize it on the FPGA series product LXC5V220 model produced by Xilinx original factory. The deinterleaver group 9-1, 9-2, 9-3, 9-4 deinterleaves the input data and passes the deinterleaving process. Interleaver groups 9-1, 9-2, 9- 3, 9-4 corresponds to output 2 pins and outputs to RS decoder group 10-1, 10-2, 10-3, 10-4corresponding input 1 pin, and the corresponding frame synchronization signal is sent by deinterleaver group 9-1 , 9-2, 9-3, 9-4 correspond tooutput 4 pins and output to RS decoder group 10-1, 10-2, 10-3, 10-4input 3 pins, RS decoder group 10-1 , 10-2, 10-3, and 10-4 are all provided by the RS decoder soft core provided in ISE10.1. According to the actual project needs and related encoder settings, set the corresponding parameters through the RS decoder soft core generation wizard And generate the corresponding netlist, and finally realize it on the FPGA series product LXC5V220 model produced by Xilinx original factory. After the RS decoder group 10-1, 10-2, 10-3, and 10-4 perform RS decoding on the input data, Through the RS decoder group 10-1, 10-2, 10-3, 10-4, the decoded data is output from theoutput pin 2, which is the final output data of the high-speed parallel concatenated code decoder. Serial output can be realized through parallel-to-serial conversion.

所述相位变换器6由可控反相交换器组11-1，11-2，11-3，11-4、可控延时器组12-1，12-2，12-3，12-4、可控次序交换器13、数据调整控制器14组成。可控反相交换器组11-1，11-2，11-3，11-4输入1，2脚分别对应连接待译码数据A、B、C、D、E、F、G、H，可控反相交换器组11-1，11-2，11-3，11-4依据数据调整控制器输出1脚通过可控反相交换器组11-1，11-2，11-3，11-4输入5脚接入的控制反馈信号，当该信号出现上升沿时，可控反相交换器组11-1，11-2，11-3，11-4依次对输入数据进行反相、交换的8钟组合变换之一，可控反相交换器组11-1，11-2，11-3，11-4输出3，4脚将处理后的数据分别传输至可控延时器12-1，12-2，12-3，12-4对应输入1，2脚，可控延时器组12-1，12-2，12-3，12-4依据数据调整控制器输出11、12、13、14脚通过可控反相交换器组11-1，11-2，11-3，11-4各自对应的输入5脚接入的控制反馈信号，当该信号为高电平时，通过输出3，5脚输出数据相对延迟1拍，当该信号为低电平时，通过输出3，5脚输出数据无相对延迟，可控延时器12-1，12-2，12-3，12-4将处理后的数据通过输出3，5脚分别对应传输给可控次序交换器13输入1，2，3，4，5，6，7，8脚，可控次序交换器13依据数据调整控制器输出17脚通过可控次序交换器13输入17脚接入的控制反馈信号，进行相应的数据次序调整，可控次序交换器将处理后的数据通过相应输出9，10，11，12，13，14，15，16脚，输出给卷积译码器组7-1，7-2，7-3，7-4对应输入1脚，2脚。数据调整控制器17通过卷积译码器组7-1，7-2，7-3，7-4输出4脚输出的误码率门限反馈信号与搜帧器组8-1，8-2，8-3，8-4输出3脚输出的帧同步指示信号，通过8路与门作为特定循环计数器复位信号，当该计数器计数达最高位时，产生一个脉冲信号，其余情况，该信号为低电平，此信号由输出1脚输出，当上述低电平持续一段时间，同时没有脉冲信号时，启动可控时延控制，此时依照帧同步信号相对延时，通过输出11，12，13，14脚控制信号分别控制数据的相对时延，当此操作结束后，通过内部触发信号，开始可控次序交换处理，此时所存各路帧同步信号后的帧头指示信息，即可产生控制信号，通过输出2脚控制可控次序交换器13，完成次序交换处理，可控次序交换器13输出9，10，11，12，13，14，15，16脚依次将处理后的数据传输给对应卷积码译码器组7-1，7-2，7-3，7-4对应输入1，2脚。Thephase converter 6 is composed of controllable inverting switch groups 11-1, 11-2, 11-3, 11-4, controllable delayer groups 12-1, 12-2, 12-3, 12- 4. It consists of acontrollable sequence switch 13 and adata adjustment controller 14. Controllable inverting switch groups 11-1, 11-2, 11-3, 11-4 input pins 1 and 2 are respectively connected to the data to be decoded A, B, C, D, E, F, G, H, The controllable inverting converter group 11-1, 11-2, 11-3, 11-4 adjusts theoutput pin 1 of the controller according to the data through the controllable inverting converter group 11-1, 11-2, 11-3, 11-4 inputs the control feedback signal connected topin 5. When the signal has a rising edge, the controllable inverting switch group 11-1, 11-2, 11-3, 11-4 inverts the input data insequence 1. One of the 8-clock combined transformations of the exchange, the controllable inverting switch group 11-1, 11-2, 11-3, 11-4outputs 3 and 4 pins to transmit the processed data to the controllable delayer respectively 12-1, 12-2, 12-3, 12-4 correspond to inputpins 1 and 2, and the controllable delayer group 12-1, 12-2, 12-3, 12-4 adjusts thecontroller output 11 according to the data , 12, 13, and 14 pins are connected to the control feedback signals through the corresponding input pins 5 of the controllable inverting switch groups 11-1, 11-2, 11-3, and 11-4. When the signal is at a high level , the output data ofpin 3 andpin 5 is relatively delayed by 1 beat, when the signal is low, there is no relative delay in the output data ofpin 3 andpin 5, and the controllable delayer 12-1, 12-2, 12-3 , 12-4 transmits the processed data to thecontrollable sequence switch 13 through the output pins 3 and 5 corresponding to the input pins 1, 2, 3, 4, 5, 6, 7, and 8, and thecontrollable sequence switch 13 is based on The data adjustment controller outputs 17 pins through thecontrollable sequence switch 13 to input the control feedback signal connected to 17 pins to adjust the corresponding data sequence, and the controllable sequence switcher passes the processed data through the correspondingoutputs 9, 10, 11, Pins 12, 13, 14, 15, and 16 are output to the convolutional decoder group 7-1, 7-2, 7-3, and 7-4 corresponding to inputpins 1 and 2. Thedata adjustment controller 17 outputs the BER threshold feedback signal output bypin 4 through the convolutional decoder group 7-1, 7-2, 7-3, 7-4 and the frame searcher group 8-1, 8-2 , 8-3, 8-4 output the frame synchronization indicator signal output bypin 3, and use the 8-way AND gate as a specific cycle counter reset signal. When the counter counts to the highest position, a pulse signal is generated. In other cases, the signal is Low level, this signal is output bypin 1. When the above low level lasts for a period of time and there is no pulse signal, the controllable delay control is started. At this time, according to the relative delay of the frame synchronization signal, through theoutput 11, 12, The control signals ofpins 13 and 14 respectively control the relative time delay of the data. When this operation is completed, the controllable sequence exchange process is started through the internal trigger signal. At this time, the frame header indication information stored after the frame synchronization signals of each channel can be generated. The control signal controls thecontrollable sequence switcher 13 by outputtingpin 2 to complete the sequence switching process, and thecontrollable sequence switcher 13 outputs pins 9, 10, 11, 12, 13, 14, 15, and 16 to transmit the processed data in sequence Correspondingly input pins 1 and 2 to the corresponding convolutional code decoder groups 7-1, 7-2, 7-3, and 7-4.

本发明简要工作原理如下：Brief operating principle of the present invention is as follows:

外部业务信号进行高速并行级联码编码时，所述高速并行级联码编码器中的分路变换器1输入端1脚与待编码输入数据通过A1通道相连，输入端2脚与输入数据相应源同步时钟信号B1相连，其输出端3、4、5、6脚分别与RS编码器组相连，数据输出至RS编码器进行RS编码后，由其输出端2脚将各编码后的数据输出至插帧器，插帧器将输入数据经过数据插帧后输出给交织器，交织器将输入数据进行交织处理后输出给卷积码编码器，卷积码编码器对输入数据进行卷积编码后，卷积码编码器输出数据即为高速并行级联码编码器最终输出数据。When external service signals are encoded with high-speed parallel concatenated codes,pin 1 of theinput terminal 1 of the shunt converter in the high-speed parallel concatenated code encoder is connected to the input data to be encoded through the A1 channel, andpin 2 of the input terminal corresponds to the input data The source synchronous clock signal is connected to B1, and itsoutput pins 3, 4, 5, and 6 are respectively connected to the RS encoder group. After the data is output to the RS encoder for RS encoding, the encoded data is output by itsoutput pin 2. To the frame inserter, the frame inserter outputs the input data to the interleaver after data frame insertion, the interleaver interleaves the input data and outputs it to the convolutional code encoder, and the convolutional code encoder performs convolutional encoding on the input data After that, the output data of the convolutional code encoder is the final output data of the high-speed parallel concatenated code encoder.

接收到待译码并行数据后，所述高速并行级联码译码器中的相位变换器6输入端与待译码并行数据通过通道A2、B2、C2、D2、E2、F2、G2、H2相连，相位变换器6将输入数据码流进行相应变换后输出至卷积码译码器，卷积码译码器将输入的数据进行卷积码译码后由其输出端将各个译码后的数据流输出至搜帧器，搜帧器完成数据搜帧后，将数据输出给解交织器，解交织器将输入数据进行解交织处理后输出给RS译码器，RS译码器对输入数据进行RS译码后，输出信号即为高速并行级联码译码器最终输出数据。After receiving the parallel data to be decoded, the input terminal of thephase converter 6 in the high-speed parallel concatenated code decoder and the parallel data to be decoded pass through channels A2, B2, C2, D2, E2, F2, G2, H2 connected, thephase converter 6 converts the input data code stream accordingly and outputs it to the convolutional code decoder, and the convolutional code decoder performs convolutional code decoding on the input data, and its output terminal converts each decoded The data stream is output to the frame searcher. After the frame searcher completes the data frame search, it outputs the data to the deinterleaver. The deinterleaver deinterleaves the input data and outputs it to the RS decoder. The RS decoder After the data is decoded by RS, the output signal is the final output data of the high-speed parallel concatenated code decoder.

本发明软件编写结构如下：The software writing structure of the present invention is as follows:

图1中所有功能模块均可在Virtex_LX110中实现，图2中所有功能模块均可在Virtex_LX220中实现，并通过FPGA相应IO引脚连接输入输出数据与时钟信号从而构成本发明。All functional modules in Fig. 1 can be realized in Virtex_LX110, all functional modules in Fig. 2 can be realized in Virtex_LX220, and connect input and output data and clock signal through corresponding IO pin of FPGA thereby constitute the present invention.

Claims (3)

Translated fromChinese

1.高速并行级联码编码译码器，包括编码器和译码器，其特征在于：所述编码器包括分路变换器(1)、第一至第四RS编码器(2-1至2-4)、第一至第四插帧器(3-1至3-4)、第一至第四交织器组(4-1至4-4)和第一至第四卷积码编码器(5-1至5-4)；所述译码器包括相位变换器(6)、第一至第四卷积码译码器(7-1至7-4)、第一至第四搜帧器(8-1至8-4)、第一至第四解交织器(9-1至9-4)和第一至第四RS译码器(10-1至10-4)；1. a high-speed parallel concatenated code codec, comprising a coder and a decoder, is characterized in that: the coder includes a shunt converter (1), the first to the fourth RS coder (2-1 to 2-4), first to fourth frame inserters (3-1 to 3-4), first to fourth interleaver groups (4-1 to 4-4) and first to fourth convolutional code encoding device (5-1 to 5-4); the decoder includes a phase shifter (6), a first to a fourth convolutional code decoder (7-1 to 7-4), a first to a fourth Frame searchers (8-1 to 8-4), first to fourth deinterleavers (9-1 to 9-4) and first to fourth RS decoders (10-1 to 10-4);所述分路变换器(1)的输入端口1与待编码串行数据输入端口A1相连，分路变换器(1)的输入端口2与源同步时钟输入端口B1相连，分路变换器(1)的输出端口3、4、5、6分别与第一至第四RS编码器(2-1至2-4)的输入端口1相连；第一至第四RS编码器(2-1至2-4)的各输出端口2分别与第一至第四插帧器(3-1至3-4)的输入端口1相连；第一至第四插帧器(3-1至3-4)的输出端口2分别与第一至第四交织器组(4-1至4-4)的输入端口1相连；第一至第四交织器组(4-1至4-4)的输出端口2分别与第一至第四卷积码编码器(5-1至5-4)输入端口1相连；第一至第四卷积码编码器(5-1至5-4)的输出端口2、3分别输出已完成的编码数据；The input port 1 of the demultiplexer (1) is connected with the serial data input port A1 to be encoded, the input port 2 of the demultiplexer (1) is connected with the source synchronous clock input port B1, and the demultiplexer (1) is connected with the input port B1 of the source synchronous clock. ) output ports 3, 4, 5, 6 are respectively connected to the input ports 1 of the first to fourth RS encoders (2-1 to 2-4); the first to fourth RS encoders (2-1 to 2 Each output port 2 of -4) is respectively connected with the input port 1 of the first to the fourth frame inserter (3-1 to 3-4); the first to the fourth frame inserter (3-1 to 3-4) The output port 2 of the first to the fourth interleaver group (4-1 to 4-4) is respectively connected to the input port 1; the output port 2 of the first to the fourth interleaver group (4-1 to 4-4) Connect with the first to the fourth convolutional code encoder (5-1 to 5-4) input port 1 respectively; The output port 2, the first to the fourth convolutional code encoder (5-1 to 5-4) 3 Output the completed encoded data respectively;分路变换器将输入的串行数据进行串并变换处理后得到四路并行数据并分别输出至第一至第四RS编码器，第一至第四RS编码器分别将输入的数据进行RS编码后输出至第一至第四插帧器，第一至第四插帧器将RS编码器产生的最后一位校验位用固定帧头替换并将数据输出给第一至第四交织器，第一至第四交织器将输入数据进行交织处理后出给第一至第四卷积码编码器，第一至第四卷积码编码器对输入数据进行卷积码编码后，分别输出已完成的编码数据；The shunt converter performs serial-to-parallel conversion on the input serial data to obtain four channels of parallel data and outputs them to the first to fourth RS encoders respectively, and the first to fourth RS encoders respectively perform RS encoding on the input data Then output to the first to fourth frame inserters, the first to fourth frame inserters replace the last parity bit generated by the RS encoder with a fixed frame header and output the data to the first to fourth interleavers, The first to fourth interleavers interleave the input data to the first to fourth convolutional code encoders, and the first to fourth convolutional code encoders perform convolutional code encoding on the input data, and output the Completed encoded data;所述相位变换器(6)的输入端口1、2、3、4、5、6、7、8分别与解调设备输出的8路待译码并行数据相连，相位变换器(6)输出端口9、10、11、12、13、14、15、16分别与第一至第四卷积码译码器(7-1至7-4)的输入端口1、2相连，相位变换器(6)输入端口17、19、21、23分别与第一至第四卷积码译码器(7-1至7-4)的输出端口4相连，相位变换器(6)的输入端口18、20、22、24分别与第一至第四搜帧器(8-1至8-4)的输出端口3相连；第一至第四卷积码译码器(7-1至7-4)的输出端口3分别与第一至第四搜帧器(8-1至8-4)的输入端口1相连；第一至第四搜帧器(8-1至8-4)的输出端口2分别与第一至第四解交织器(9-1至9-4)的输入端口1相连，第一至第四搜帧器(8-1至8-4)的输出端口4分别与第一至第四解交织器(9-1至9-4)对应的输入端口3相连；第一至第四解交织器(9-1至9-4)的输出端口2分别与第一至第四RS译码器(10-1至10-4)的输入端口1相连，第一至第四解交织器(9-1至9-4)的输出端口4分别与第一至第四RS译码器(10-1至10-4)的输入端口3相连，第一至第四RS译码器(10-1至10-4)的输出端口2输出数据即为高速并行级联码译码器最终输出数据，并将传输给相应的后续数据接收设备；The input ports 1, 2, 3, 4, 5, 6, 7, and 8 of the phase converter (6) are respectively connected to the 8-way parallel data to be decoded output by the demodulator, and the output port of the phase converter (6) 9, 10, 11, 12, 13, 14, 15, 16 are respectively connected with the input port 1, 2 of the first to the fourth convolutional code decoder (7-1 to 7-4), and the phase converter (6 ) input port 17,19,21,23 is connected with the output port 4 of the first to the fourth convolutional code decoder (7-1 to 7-4) respectively, the input port 18,20 of phase converter (6) , 22, 24 are respectively connected with the output port 3 of the first to the fourth frame searcher (8-1 to 8-4); the first to the fourth convolutional code decoder (7-1 to 7-4) The output ports 3 are respectively connected to the input ports 1 of the first to the fourth frame searchers (8-1 to 8-4); the output ports 2 of the first to the fourth frame searchers (8-1 to 8-4) are respectively It is connected with the input port 1 of the first to the fourth deinterleaver (9-1 to 9-4), and the output port 4 of the first to the fourth frame searcher (8-1 to 8-4) is connected with the first to the fourth frame searcher (8-1 to 8-4) respectively. The input port 3 corresponding to the fourth deinterleaver (9-1 to 9-4) is connected; the output port 2 of the first to the fourth deinterleaver (9-1 to 9-4) is respectively connected to the first to the fourth RS The input port 1 of the decoder (10-1 to 10-4) is connected, and the output port 4 of the first to the fourth deinterleaver (9-1 to 9-4) is respectively connected to the first to the fourth RS decoder The input port 3 of (10-1 to 10-4) is connected, and the output data of the output port 2 of the first to the fourth RS decoder (10-1 to 10-4) is the final high-speed parallel concatenated code decoder Output data and transmit it to the corresponding subsequent data receiving device;相位变换器依据第一至第四卷积码译码器及第一至第四搜帧器提供的反馈控制信号，将解调设备输出的8路待译码并行数据进行自适应处理后，输出给第一至第四卷积码译码器，第一至第四卷积码译码器对输入数据进行卷积码译码后，将其输出给第一至第四搜帧器，第一至第四搜帧器对输入数据进行搜帧，当帧同步后将数据输出给第一至第四解交织器，第一至第四解交织器对输入数据进行解交织处理后，将数据输出给第一至第四RS译码器，第一至第四RS译码器对输入数据进行RS译码后的输出数据即为高速并行级联码译码器最终输出数据，并将传输给相应的后续数据接收设备。According to the feedback control signals provided by the first to fourth convolutional code decoders and the first to fourth frame searchers, the phase converter performs adaptive processing on the 8 channels of parallel data to be decoded output by the demodulation device, and outputs For the first to fourth convolutional code decoders, the first to fourth convolutional code decoders perform convolutional code decoding on the input data, and then output it to the first to fourth frame searchers, the first The fourth frame searcher performs frame search on the input data, and outputs the data to the first to fourth deinterleavers after the frame is synchronized, and the first to fourth deinterleavers perform deinterleaving processing on the input data, and output the data For the first to fourth RS decoders, the output data after the first to fourth RS decoders perform RS decoding on the input data is the final output data of the high-speed parallel concatenated code decoder, and will be transmitted to the corresponding subsequent data receiving equipment.2.根据权利要求1所述的高速并行级联码编码译码器，其特征在于：相位变换器(6)包括第一至第四可控反相交换器(11-1至11-4)、第一至第四可控延时器(12-1至12-4)、可控次序交换器(13)和数据调整控制器(14)；2. The high-speed parallel concatenated code codec according to claim 1, characterized in that: the phase shifter (6) comprises first to fourth controllable inverting switches (11-1 to 11-4) , first to fourth controllable delayers (12-1 to 12-4), controllable sequence switcher (13) and data adjustment controller (14);第一至第四可控反相交换器(11-1至11-4)各输入端口1、2分别连接待译码数据，第一至第四可控反相交换器(11-1至11-4)的输出端口3、4分别与第一至第四可控延时器(12-1至12-4)的输入端口1、2相连，第一至第四可控延时器(12-1至12-4)的输出端口3分别与可控次序交换器(13)输入端口1、3、5、7相连，第一至第四可控延时器(12-1至12-4)的输出端口5分别与可控次序交换器(13)输入端口2、4、6、8相连；可控次序交换器(13)输出端口9、11、13、15分别与第一至第四卷积码译码器(7-1至7-4)的输入端口1相连，可控次序交换器(13)输出端口10、12、14、16分别与第一至第四卷积码译码器(7-1至7-4)的输入端口2相连；数据调整控制器(14)输入端口3、4、5、6分别与第一至第四卷积码译码器(7-1至7-4)的输出端口4相连，数据调整控制器(14)输入端口7、8、9、10脚分别与第一至第四搜帧器(8-1至8-4)的输出端口3相连，数据调整控制器(14)输出端口1分别与第一至第四可控反相交换器(11-1至11-4)输入端口5相连，数据调整控制器(14)输出端口11、12、13和14分别与第一至第四可控延时器(12-1至12-4)的输入端口4相连，数据调整控制器(14)的输出端口2与可控次序交换器(13)的输入端口17相连；The input ports 1 and 2 of the first to fourth controllable inverting switches (11-1 to 11-4) are respectively connected to the data to be decoded, and the first to fourth controllable inverting switches (11-1 to 11 -4) the output port 3,4 is connected with the input port 1,2 of the first to the fourth controllable delayer (12-1 to 12-4) respectively, the first to the fourth controllable delayer (12-4) -1 to 12-4) output port 3 is connected with controllable sequence switch (13) input port 1,3,5,7 respectively, the first to the fourth controllable delayer (12-1 to 12-4 ) output port 5 is connected to the input port 2, 4, 6, 8 of the controllable sequence switch (13) respectively; The input port 1 of the convolutional code decoder (7-1 to 7-4) is connected, and the output ports 10, 12, 14, 16 of the controllable sequence switcher (13) are respectively decoded with the first to fourth convolutional codes. The input port 2 of the device (7-1 to 7-4) is connected; the input port 3, 4, 5, 6 of the data adjustment controller (14) is respectively connected with the first to the fourth convolutional code decoder (7-1 to The output port 4 of 7-4) is connected, and the input ports 7, 8, 9, and 10 pins of the data adjustment controller (14) are respectively connected to the output port 3 of the first to fourth frame search devices (8-1 to 8-4) connected, the output port 1 of the data adjustment controller (14) is connected to the input port 5 of the first to fourth controllable inverting switches (11-1 to 11-4) respectively, and the output port 11, 12, 13 and 14 are respectively connected with the input port 4 of the first to the fourth controllable delayers (12-1 to 12-4), and the output port 2 of the data adjustment controller (14) is connected with the controllable sequence switch ( 13) the input port 17 is connected;第一至第四可控反相交换器依据数据调整控制器输出相应控制信号，将输入数据进行相应反相交换处理后，输出给第一至第四可控延时器，第一至第四可控延时器依据数据调整控制器输出相应控制信号，将数据进行相应延时处理后，将数据输出给可控次序交换器，可控次序交换器依据数据调整控制器输出相应控制信号，将数据进行相应排序后，将数据输出给第一至第四卷积码译码器。The first to fourth controllable inverting converters output corresponding control signals according to the data adjustment controller, and after the input data is subjected to corresponding inverting and exchanging processing, they are output to the first to fourth controllable delayers, and the first to fourth The controllable delayer adjusts the controller to output the corresponding control signal according to the data, and after the data is correspondingly delayed, it outputs the data to the controllable sequence switcher, and the controllable sequence switcher adjusts the controller to output the corresponding control signal according to the data, and the After the data is sorted accordingly, the data is output to the first to fourth convolutional code decoders.3.根据权利要求1所述的高速并行级联码编码译码器，其特征在于：高速并行级联码译码器相位变换器(6)中并行数据相位模糊度消除算法、并行数据时延消除算法、并行数据随机次序消除算法。3. The high-speed parallel concatenated code codec according to claim 1, characterized in that: in the high-speed parallel concatenated code decoder phase converter (6), parallel data phase ambiguity elimination algorithm, parallel data time delay Elimination algorithm, parallel data random order elimination algorithm.

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