CN102437196A - Low-temperature polycrystalline silicon thin film transistor and manufacturing method thereof - Google Patents

Abstract

Translated fromChinese

本发明公开了一种低温多晶硅薄膜晶体管及其制造方法，所述低温多晶硅薄膜晶体管包括栅极、源极和漏极，所述源极和漏极之间有沟道隔开，所述栅极和源极、漏极之间形成有多晶硅硅岛图案，其中，所述沟道处的多晶硅硅岛图案上至少有一个凹槽从而形成立体沟道，所述凹槽的深度小于沟道的深度。本发明提供的低温多晶硅薄膜晶体管，通过衍射曝光在沟道处的多晶硅硅岛图案上形成立体沟道，有效增大沟道宽度，从而增大薄膜晶体管的宽长比和开口率，且结构简单，易于实施。

The present invention discloses a low-temperature polysilicon thin film transistor and a manufacturing method thereof, wherein the low-temperature polysilicon thin film transistor comprises a gate, a source and a drain, wherein the source and the drain are separated by a channel, and a polysilicon island pattern is formed between the gate and the source and the drain, wherein the polysilicon island pattern at the channel has at least one groove to form a three-dimensional channel, and the depth of the groove is less than the depth of the channel. The low-temperature polysilicon thin film transistor provided by the present invention forms a three-dimensional channel on the polysilicon island pattern at the channel by diffraction exposure, effectively increasing the channel width, thereby increasing the aspect ratio and aperture ratio of the thin film transistor, and has a simple structure and is easy to implement.

Description

Translated fromChinese

低温多晶硅薄膜晶体管及其制造方法Low temperature polysilicon thin film transistor and its manufacturing method

技术领域technical field

本发明涉及一种薄膜晶体管及其制造方法，尤其涉及一种低温多晶硅薄膜晶体管及其制造方法。The invention relates to a thin film transistor and a manufacturing method thereof, in particular to a low-temperature polysilicon thin film transistor and a manufacturing method thereof.

背景技术Background technique

有机发光显示器件（OLED ）是主动发光器件。相比现在的主流平板显示技术薄膜晶体管液晶显示器（TFT -LCD )，OLED 具有高对比度，广视角，低功耗，体积更薄等优点，有望成为继LCD之后的下一代平板显示技术，是目前平板显示技术中受到关注最多的技术之一。Organic light-emitting display devices (OLEDs) are active light-emitting devices. Compared with the current mainstream flat-panel display technology Thin Film Transistor Liquid Crystal Display (TFT-LCD), OLED has the advantages of high contrast, wide viewing angle, low power consumption, and thinner volume. It is expected to become the next-generation flat-panel display technology after LCD. It is one of the most concerned technologies in flat panel display technology.

目前主要使用低温多晶硅薄膜晶体管（LTPS-TFT）驱动OLED发光，图1是一种现有技术薄膜晶体管的平面图，图2是按照图1中A-A线所形成的截面图。如图1和图2所示，先在玻璃衬底上使用化学气相沉积的方法沉积缓冲层，然后在缓冲层上沉积非晶硅；将非晶硅层使用固相结晶或者准分子激光晶化的方法转化为多晶硅；最后将多晶硅刻蚀成硅岛形状并依次在上面形成绝缘层、栅极金属层、介电层和源漏金属层图案，并最终形成驱动薄膜晶体管。At present, low-temperature polysilicon thin-film transistors (LTPS-TFT) are mainly used to drive OLEDs to emit light. Figure 1 is a plan view of a prior art thin-film transistor, and Figure 2 is a cross-sectional view formed along line A-A in Figure 1 . As shown in Figure 1 and Figure 2, a buffer layer is first deposited on the glass substrate by chemical vapor deposition, and then amorphous silicon is deposited on the buffer layer; the amorphous silicon layer is crystallized by solid phase crystallization or excimer laser The method is converted into polysilicon; finally, the polysilicon is etched into a silicon island shape, and an insulating layer, a gate metal layer, a dielectric layer, and a source-drain metal layer pattern are sequentially formed on it, and finally a driving thin film transistor is formed.

因为驱动OLED发光需要较大的电流，所以驱动TFT需要有较宽的沟道宽度和较短的沟道长度以使宽度和长度的比值足够大，从而驱动TFT能为OLED提供足够的电流以控制和驱动有机电致发光二极管发光。Because driving OLED requires a large current to emit light, the driving TFT needs to have a wider channel width and a shorter channel length to make the ratio of width to length large enough, so that the driving TFT can provide enough current for the OLED to control And drive organic light-emitting diodes to emit light.

为了保证显示屏的分辨率，像素区的面积需要尽可能的小，开口率需要尽可能的大，因此驱动薄膜晶体管以及外围电路不能超过一定的面积，这就决定了薄膜晶体管的沟道宽度不能做的太宽，在这种情况下需要增大薄膜晶体管沟道的宽长比就只能通过减小长度来解决，但是薄膜晶体管沟道长度降低到一定程度会引起漏电流和沟道击穿等现象，造成薄膜晶体管无法工作。In order to ensure the resolution of the display screen, the area of the pixel area needs to be as small as possible, and the aperture ratio needs to be as large as possible, so the driving thin film transistor and peripheral circuits cannot exceed a certain area, which determines that the channel width of the thin film transistor cannot If it is too wide, in this case, it is necessary to increase the width-to-length ratio of the thin film transistor channel, which can only be solved by reducing the length, but reducing the channel length of the thin film transistor to a certain extent will cause leakage current and channel breakdown and other phenomena, causing the thin film transistor to fail to work.

发明内容Contents of the invention

本发明所要解决的技术问题是提供一种低温多晶硅薄膜晶体管及其制造方法，能够有效增大沟道宽度，从而增大薄膜晶体管的宽长比和开口率，且结构简单，易于实施。The technical problem to be solved by the present invention is to provide a low-temperature polysilicon thin film transistor and its manufacturing method, which can effectively increase the channel width, thereby increasing the aspect ratio and aperture ratio of the thin film transistor, and has a simple structure and is easy to implement.

本发明为解决上述技术问题而采用的技术方案是提供一种低温多晶硅薄膜晶体管，包括栅极、源极和漏极，所述源极和漏极之间有沟道隔开，所述栅极和源极、漏极之间形成有多晶硅硅岛图案，其中，所述沟道处的多晶硅硅岛图案上至少有一个凹槽从而形成立体沟道，所述凹槽的深度小于沟道的深度。The technical scheme adopted by the present invention to solve the above-mentioned technical problems is to provide a low-temperature polysilicon thin film transistor, comprising a gate, a source and a drain, the source and the drain are separated by a channel, and the gate A polysilicon island pattern is formed between the source electrode and the drain electrode, wherein there is at least one groove on the polysilicon island pattern at the channel to form a three-dimensional channel, and the depth of the groove is smaller than the depth of the channel .

本发明为解决上述技术问题还提供一种低温多晶硅薄膜晶体管制造方法，如下步骤：首先在玻璃基板上使用化学气相沉积方法依次沉积一层缓冲层和一非晶硅层，采用准分子激光退火或固相结晶方法将非晶硅层晶化为多晶硅层；用第一掩模板，通过光刻在多晶硅层上形成光刻胶图案，所述第一掩模板为多灰阶掩模板，在沟道区域形成第一高度光刻胶层和第二高度光刻胶层，所述第一高度小于第二高度；使用光刻胶图案，通过第一次化学干法刻蚀工序形成包括沟道、源/漏极接触区在内的多晶硅硅岛图案；去除具有第一高度的光刻胶；然后通过第二次化学干法刻蚀工序形成立体沟道图案；在具有硅岛图案的玻璃基板上继续沉积栅极绝缘层和第一金属层，然后经过光刻以及刻蚀工序形成栅极金属图案；在具有栅极金属图案的玻璃基板表面上，再沉积一介电层；接着利用光刻和蚀刻工序在源/漏极接触区上方形成接触孔；最后在玻璃基板表面上沉积第二金属层，接着利用光刻及刻蚀工序，形成源极和漏极。In order to solve the above-mentioned technical problems, the present invention also provides a method for manufacturing a low-temperature polysilicon thin-film transistor. The steps are as follows: firstly, a buffer layer and an amorphous silicon layer are sequentially deposited on a glass substrate by chemical vapor deposition, and an excimer laser annealing or The solid-phase crystallization method crystallizes the amorphous silicon layer into a polysilicon layer; using a first mask to form a photoresist pattern on the polysilicon layer by photolithography, the first mask is a multi-gray scale mask, and the channel A first-height photoresist layer and a second-height photoresist layer are formed in the region, and the first height is smaller than the second height; using the photoresist pattern, the first chemical dry etching process is used to form a channel, a source / polysilicon island pattern within the drain contact region; remove the photoresist with the first height; then form a three-dimensional channel pattern through the second chemical dry etching process; continue on the glass substrate with the silicon island pattern Deposit the gate insulating layer and the first metal layer, and then form the gate metal pattern through photolithography and etching processes; deposit a dielectric layer on the surface of the glass substrate with the gate metal pattern; then use photolithography and etching The process forms a contact hole above the source/drain contact area; finally, deposits a second metal layer on the surface of the glass substrate, and then uses photolithography and etching processes to form the source and drain.

上述的低温多晶硅薄膜晶体管制造方法，其中，所述栅极绝缘层为氧化硅层、氮化硅层或复合绝缘层。In the above method for manufacturing a low-temperature polysilicon thin film transistor, the gate insulating layer is a silicon oxide layer, a silicon nitride layer or a composite insulating layer.

上述的低温多晶硅薄膜晶体管制造方法，其中，所述第一金属层和第二金属层为一铝层、一钨层、一铬层或金属化合物导电层。In the manufacturing method of the above low-temperature polysilicon thin film transistor, wherein, the first metal layer and the second metal layer are an aluminum layer, a tungsten layer, a chromium layer or a metal compound conductive layer.

上述的低温多晶硅薄膜晶体管制造方法，其中，所述介电层为氧化硅或氮化硅。In the above method for manufacturing a low temperature polysilicon thin film transistor, the dielectric layer is silicon oxide or silicon nitride.

本发明对比现有技术有如下的有益效果：本发明提供的低温多晶硅薄膜晶体管及其制造方法，通过衍射曝光在沟道处的多晶硅硅岛图案上形成立体沟道，有效增大沟道宽度，从而增大薄膜晶体管的宽长比和开口率，且结构简单，易于实施。Compared with the prior art, the present invention has the following beneficial effects: the low-temperature polysilicon thin film transistor and its manufacturing method provided by the present invention form a three-dimensional channel on the polysilicon island pattern at the channel by diffraction exposure, effectively increasing the channel width, Therefore, the aspect ratio and aperture ratio of the thin film transistor are increased, and the structure is simple and easy to implement.

附图说明Description of drawings

图1为一种低温多晶硅薄膜晶体管平面示意图；1 is a schematic plan view of a low-temperature polysilicon thin film transistor;

图2为现有一种低温多晶硅薄膜晶体管沿A-A线截面图；Fig. 2 is a cross-sectional view along line A-A of an existing low-temperature polysilicon thin film transistor;

图3为本发明低温多晶硅薄膜晶体管沿A-A线截面图；3 is a cross-sectional view along line A-A of a low-temperature polysilicon thin film transistor of the present invention;

图4A为现有低温多晶硅薄膜晶体管沟道宽度示意图；FIG. 4A is a schematic diagram of the channel width of an existing low-temperature polysilicon thin film transistor;

图4B为本发明低温多晶硅薄膜晶体管沟道宽度示意图；FIG. 4B is a schematic diagram of the channel width of the low-temperature polysilicon thin film transistor of the present invention;

图5A为本发明形成缓冲层示意图；FIG. 5A is a schematic diagram of forming a buffer layer in the present invention;

图5B为本发明形成非晶硅层示意图；5B is a schematic diagram of forming an amorphous silicon layer according to the present invention;

图5C为本发明形成多晶硅半导体层示意图；5C is a schematic diagram of forming a polysilicon semiconductor layer according to the present invention;

图5D为本发明多晶硅光刻胶图案形成示意图；5D is a schematic diagram of forming a polysilicon photoresist pattern according to the present invention;

图5E为本发明多晶硅图案形成示意图；FIG. 5E is a schematic diagram of forming a polysilicon pattern according to the present invention;

图5F为本发明灰化工艺后光刻胶形状示意图；5F is a schematic diagram of the shape of the photoresist after the ashing process of the present invention;

图5G为本发明立体沟道形成示意图；Fig. 5G is a schematic diagram of the formation of the three-dimensional channel of the present invention;

图5H为本发明形成栅极绝缘层示意图；FIG. 5H is a schematic diagram of forming a gate insulating layer according to the present invention;

图5I为本发明形成栅极金属层示意图；5I is a schematic diagram of forming a gate metal layer according to the present invention;

图5J为本发明形成栅极图案示意图；FIG. 5J is a schematic diagram of forming a gate pattern according to the present invention;

图5K为本发明形成介电层和源/漏接触孔示意图；FIG. 5K is a schematic diagram of forming a dielectric layer and a source/drain contact hole according to the present invention;

图5L为本发明形成源/漏金属图案示意图。5L is a schematic diagram of forming a source/drain metal pattern according to the present invention.

 the

图中：In the picture:

1 缓冲层               2’非晶硅层           2 多晶硅层1 buffer layer 2'amorphoussilicon layer 2 polysilicon layer

3 栅绝缘层            4 介电层              5 光刻胶图案3Gate insulating layer 4Dielectric layer 5 Photoresist pattern

6 掩膜板              21 凹槽               31 栅极6mask plate 21groove 31 gate

41 源极                42 漏极。41Source 42 Drain.

 the

具体实施方式Detailed ways

下面结合附图和实施例对本发明作进一步的描述。The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

图3为本发明低温多晶硅薄膜晶体管沿A-A线截面图；图4为本发明与现有一种低温多晶硅薄膜晶体管沟道宽度对比示意图。FIG. 3 is a cross-sectional view along the A-A line of the low-temperature polysilicon thin film transistor of the present invention; FIG. 4 is a schematic diagram of a channel width comparison between the present invention and the existing low-temperature polysilicon thin film transistor.

请参见图3、图4A和图4B，本发明提供的低温多晶硅薄膜晶体管包括栅极31、源极41和漏极42，所述源极41和漏极42之间有沟道隔开，所述栅极31和源极41、漏极42之间形成有多晶硅硅岛图案，其中，所述沟道处的多晶硅硅岛图案上至少有一个凹槽21从而形成立体沟道，所述凹槽21的深度小于沟道的深度。本发明形成的立体薄膜晶体管，沟道宽度增加了立体沟道侧壁的高度（L2+L4），长度L1+L3+L5仍等于现有的长度L；当采用N个凹槽/突起形状时，增加的沟道宽度即为N*（L2+L4），N为自然数，从而明显增大宽长比。凹槽/突起的数目最少为一个，上限由沟道宽度、曝光机分辨率和MASK的制作精度共同决定；凹槽/突起的深度/高度由沟道的深度决定，可以略小于沟道的深度。Referring to FIG. 3, FIG. 4A and FIG. 4B, the low-temperature polysilicon thin film transistor provided by the present invention includes agate 31, asource 41 and adrain 42, and thesource 41 and thedrain 42 are separated by a channel, so A polysilicon island pattern is formed between thegate 31, thesource 41, and thedrain 42, wherein at least onegroove 21 is formed on the polysilicon island pattern at the channel to form a three-dimensional channel, and the groove The depth of 21 is smaller than the depth of the trench. For the three-dimensional thin film transistor formed by the present invention, the channel width increases the height (L2+L4) of the sidewall of the three-dimensional channel, and the length L1+L3+L5 is still equal to the existing length L; when N grooves/protrusions are used , the increased channel width is N*(L2+L4), where N is a natural number, thus significantly increasing the aspect ratio. The number of grooves/protrusions is at least one, and the upper limit is determined by the width of the channel, the resolution of the exposure machine and the manufacturing accuracy of MASK; the depth/height of the grooves/protrusions is determined by the depth of the channel, which can be slightly smaller than the depth of the channel .

下面详细介绍本发明提供的低温多晶硅薄膜晶体管制造方法：The manufacturing method of the low-temperature polysilicon thin film transistor provided by the present invention is introduced in detail below:

如图5A所示，首先在阵列基板（玻璃）上使用化学气相沉积（CVD）方法沉积一层缓冲层1；如图5B所示，在缓冲层1上使用化学气相沉积（CVD）方法沉积非晶硅层2’；如图5C所示，采用准分子激光退火（ELA）或固相结晶（SPC）方法将非晶硅晶化为多晶硅层2。As shown in Figure 5A, abuffer layer 1 is first deposited on the array substrate (glass) by chemical vapor deposition (CVD); as shown in Figure 5B, a non- Acrystalline silicon layer 2 ′; as shown in FIG. 5C , the amorphous silicon is crystallized into apolycrystalline silicon layer 2 by excimer laser annealing (ELA) or solid phase crystallization (SPC).

如图5D所示，用第一掩模板6，通过光刻在多晶硅层2上形成光刻胶图案5。第一掩模板为多灰阶光掩膜板，可分为Gray-tone mask和Half tone mask两种。 Gray-tone mask是制作出曝光机解析度以下的微缝，再藉由此微缝部位遮住一部份的光源，以达成半曝光的效果。另一方面，Half tone mask是利用「半透过」的膜，来进行半曝光。因为以上两种方式皆是在１次的曝光过程后即可呈现出「曝光部分」「半曝光部分」及「未曝光部分」的３种的曝光层次，故在显影后能够形成２种厚度的光刻胶（感光剂）；本发明在沟道区域形成第一高度光刻胶层和第二高度光刻胶层，所述第一高度小于第二高度。As shown in FIG. 5D , aphotoresist pattern 5 is formed on thepolysilicon layer 2 by photolithography using thefirst mask 6 . The first mask is a multi-grayscale photomask, which can be divided into Gray-tone mask and Half tone mask. Gray-tone mask is to make micro-slits below the resolution of the exposure machine, and then use the micro-slits to cover part of the light source to achieve a half-exposure effect. On the other hand, half tone mask uses a "half-transmissive" film for half exposure. Because the above two methods can present three kinds of exposure layers of "exposed part", "semi-exposed part" and "unexposed part" after one exposure process, so two kinds of thickness can be formed after development. Photoresist (photosensitive agent); the present invention forms a photoresist layer with a first height and a photoresist layer with a second height in the channel region, and the first height is smaller than the second height.

如图5E所示，使用光刻胶图案，通过化学干法刻蚀（CDE）工序形成包括沟道、源/漏极接触区在内的多晶硅硅岛图案。As shown in FIG. 5E , using a photoresist pattern, a polysilicon island pattern including a channel and source/drain contact regions is formed through a chemical dry etching (CDE) process.

如图5F所示，刻蚀完成后，对多晶硅硅岛上部的光刻胶进行灰化工序，具有第一高度的光刻胶被去除，得到如图所示的光刻胶图案，形成至少一个沟道凹槽21。As shown in Figure 5F, after the etching is completed, the photoresist on the upper part of the polysilicon island is ashed, and the photoresist with the first height is removed to obtain the photoresist pattern as shown in the figure, forming at least onechannel groove 21 .

如图5G所示通过第二次化学干法刻蚀（CDE）工序形成本发明所需要的立体沟道图案。As shown in FIG. 5G , the three-dimensional channel pattern required by the present invention is formed through the second chemical dry etching (CDE) process.

如图5H所示，通过化学气相沉积（CVD）方法在具有硅岛图案的玻璃基板上沉积栅极绝缘层3，如氧化硅层、氮化硅层或复合绝缘层；As shown in FIG. 5H, agate insulating layer 3, such as a silicon oxide layer, a silicon nitride layer or a composite insulating layer, is deposited on a glass substrate having a silicon island pattern by a chemical vapor deposition (CVD) method;

如图5I所示，通过物理气相沉积（PVD）方法在绝缘层上形成一金属层，该金属层可以是一铝层、一钨层、一铬层或其他金属及金属化合物导电层, 所述第一金属层经过光刻以及刻蚀工序后形成栅极31金属图案。As shown in Figure 5I, a metal layer is formed on the insulating layer by physical vapor deposition (PVD), and the metal layer can be an aluminum layer, a tungsten layer, a chromium layer or other metal and metal compound conductive layers, said The metal pattern of thegate 31 is formed after the first metal layer undergoes photolithography and etching processes.

图5J～图5L为图1中沿B-B线所形成的截面图，图5I形成的第一金属层经过光刻以及刻蚀工序后形成栅极31金属图案。FIGS. 5J-5L are cross-sectional views along the line B-B in FIG. 1 . The metal pattern of thegate 31 is formed after the first metal layer formed in FIG. 5I undergoes photolithography and etching processes.

如图5K所示，在具有栅极金属图案的玻璃基板表面上，再沉积一介电层4，该介电层4的材料可以为氧化硅或氮化硅；接着利用光刻和蚀刻工序在源极欧姆接触区域以及漏极欧姆区域的上方的介电层以及绝缘层之内分别形成一直达源极的接触孔以及漏极的接触孔。As shown in FIG. 5K, on the surface of the glass substrate with the gate metal pattern, adielectric layer 4 is deposited again, and the material of thedielectric layer 4 can be silicon oxide or silicon nitride; A contact hole reaching the source and a drain contact hole are respectively formed in the dielectric layer and the insulating layer above the source ohmic contact region and the drain ohmic region.

如图5L所示，最后在玻璃基板表面上沉积第二金属层，如一铝层、一钨层、一铬层或其他金属单层或复合多层导电层；接着利用光刻及刻蚀工序，形成源极41和漏极42，这样就可以把信号从源极电连接至漏极，完成整个低温多晶硅薄膜晶体管的制造过程。As shown in FIG. 5L, finally deposit a second metal layer on the surface of the glass substrate, such as an aluminum layer, a tungsten layer, a chromium layer or other metal single-layer or composite multi-layer conductive layer; then use photolithography and etching processes, Thesource 41 and thedrain 42 are formed, so that the signal can be electrically connected from the source to the drain, and the entire manufacturing process of the low-temperature polysilicon thin film transistor is completed.

虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的修改和完善，因此本发明的保护范围当以权利要求书所界定的为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (5)

Translated fromChinese

1.一种低温多晶硅薄膜晶体管，包括栅极、源极和漏极，所述源极和漏极之间有沟道隔开，所述栅极和源极、漏极之间形成有多晶硅硅岛图案，其特征在于，所述沟道处的多晶硅硅岛图案上至少有一个凹槽从而形成立体沟道，所述凹槽的深度小于沟道的深度。1. A low-temperature polysilicon thin-film transistor, comprising a gate, a source and a drain, separated by a channel between the source and the drain, and polysilicon is formed between the gate and the source and the drain The island pattern is characterized in that there is at least one groove on the polysilicon island pattern at the channel to form a three-dimensional channel, and the depth of the groove is smaller than the depth of the channel.2.一种如权利要求1所述的低温多晶硅薄膜晶体管制造方法，其特征在于，包括如下步骤：2. A method for manufacturing a low-temperature polysilicon thin film transistor as claimed in claim 1, comprising the steps of:首先在玻璃基板上使用化学气相沉积方法依次沉积一层缓冲层和一非晶硅层，采用准分子激光退火或固相结晶方法将非晶硅层晶化为多晶硅层；First, a buffer layer and an amorphous silicon layer are sequentially deposited on the glass substrate by chemical vapor deposition, and the amorphous silicon layer is crystallized into a polysilicon layer by excimer laser annealing or solid-phase crystallization;用第一掩模板，通过光刻在多晶硅层上形成光刻胶图案，所述第一掩模板为多灰阶掩模板，在沟道区域形成第一高度光刻胶层和第二高度光刻胶层，所述第一高度小于第二高度；Form a photoresist pattern on the polysilicon layer by photolithography with a first mask, the first mask is a multi-grayscale mask, and form a first-level photoresist layer and a second-level photoresist layer in the channel region an adhesive layer, the first height being less than the second height;使用光刻胶图案，通过第一次化学干法刻蚀工序形成包括沟道、源/漏极接触区在内的多晶硅硅岛图案；去除具有第一高度的光刻胶；然后通过第二次化学干法刻蚀工序形成立体沟道图案；Using the photoresist pattern, form the polysilicon island pattern including the channel, source/drain contact area through the first chemical dry etching process; remove the photoresist with the first height; then pass the second The chemical dry etching process forms a three-dimensional channel pattern;在具有硅岛图案的玻璃基板上继续沉积栅极绝缘层和第一金属层，然后经过光刻以及刻蚀工序形成栅极金属图案；Continue to deposit the gate insulating layer and the first metal layer on the glass substrate with the silicon island pattern, and then form the gate metal pattern through photolithography and etching processes;在具有栅极金属图案的玻璃基板表面上，再沉积一介电层；接着利用光刻和蚀刻工序在源/漏极接触区上方形成接触孔；On the surface of the glass substrate with the gate metal pattern, deposit a dielectric layer; then use photolithography and etching to form a contact hole above the source/drain contact region;最后在玻璃基板表面上沉积第二金属层，接着利用光刻及刻蚀工序，形成源极和漏极。Finally, a second metal layer is deposited on the surface of the glass substrate, and then a source electrode and a drain electrode are formed by using photolithography and etching processes.3.如权利要求2所述的低温多晶硅薄膜晶体管制造方法，其特征在于，所述栅极绝缘层为氧化硅层、氮化硅层或复合绝缘层。3. The method for manufacturing a low-temperature polysilicon thin film transistor according to claim 2, wherein the gate insulating layer is a silicon oxide layer, a silicon nitride layer or a composite insulating layer.4.如权利要求2所述的低温多晶硅薄膜晶体管制造方法，其特征在于，所述第一金属层和第二金属层为一铝层、一钨层、一铬层或金属化合物导电层。4 . The method for manufacturing a low temperature polysilicon thin film transistor according to claim 2 , wherein the first metal layer and the second metal layer are an aluminum layer, a tungsten layer, a chromium layer or a metal compound conductive layer.5.如权利要求2所述的低温多晶硅薄膜晶体管制造方法，其特征在于，所述介电层为氧化硅或氮化硅。5. The method for manufacturing a low temperature polysilicon thin film transistor according to claim 2, wherein the dielectric layer is silicon oxide or silicon nitride.

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