The manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor DRAMTechnical field
The present invention relates to field of semiconductor manufacture, particularly relate to the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor DRAM.
Background technology
In semiconductor fabrication, along with semiconductor integrated circuit enters the epoch (Generation) of more high-order, prepare difficulty with the capacitor of high density of integration, Low dark curient constantly to increase, tradition 1 transistor 1 electric capacity (1 Transistor 1 Capacitance, being called for short ITIC) dynamic random access memory (Dynamic Random Access Memory, be called for short DRAM) institute's facing challenges of structure is increasing.Therefore, at present to the 2T(Transistor that may substitute 1T1C structure DRAM) even the research of the zero capacitance dynamic random access memory (Zero-Capacitor RAM or Capacitor less RAM is called for short Z-RAM) of 1T structure is more and more popular.
Because the storage density of DRAM can not only be doubled by Z-RAM, the buffer memory capacity of processor can also be improved 5 times, and without the need to using special material or more advanced manufacturing process, so Z-RAM has a good application prospect.
United States Patent (USP) (patent No. US20100329043.A1, Two-Transistor Floating-Body Dynamic Memory Cell) disclose the modified version of a kind of elemental floating body (Floating Body/Gate Cell, be called for short FBGC) 2T DRAM structure.
Be illustrated in figure 1 for the FBGC cellular construction figure of the modified version of the 2T DRAM structure of NMOS, based on silicon-on-insulator (Silicon On Insulator, be called for short SOI) dual-MOS structure, adopt part depletion (Partial Depletion, be called for short PD) technique or fully-depleted (Full Depletion is called for short FD) technique preparation.
Wherein, the drain terminal of T1 meets bit line 1 (Bitline1, be called for short BL1), source is P+ but not N+, source connects the grid G 2 of T2, T1 is now tunnel (tunneling) field-effect transistor (Field Effect Transistor in fact, be called for short FET), it utilizes band-to-band-tunneling (Band to Band Tunneling, be called for short BTB tunneling) or grid induce drain leakage effect (Gate-induced Drain Leakage, be called for short GIDL) positive charge (charging) is filled to the buoyancy aid (Floating Body) of T1 write (write) " 1 ", PN junction forward bias electric discharge (discharging) between the body source of T1 is utilized to carry out writing (write) " 0 ", and the source of T1 uses P+ to be conducive to T1 source and directly to connect grid, eliminate body contact (Body Contact) of T1 simultaneously, thus increase integration density." 0 " and " 1 " read voltage that (read) result is bit line 2 (Bitline2 is called for short BL2) or results of weak current.
Be illustrated in figure 2 for a kind of mode of operation of the FBGC cellular construction of NMOS, the people such as Zhichao Lu are described in detail this mode of operation in " a kind of senior elemental floating body DRAM unit (A Simplified Superior Floating-Body/Gate DRAM Cell) of simplification; electronic device (Electron Devices); IEEE ELECTRON DEVICE LETTERS; VOL. 30; NO. 3, MARCH 2009 ".Wherein the drain terminal of T1 and grid have the crossover area (overlap) of 20-30nm.As shown in Figures 3 and 4, when writing (write) " 1 ", WL negative voltage, BL1 positive voltage, due to the excessive crossover area of T1 drain-gate (overlap), GIDL effect increases greatly, thus accelerates the charging to T1 tagma.And when writing (write) " 0 ", WL positive voltage, BL1 negative voltage, T1 body drain PN junction positively biased, realizes the electric discharge to T1 tagma.Wherein, the grid of T2 is driven by the source volume charge of T1, reads (read) action and is realized by the current signal or voltage signal reading T2 drain terminal.
Although above-mentioned FBGC 2T DRAM structure has novelty very much, but do not solve manufacturability (Design for Manufacturability, be called for short DFM) problem, namely how in technique, effectively to realize by autoregistration drain-gate crossover area (overlap) elongation property being different from stand CMOS.
Summary of the invention
The invention discloses the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor DRAM, the two transistor DRAM structure adopting post tensioned unbonded prestressed concrete high-dielectric constant metal grid technique to prepare at least comprises a first transistor and a transistor seconds, and sample grid are all filled with in the grid groove that first, second transistor is comprised separately, after sample grid are eat-back, high dielectric layer and metal oxide dielectric materials layer is upwards disposed with in the bottom of grid groove, wherein, comprise the following steps:
Step S1, spin coating photoresist in two quartz crystal pipe DRAM structures, removes the photoresist on the first transistor structural region, forms photoresistance after exposure, development;
Step S2, angular slope ion implantation technology is carried out in the grid groove exposed from photoresistance, near one end that the first transistor drains, work function adjustment is carried out to the metal oxide dielectric materials layer in the first transistor grid groove, makes to drain identical doping type near the region transoid Cheng Yuqi of drain electrode in the channel region of the first transistor.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the high dielectric layer of first and second transistor gate trench bottom and the preparation before the preparation of filling sample grid of metal oxide dielectric materials layer, or prepare after sample grid eat-back.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, alternatively, wherein, can be provided with thin oxide layer between first and second transistor height dielectric layer and its raceway groove.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the source electrode of the first transistor is P+ type, and its drain electrode is N+ type, and the source-drain electrode of transistor seconds is N+ type.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the ion that angular slope ion implantation technology is injected is the ion that work function is less, as the ion being base with elements such as Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, Th.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the source electrode of the first transistor is N+ type, and drain as P+ type, raceway groove is N-type; The source-drain electrode of transistor seconds is P+ type, and raceway groove is N-type.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the ion that angular slope ion implantation technology is injected is the ion that work function is larger, as the ion being base with elements such as B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, also comprises: adopt the silicon post tensioned unbonded prestressed concrete high-dielectric constant metal grid technique in dielectric substrate after ion implantation, complete the preparation of two transistor DRAM device; Wherein, the first transistor source electrode is connected with transistor seconds grid, transistor seconds source ground.
The present invention also discloses the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor DRAM, the two transistor DRAM structure adopting post tensioned unbonded prestressed concrete high-dielectric constant metal grid technique to prepare at least comprises a first transistor and a transistor seconds, and sample grid are all filled with in the grid groove that first, second transistor is comprised separately, after sample grid are eat-back, thin oxide layer is retained in the bottom of grid groove, wherein, comprise the following steps:
Step S1, spin coating photoresist in two quartz crystal pipe DRAM structures, removes the photoresist on the first transistor structural region, forms photoresistance after exposure, development;
Step S2, carries out angular slope ion implantation technology in the grid groove exposed from photoresistance, makes to drain identical doping type near the region transoid Cheng Yuqi of drain electrode in the channel region of the first transistor, and activates the ion injected.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, activates the ion of injection in described step S2, namely adopt quick thermal treatment process, peak value annealing process or flash anneal technique to activate the ion injected.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the source electrode of the first transistor is P+ type, and drain as N+ type, raceway groove is P type; The source-drain electrode of transistor seconds is N+ type, and raceway groove is P type.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the ion that the ion that angular slope ion implantation technology is injected is is base with elements such as P or As.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the source electrode of the first transistor is N+ type, and drain as P+ type, raceway groove is N-type; The source-drain electrode of transistor seconds is P+ type, and raceway groove is N-type.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, the ion of described ion implantation is with B, BF2, BF or ln etc. be the ion of base.
The manufacture method of above-mentioned post tensioned unbonded prestressed concrete two transistor DRAM, wherein, also comprises: adopt the silicon post tensioned unbonded prestressed concrete high-dielectric constant metal grid technique in dielectric substrate after ion implantation, complete the preparation of two transistor DRAM device; Wherein, the first transistor source electrode is connected with transistor seconds grid, transistor seconds source ground.
In sum, owing to have employed technique scheme, the present invention proposes the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor DRAM, regulated by work function or ion implantation compensate for process, solve manufacturability (the Design for Manufacturability of FBGC 2T DRAM structure, be called for short DFM) problem, namely regulated by work function or ion implantation compensate for process, to realize by autoregistration drain-gate crossover area (overlap) elongation property being different from stand CMOS in technique, and technique is simple, be easy to realization operation.
Accompanying drawing explanation
Fig. 1 is FBGC 2T DRAM structural representation in background technology of the present invention;
Fig. 2 is the structural representation of a kind of mode of operation of FBGC 2T DRAM structure in background technology of the present invention;
Fig. 3-4 is emulation schematic diagrames of a kind of mode of operation of FBGC 2T DRAM structure in background technology of the present invention;
Fig. 5-8 is schematic flow sheets of the embodiment of the present invention one;
Fig. 9-12 is schematic flow sheets of the embodiment of the present invention two;
Figure 13-16 is schematic flow sheets of the embodiment of the present invention three;
Figure 17-20 is schematic flow sheets of the embodiment of the present invention four.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Embodiment one:
As viewed in figures 5-8, for NMOS, this mode of operation is adopted to be regulated by work function, the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor of the present invention DRAM, adopt post tensioned unbonded prestressed concrete (Gate-Last) high-dielectric constant metal grid (High-K Metal-gate, being called for short HKMG) two transistor (2T) the DRAM structure 1 prepared of technique comprises the first transistor 101 and transistor seconds 102, and at the first transistor 101 and respective the comprised grid groove 109 of transistor seconds 102, sample grid are all filled with in 110, after sample grid are eat-back, at grid groove 109, the bottom of 110 is upwards disposed with high dielectric layer 1032, 1042with metal oxide dielectric materials layer 1031, 1041.
The source electrode 107 of the first transistor 101 is p+ type, and drain electrode 108 is n+ type, and the bottom of its grid groove 109 is provided with the thin oxide layer (Dummy Oxide) 105 be positioned at above its raceway groove 111, by metal oxide dielectric materials layer (Cap layer) 1031with high dielectric layer (HK layer) 1032the dielectric layer (Dielectric layer) 103 formed, thin oxide layer 105 is positioned at raceway groove 111 and high dielectric layer 1032between, metal oxide dielectric materials layer 1031cover high dielectric layer 1032.Transistor seconds 102 is NMOS tube, and the bottom of its grid groove 110 is provided with the thin oxide layer (Dummy Oxide) 106 be positioned at above its raceway groove 112 equally, by metal oxide dielectric materials layer (Cap layer) 1041with high dielectric layer (HK layer) 1042the dielectric layer (Dielectric layer) 104 formed, thin oxide layer 106 is positioned at raceway groove 112 and high dielectric layer 1042between, metal oxide dielectric materials layer 1041cover high dielectric layer 1042.
Wherein, dielectric layer 103,104 preparation before sample grid preparation technology or after grid groove 109,110 is formed.
Then, spin coating photoresist, exposure, the photoresist on the first transistor 101 region is removed after development, after forming the photoresistance 113 only covering transistor seconds 102 region, carry out angular slope ion implantation technology 114, inject the ion that work function is less, as with Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, the elements such as Th are the ion of base, with the metal oxide dielectric materials layer 103 bottom the grid groove 109 of the first transistor 1011upper near its 108 parts formation work function adjustment region 103 that drain4with residual metallic oxide dielectric material layer 1033, the raceway groove 111 making to be arranged in its drain electrode 108 close below grid groove 109 when not adding grid voltage forms opposite-type region 115, i.e. work function adjustment region 1034relative to residual metallic oxide dielectric material layer 1033work function less, opposite-type region 115 is drain-gate crossover area, and the same with drain electrode 108 be n+ type.
Afterwards, remove photoresistance 113, continue to adopt silicon post tensioned unbonded prestressed concrete technique high-dielectric constant metal grid (the SOI Gate Last HKMG) preparation technology in dielectric substrate, complete the preparation of 2T structure DRAM device.
Finally, the source electrode 116 of the first transistor 101 of the 2T structure DRAM device of preparation is connected with the grid 118 of its transistor seconds 102, source electrode 117 ground connection of transistor seconds.
Embodiment two:
As shown in figs9-12, for PMOS, above-mentioned mode of operation is adopted to be regulated by work function, the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor of the present invention DRAM, the two transistor DRAM structure 2 adopting post tensioned unbonded prestressed concrete high-dielectric constant metal grid technique to prepare comprises the first transistor 201 and transistor seconds 202, and sample grid are all filled with in the first transistor 201 and respective the comprised grid groove 209,210 of transistor seconds 202, after sample grid are eat-back, be upwards disposed with high dielectric layer 203 in the bottom of grid groove 209,2102, 2042with metal oxide dielectric materials layer 2031, 2041.
The source electrode 207 of the first transistor 201 is n+ type, and drain electrode 208 is p+ type, and the bottom of its grid groove 209 is provided with the thin oxide layer (Dummy Oxide) 205 be positioned at above its raceway groove 211, by metal oxide dielectric materials layer (Cap layer) 2031with high dielectric layer (HK layer) 2032the dielectric layer (Dielectric layer) 203 formed, thin oxide layer 205 is positioned at raceway groove 211 and high dielectric layer 2032between, metal oxide dielectric materials layer 2031cover high dielectric layer 2032.Transistor seconds 202 is PMOS, and the bottom of its grid groove 210 is provided with the thin oxide layer (Dummy Oxide) 206 be positioned at above its raceway groove 212 equally, by metal oxide dielectric materials layer (Cap layer) 2041with high dielectric layer (HK layer) 2042the dielectric layer (Dielectric layer) 204 formed, thin oxide layer 206 is positioned at raceway groove 212 and high dielectric layer 2042between, metal oxide dielectric materials layer 2041cover high dielectric layer 2042.
Wherein, dielectric layer 203,204 preparation before sample grid preparation technology or after grid groove 209,210 is formed.
Then, spin coating photoresist, the photoresist on the first transistor 201 region is removed after exposure, development, after forming the photoresistance 213 only covering transistor seconds 202 region, carry out angular slope ion implantation technology 214, inject the ion that work function is larger, as the ion being base with elements such as B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po, with the metal oxide dielectric materials layer 203 bottom the grid groove 209 of the first transistor 2011upper near its 208 parts formation work function adjustment region 203 that drain4with residual metallic oxide dielectric material layer 2033, the raceway groove 211 making to be arranged in its drain electrode 208 close below grid groove 209 when not adding grid voltage forms opposite-type region 215, i.e. work function adjustment region 2034relative to residual metallic oxide dielectric material layer 2033work function comparatively large, opposite-type region 215 is drain-gate crossover area, and the same with drain electrode 208 be p+ type.
Afterwards, remove photoresistance 213, continue to adopt silicon post tensioned unbonded prestressed concrete technique high-dielectric constant metal grid (the SOI Gate Last HKMG) preparation technology in dielectric substrate, complete the preparation of 2T structure DRAM device.
Finally, the source electrode 216 of the first transistor 201 of the 2T structure DRAM device of preparation is connected with the grid 218 of its transistor seconds 202, source electrode 217 ground connection of transistor seconds.
In sum, owing to have employed technique scheme, the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor of the present invention DRAM, regulates drain-gate crossover area (overlap) elongation property to realize being different from stand CMOS in technique by autoregistration by work function.
Embodiment three:
As shown in figures 13-16, for NMOS, adopt above-mentioned mode of operation and ion implantation compensate for process, the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor of the present invention DRAM, adopt post tensioned unbonded prestressed concrete (Gate-Last) high-dielectric constant metal grid (High-K Metal-gate, being called for short HKMG) two transistor (2T) the DRAM structure 3 prepared of technique comprises the first transistor 301 and transistor seconds 302, and at the first transistor 301 and respective the comprised grid groove 309 of transistor seconds 302, sample grid are all filled with in 310, after sample grid are eat-back, at grid groove 309, the bottom of 310 retains thin oxide layer 303, 304.
The source electrode 305 of the first transistor 301 is p+ type, and drain electrode 306 is n+ type, and the bottom of its grid groove 309 remains with the thin oxide layer (Dummy Oxide) 303 be positioned at above its raceway groove 307, and thin oxide layer 303 covers on its raceway groove 307.Transistor seconds 302 is NMOS tube, and the bottom of its grid groove 310 remains with the thin oxide layer (Dummy Oxide) 304 be positioned at above its raceway groove 308, and thin oxide layer 304 covers on its raceway groove 308.
Then, spin coating photoresist, the photoresist on the first transistor 301 region is removed after exposure, development, after forming the photoresistance 311 only covering transistor seconds 302 region, carry out angular slope ion implantation technology 312, the ion that to inject with elements such as P, As be base, when not adding grid voltage, form opposite-type region 313 near raceway groove 307 region of drain electrode 306 under making grid, namely opposite-type region 313 is the same with drain electrode 306 is n+ type; Adopt quick thermal treatment process (Rapid Thermal Processor again, be called for short RTP), peak value annealing process (Spike Anneal) or flash anneal technique (Flash Anneal) activates the ion of above-mentioned injection, is finally formed as drain-gate crossover area to make opposite-type region 313.
Afterwards, remove photoresistance 311, continue to adopt silicon post tensioned unbonded prestressed concrete technique high-dielectric constant metal grid (the SOI Gate Last HKMG) preparation technology in dielectric substrate, complete the preparation of 2T structure DRAM device.
Finally, the source electrode 314 of the first transistor 301 of the 2T structure DRAM device of preparation is connected with the grid 315 of its transistor seconds 302, source electrode 316 ground connection of transistor seconds 302.
Embodiment four:
As shown in figures 17 to 20, for PMOS, adopt mode of operation two and ion implantation compensate for process, the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor of the present invention DRAM, adopt post tensioned unbonded prestressed concrete (Gate-Last) high-dielectric constant metal grid (High-K Metal-gate, being called for short HKMG) two transistor (2T) the DRAM structure 4 prepared of technique comprises the first transistor 401 and transistor seconds 402, and at the first transistor 401 and respective the comprised grid groove 409 of transistor seconds 402, sample grid are all filled with in 410, after sample grid are eat-back, at grid groove 409, the bottom of 410 retains thin oxide layer 403, 404.
The source electrode 405 of the first transistor 401 is n+ type, and drain electrode 406 is p+ type, and the bottom of its grid groove 409 remains with the thin oxide layer (Dummy Oxide) 403 be positioned at above its raceway groove 407, and thin oxide layer 403 covers on its raceway groove 407.Transistor seconds 402 is PMOS, and the bottom of its grid groove 410 remains with the thin oxide layer (Dummy Oxide) 404 be positioned at above its raceway groove 408, and thin oxide layer 404 covers on its raceway groove 408.
Then, spin coating photoresist, removes the photoresist on the first transistor 401 region, after forming the photoresistance 411 only covering transistor seconds 402 region, carries out angular slope ion implantation technology 412, inject with B, BF after exposure, development2, BF, ln etc. are the ion of base, when not adding grid voltage, form opposite-type region 413 under making grid near raceway groove 407 region of drain electrode 406, namely opposite-type region 413 be the same with drain electrode 406 is p+ type; Adopt quick thermal treatment process (Rapid Thermal Processor again, be called for short RTP), peak value annealing process (Spike Anneal) or flash anneal technique (Flash Anneal) activates the ion of above-mentioned injection, makes opposite-type region 413 finally be formed as drain-gate crossover area.
Afterwards, remove photoresistance 411, continue to adopt silicon post tensioned unbonded prestressed concrete technique high-dielectric constant metal grid (the SOI Gate Last HKMG) preparation technology in dielectric substrate, complete the preparation of 2T structure DRAM device.
Finally, the source electrode 414 of the first transistor 401 of the 2T structure DRAM device of preparation is connected with the grid 415 of its transistor seconds 402, source electrode 416 ground connection of transistor seconds 402.
In sum, owing to have employed technique scheme, the manufacture method of a kind of post tensioned unbonded prestressed concrete two transistor of the present invention DRAM, drain-gate crossover area (overlap) elongation property to realize being different from stand CMOS in technique by autoregistration is compensated by ion implantation, and technique is simple, be easy to realization operation.
Be described in detail specific embodiments of the invention above, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, equalization conversion done without departing from the spirit and scope of the invention and amendment, all should contain within the scope of the invention.