本申请基于且主张2010年9月21日申请的在先日本专利申请第2010-210476号的优先权，此申请案的全部内容以引用的方式并入本文。This application is based on and claims priority from prior Japanese Patent Application No. 2010-210476 filed on September 21, 2010, the entire contents of which are hereby incorporated by reference.
技术领域technical field
本发明的实施方式涉及一种半导体元件及该半导体元件的制造方法。Embodiments of the present invention relate to a semiconductor element and a method for manufacturing the semiconductor element.
背景技术Background technique
MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)或IGBT(Insulated Gate BipolarTransistor，绝缘栅双极型晶体管)等功率半导体元件具有高速开关(switching)特性、数十～数百伏特(V)的反向闭塞电压(blockingvoltage)(耐压)，从而被广泛用于家用电器、通信设备、车载电动机等的功率变换及控制中。而且，为了提高这些设备的效率并降低消耗功率，而要求半导体元件具有高耐压及低导通阻抗的特性。例如，在具备交替配置着p型及n型的半导体层的超结(superjunction)结构的半导体元件中，可同时实现高耐压与低导通阻抗。Power semiconductor components such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) have high-speed switching (switching) characteristics, tens to hundreds of volts ( V) reverse blocking voltage (blocking voltage) (withstand voltage), which is widely used in power conversion and control of household appliances, communication equipment, vehicle motors, etc. Furthermore, in order to improve the efficiency of these devices and reduce power consumption, semiconductor elements are required to have characteristics of high withstand voltage and low on-resistance. For example, in a semiconductor device having a superjunction structure in which p-type and n-type semiconductor layers are alternately arranged, high withstand voltage and low on-resistance can be simultaneously realized.
然而，存在如下问题：如果对超结结构施加了偏压，那么pn结的电容会急剧减少，半导体元件的输出电容大幅变化。即，具备超结结构的半导体元件的依赖于输出电容的开关噪声(switching noise)高。因此，需要能够增大输出电容而减小开关噪声的具备超结结构的半导体元件。However, there is a problem that when a bias voltage is applied to the superjunction structure, the capacitance of the pn junction decreases sharply, and the output capacitance of the semiconductor element greatly changes. That is, the semiconductor element having a super junction structure has high switching noise depending on the output capacitance. Therefore, there is a need for a semiconductor element having a super-junction structure capable of increasing output capacitance and reducing switching noise.
发明内容Contents of the invention
本发明的实施方式提供一种能够增大输出电容而减小开关噪声的具备超结结构的半导体元件及该半导体元件的制造方法。Embodiments of the present invention provide a semiconductor element having a super junction structure capable of increasing output capacitance and reducing switching noise, and a method of manufacturing the semiconductor element.
本发明的实施方式的半导体元件包括：第二半导体层，包含在沿着第一半导体层的主面的方向上交替设置的第一导电型的第一柱及第二导电型的第二柱；第一控制电极，填埋在从所述第二半导体层的表面向所述第一半导体层的方向设置的沟槽的内部；及第二控制电极，设置在所述第二半导体层上，且与所述第一控制电极相连。在除由所述第二控制电极覆盖的部分以外的所述第二半导体层的表面，设置着第二导电型的第一半导体区域，在所述第一半导体区域的表面，选择性地设置着与由所述第二控制电极覆盖的所述第二半导体层的表面相隔开的第一导电型的第二半导体区域。此外，与所述第二半导体区域相邻接的第二导电型的第三半导体区域选择性地设置在所述第一半导体区域的表面。The semiconductor element according to the embodiment of the present invention includes: a second semiconductor layer including first columns of the first conductivity type and second columns of the second conductivity type alternately arranged in a direction along the main surface of the first semiconductor layer; a first control electrode buried in a trench provided from the surface of the second semiconductor layer toward the first semiconductor layer; and a second control electrode provided on the second semiconductor layer, and connected to the first control electrode. On the surface of the second semiconductor layer except the portion covered by the second control electrode, a first semiconductor region of the second conductivity type is provided, and on the surface of the first semiconductor region, selectively A second semiconductor region of the first conductivity type spaced apart from the surface of the second semiconductor layer covered by the second control electrode. In addition, a third semiconductor region of the second conductivity type adjacent to the second semiconductor region is selectively provided on the surface of the first semiconductor region.
根据本发明的实施方式，能够提供一种能够增大输出电容而减小开关噪声的具备超结结构的半导体元件及该半导体元件的制造方法。According to the embodiments of the present invention, it is possible to provide a semiconductor element having a super junction structure capable of increasing output capacitance and reducing switching noise, and a method of manufacturing the semiconductor element.
附图说明Description of drawings
图1是表示第一实施方式的半导体元件的示意图。图1(a)是表示Ia-Ia剖面的结构的立体图，图1(b)是表示栅极电极的配置的俯视图。FIG. 1 is a schematic diagram showing a semiconductor element according to a first embodiment. FIG. 1( a ) is a perspective view showing the structure of the Ia-Ia cross section, and FIG. 1( b ) is a plan view showing the arrangement of the gate electrodes.
图2是表示第一实施方式的半导体元件的电压-电容特性的曲线图。FIG. 2 is a graph showing voltage-capacitance characteristics of the semiconductor element of the first embodiment.
图3(a)～图8(b)是示意性地表示第一实施方式的半导体元件的制造过程的剖面图。图3(a)～图8(b)中，各图的(a)表示图1(b)的Ia-Ia剖面的结构，各图的(b)表示图1(b)的IVb-IVb剖面的结构。3(a) to 8(b) are cross-sectional views schematically showing the manufacturing process of the semiconductor element of the first embodiment. In Fig. 3 (a) ~ Fig. 8 (b), (a) of each figure represents the structure of the Ia-Ia cross section of Fig. 1 (b), and (b) of each figure represents the IVb-IVb cross section of Fig. 1 (b) Structure.
图9是示意性地表示第一实施方式的变形例的半导体元件的结构的立体图。9 is a perspective view schematically showing the structure of a semiconductor element according to a modified example of the first embodiment.
图10是示意性地表示第一实施方式的另一变形例的半导体元件的结构的立体图。10 is a perspective view schematically showing the structure of a semiconductor element according to another modified example of the first embodiment.
图11是表示第一实施方式的变形例的栅极电极的配置的俯视图。11 is a plan view showing the arrangement of gate electrodes in a modified example of the first embodiment.
图12是表示具有图11(a)所示的栅极电极的半导体元件的示意图。图12(a)是示意性地表示半导体元件的结构的立体图，图12(b)是表示XIIb-XIIb剖面的结构的示意图。FIG. 12 is a schematic diagram showing a semiconductor element having the gate electrode shown in FIG. 11( a ). FIG. 12( a ) is a perspective view schematically showing the structure of a semiconductor element, and FIG. 12( b ) is a schematic view showing the structure of the XIIb-XIIb cross section.
图13是表示第二实施方式的半导体元件的结构的示意图。图13(a)是表示除源极电极及层间绝缘膜以外的半导体元件的芯片面的一部分的俯视图。图13(b)是示意性地表示半导体元件的结构的立体图。FIG. 13 is a schematic diagram showing the structure of a semiconductor element according to the second embodiment. FIG. 13( a ) is a plan view showing part of the chip surface of the semiconductor element except for the source electrode and the interlayer insulating film. Fig. 13(b) is a perspective view schematically showing the structure of a semiconductor element.
图14是示意性地表示比较例的半导体元件的立体图。FIG. 14 is a perspective view schematically showing a semiconductor element of a comparative example.
具体实施方式Detailed ways
以下，一边参照附图一边说明本发明的实施方式。另外，在以下的实施方式中，对附图中的同一部分标注同一编号并适当省略该部分的详细说明，对不同的部分适当地进行说明。以第一导电型为n型、第二导电型为p型来进行说明，但也可将第一导电型设为p型，将第二导电型设为n型。Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in the following embodiments, the same reference numerals are assigned to the same parts in the drawings, and detailed descriptions of these parts are appropriately omitted, and different parts are appropriately described. The first conductivity type is n-type and the second conductivity type is p-type for description, but the first conductivity type may be p-type and the second conductivity type may be n-type.
(第一实施方式)(first embodiment)
图1是表示本实施方式的半导体元件100的示意图。图1(a)是表示剖面结构的立体图，图1(b)是表示栅极电极12及15的配置的俯视图。图1(a)为了表示栅极电极12及15与n型源极区域7及p+接触区域8之间的配置关系，而以除去了层间绝缘膜23及源极电极19的状态来表示(参照图8)。FIG. 1 is a schematic diagram showing a semiconductor element 100 according to this embodiment. FIG. 1( a ) is a perspective view showing a cross-sectional structure, and FIG. 1( b ) is a plan view showing the arrangement of gate electrodes 12 and 15 . FIG. 1(a) shows the state in which the interlayer insulating film 23 and the source electrode 19 are removed in order to show the arrangement relationship between the gate electrodes 12 and 15, the n-type source region 7 and the p+ contact region 8. (Refer to Figure 8).
如图1(a)所示，半导体元件100包括：作为第一半导体层的n型漏极层2；作为第二半导体层的漂移层3；作为第一控制电极的栅极电极12，填埋在从漂移层3的表面向n型漏极层的方向设置的沟槽13的内部；及作为第二控制电极的栅极电极15，设置在漂移层3上。As shown in Figure 1 (a), the semiconductor element 100 includes: the n-type drain layer 2 as the first semiconductor layer; the drift layer 3 as the second semiconductor layer; the gate electrode 12 as the first control electrode, buried Inside the trench 13 provided from the surface of the drift layer 3 toward the n-type drain layer; and the gate electrode 15 as the second control electrode is provided on the drift layer 3 .
漂移层3包含在沿着n型漏极层2的主面2a的方向上交替设置的作为第一柱的n型柱4、及作为第二柱的p型柱5。Drift layer 3 includes n-type pillars 4 as first pillars and p-type pillars 5 as second pillars, which are alternately arranged along the main surface 2 a of n-type drain layer 2 .
栅极电极12隔着设置在沟槽13的内表面的作为第一绝缘膜的栅极绝缘膜11而填埋在沟槽13的内部。Gate electrode 12 is buried in trench 13 via gate insulating film 11 as a first insulating film provided on the inner surface of trench 13 .
栅极电极15隔着设置在漂移层3的表面的作为第二绝缘膜的栅极绝缘膜14而设置在漂移层3上。The gate electrode 15 is provided on the drift layer 3 via a gate insulating film 14 serving as a second insulating film provided on the surface of the drift layer 3 .
在漂移层3的表面的除由栅极电极15覆盖的部分以外的部分，设置着作为第一半导体区域的p型基极区域6。但也可以如图1所示，使沿着栅极电极15的p型基极区域6的外缘6a延伸到栅极电极15下方。A p-type base region 6 serving as a first semiconductor region is provided on a portion of the surface of the drift layer 3 other than the portion covered by the gate electrode 15 . However, as shown in FIG. 1 , the outer edge 6 a of the p-type base region 6 along the gate electrode 15 may extend below the gate electrode 15 .
此外，在p型基极区域6的表面设置着作为第二半导体区域的n型源极区域7。n型源极区域7与由栅极电极15覆盖的漂移层3的表面相隔开地设置。Furthermore, an n-type source region 7 serving as a second semiconductor region is provided on the surface of the p-type base region 6 . N-type source region 7 is provided at a distance from the surface of drift layer 3 covered by gate electrode 15 .
而且，作为第三半导体区域的p+接触区域8与n型源极区域7相邻接且选择性地设置在p型基极区域6的表面。n型源极区域7及p+接触区域8与未图示的源极电极19电连接。Furthermore, a p+ contact region 8 serving as a third semiconductor region is adjacent to the n-type source region 7 and is selectively provided on the surface of the p-type base region 6 . N-type source region 7 and p+ contact region 8 are electrically connected to unshown source electrode 19 .
本实施方式的半导体元件100中，通过对填埋在沟槽13内的栅极电极12施加栅极电压，经由形成在p型基极区域6与栅极绝缘膜11的界面的反型沟道，能够在与n型漏极层2电连接的作为第一主电极的漏极电极与作为第二主电极的源极电极19之间流通漏极电流。In the semiconductor element 100 of the present embodiment, when a gate voltage is applied to the gate electrode 12 buried in the trench 13, the inversion channel formed at the interface between the p-type base region 6 and the gate insulating film 11 , the drain current can flow between the drain electrode as the first main electrode electrically connected to the n-type drain layer 2 and the source electrode 19 as the second main electrode.
另一方面，设置在漂移层3上的栅极电极15如图1(a)中所示，n型源极区域7隔着p+接触区域8的一部分8a而与栅极电极15相隔开地设置。由此，能够成为如下结构：即便例如在栅极电极15下方形成的p型基极区域6的扩散部6a与栅极绝缘膜14的界面形成了反型沟道，漏极电流也不会流通到栅极电极15下方。而且，能够防止形成在栅极电极15下方的反型沟道的阈值电压变小而使漏极电流集中在栅极电极15。On the other hand, in the gate electrode 15 provided on the drift layer 3, asshown in FIG. ground setting. Thus, it is possible to obtain a structure in which, for example, even if an inversion channel is formed at the interface between the diffusion portion 6a of the p-type base region 6 formed below the gate electrode 15 and the gate insulating film 14, the drain current does not flow. to under the gate electrode 15. Furthermore, it is possible to prevent the drain current from concentrating on the gate electrode 15 because the threshold voltage of the inversion channel formed below the gate electrode 15 is reduced.
图1(b)是例示半导体元件100中的栅极电极12及15、与n型柱4及p型柱5的配置关系的俯视图。图1(a)所示的立体图的正面的剖面结构示意性地表示图1(b)中的Ia-Ia剖面。FIG. 1( b ) is a plan view illustrating an arrangement relationship between the gate electrodes 12 and 15 , and the n-type column 4 and the p-type column 5 in the semiconductor element 100 . The front cross-sectional structure of the perspective view shown in FIG. 1( a ) schematically shows the Ia-Ia cross-section in FIG. 1( b ).
例如，n型柱4及p型柱5能够设置成在沿着漏极层2的主面2a的方向上延伸的条纹状。而且，如图1(a)及(b)所示，栅极电极12能够沿着n型柱4及p型柱5的延伸方向而设置于在n型柱4的表面形成的沟槽13中。For example, n-type columns 4 and p-type columns 5 can be provided in stripes extending in a direction along main surface 2 a of drain layer 2 . Moreover, as shown in FIG. 1(a) and (b), the gate electrode 12 can be arranged in the trench 13 formed on the surface of the n-type column 4 along the extending direction of the n-type column 4 and the p-type column 5. .
栅极电极15能够设置成在与n型柱4及p型柱5的延伸方向交叉的方向上将相邻的栅极电极12相连的梯子状。而且，由栅极电极15覆盖的漂移层3中包含p型柱5的一部分。The gate electrode 15 can be provided in a ladder shape that connects adjacent gate electrodes 12 in a direction intersecting with the extending direction of the n-type column 4 and the p-type column 5 . Furthermore, drift layer 3 covered by gate electrode 15 includes a part of p-type column 5 .
如图1(b)所示，栅极电极15将配置位置在与p型柱5的延伸方向正交的方向上交替地移位而设置。As shown in FIG. 1( b ), the gate electrodes 15 are arranged so that their positions are alternately shifted in the direction perpendicular to the direction in which the p-type pillars 5 extend.
图2是概念性地表示半导体元件100、及图14所示的比较例的半导体元件600的电压-电容特性的曲线图。纵轴表示电容值C，横轴表示源极漏极间电压Vds。FIG. 2 is a graph conceptually showing the voltage-capacitance characteristics of the semiconductor element 100 and the semiconductor element 600 of the comparative example shown in FIG. 14 . The vertical axis represents the capacitance value C, and the horizontal axis represents the source-drain voltage Vds .
图2所示的Cds为半导体元件100的源极漏极间电容，Cgd1表示半导体元件100的栅极漏极间电容、Cgd2表示比较例的半导体元件600的栅极漏极间电容。Cds shown in FIG. 2 is the source-drain capacitance of the semiconductor element 100 , Cgd1 is the gate-drain capacitance of the semiconductor element 100 , and Cgd2 is the gate-drain capacitance of the semiconductor element 600 of the comparative example.
例如，Cds随着Vds变高而减少，且在图2中所示的A区域内急剧变小。该A区域内的Cds的减少对应于如下情况：在n型柱4与p型柱5之间的pn结处，分别在n型柱4及p型柱5中扩展的耗尽层相连，并且漂移层3耗尽化。而且，若耗尽层扩展到漂移层3的整体，则Cds接近于最小值，之后，呈现出相对于Vds的上升而平缓减少的倾向。For example, Cds decreases as Vds becomes higher, and becomes smaller sharply in the region A shown in FIG. 2 . The reduction of Cds in this A region corresponds to the fact that at the pn junction between the n-type pillar 4 and the p-type pillar 5, the depletion layers extended in the n-type pillar 4 and the p-type pillar 5, respectively, are connected, And the drift layer 3 is depleted. Furthermore, when the depletion layer spreads over the entire drift layer 3 , Cds approaches a minimum value, and then tends to gradually decrease with an increase in Vds .
另一方面，Cgd1随着Vds变高而减少，且在Vds移动到A区域时饱和。之后，Cgd1呈现出相对于Vds的上升而缓慢增加的倾向。On the other hand, Cgd1 decreases as Vds becomes higher and saturates when Vds moves to the A region. After that, Cgd1 tends to increase slowly with respect to the rise of Vds .
Cgd1为填埋在沟槽13内的栅极电极12的底部与漏极电极17之间的电容。对源极漏极间施加Vds，随着耗尽层从p型基极区域6、及p型柱5与n型柱4之间的pn结向n型柱4扩展，而Cgd1减少。Cgd1 is the capacitance between the bottom of the gate electrode 12 buried in the trench 13 and the drain electrode 17 . When Vds is applied between the source and drain, as the depletion layer expands from the p-type base region 6 and the pn junction between the p-type pillar 5 and n-type pillar 4 to the n-type pillar 4 , Cgd1 decreases.
例如，图14所示的半导体元件600中，施加Vds，直到耗尽层在n型柱4及p型柱5扩展从而漂移层3大致整体耗尽化为止，Cgd2以较大的变化率减少。之后，漂移层3的耗尽层的扩展减缓，Cgd2呈现出相对于Vds的上升而缓慢减少的倾向。For example, in the semiconductor device 600 shown in FIG. 14 , when Vds is applied until the depletion layer expands in the n-type column 4 and the p-type column 5 and the drift layer 3 is substantially depleted as a whole, Cgd2 changes at a relatively large rate. reduce. After that, the expansion of the depletion layer of the drift layer 3 slows down, and Cgd2 tends to decrease slowly with the increase of Vds .
与此相对，半导体元件100中，在漂移层3上设置着栅极电极15，在该栅极电极15的下部未形成p型基极区域6。因此，若栅极电极15下方的p型柱5耗尽，则隔着p型柱5而与漏极层2相向的栅极电极15的一部分隔着耗尽层而与漏极层2相向。而且，栅极电极15的一部分重新变得有助于Cgd1，从而减少的Cgd1暂时呈现出随着Vds的上升而增加的倾向。In contrast, in the semiconductor element 100 , the gate electrode 15 is provided on the drift layer 3 , and the p-type base region 6 is not formed under the gate electrode 15 . Therefore, when the p-type column 5 under the gate electrode 15 is depleted, a part of the gate electrode 15 facing the drain layer 2 via the p-type column 5 faces the drain layer 2 via the depletion layer. Also, a part of the gate electrode 15 again contributes to Cgd1 , so that the reduced Cgd1 temporarily exhibits a tendency to increase as Vds rises.
半导体元件100的输出电容为源极漏极间电容Cds与栅极漏极间电容Cgd1的和。例如，假设半导体元件100与半导体元件600的不同点在于栅极电极15的有无，那么可以认为半导体元件100的Cds与半导体元件600的源极漏极间电容大致相等。因此，因为Cgd1大于Cgd2，所以半导体元件100的输出电容大于半导体元件600的输出电容。漏极电压Vds上升并且Cds大幅减少之后，相对的输出电容的差进一步变大。The output capacitance of the semiconductor element 100 is the sum of the source-drain capacitance Cds and the gate-drain capacitance Cgd1 . For example, assuming that the semiconductor element 100 differs from the semiconductor element 600 in the presence or absence of the gate electrode 15 , it can be considered that Cds of the semiconductor element 100 is approximately equal to the source-drain capacitance of the semiconductor element 600 . Therefore, since Cgd1 is greater than Cgd2 , the output capacitance of the semiconductor element 100 is greater than the output capacitance of the semiconductor element 600 . After the drain voltage Vds rises and Cds decreases significantly, the relative difference in output capacitance further increases.
例如，使半导体元件100及600进行开关动作时的漏极电压的变化量(dV/dt)与输出电容成反比。因此，半导体元件100的漏极电压的变化量小于半导体元件600的漏极电压的变化量。而且，因为开关噪声与漏极电压的变化率成正比，所以半导体元件100的噪声比半导体元件600的噪声低。For example, the change amount (dV/dt) of the drain voltage when the semiconductor elements 100 and 600 perform switching operations is inversely proportional to the output capacitance. Therefore, the amount of change in the drain voltage of the semiconductor element 100 is smaller than the amount of change in the drain voltage of the semiconductor element 600 . Also, since the switching noise is proportional to the rate of change of the drain voltage, the noise of the semiconductor element 100 is lower than that of the semiconductor element 600 .
即，半导体元件100设为如下构成：在漂移层3上设置栅极电极15，在栅极电极15的下部未设置p型基极区域6。由此，能够增大栅极漏极间电容Cgd1，降低开关噪声。That is, the semiconductor element 100 has a configuration in which the gate electrode 15 is provided on the drift layer 3 and the p-type base region 6 is not provided below the gate electrode 15 . Thereby, the gate-drain capacitance Cgd1 can be increased, and switching noise can be reduced.
图14所示的半导体元件600例如通过使栅极电极12的下部从p型基极区域6与n型柱4的边界向朝向漏极层2的方向突出的量ΔG增大，也能够使栅极漏极间电容Cgd2增大。In the semiconductor element 600 shown in FIG. 14, for example, by increasing the protruding amount ΔG of the lower portion of the gate electrode 12 toward the drain layer 2 from the boundary between the p-type base region 6 and the n-type column 4, the gate electrode 12 can also be made larger. The capacitance Cgd2 between the electrode and the drain increases.
然而，若增大ΔG而使栅极电极12的底部突出到n型柱4，则在漂移层3耗尽且n型柱4中成为高电场的情况下，沟槽13的底部的栅极绝缘膜11暴露在高电场中。并且，存在以下情况：由高电场加速后的热载流子注入到栅极绝缘膜11的内部，成为使栅极绝缘膜11的绝缘性劣化等使可靠性降低的原因。However, if the bottom of the gate electrode 12 protrudes to the n-type column 4 by increasing ΔG, when the drift layer 3 is depleted and the electric field becomes high in the n-type column 4, the gate insulation at the bottom of the trench 13 Membrane 11 is exposed to a high electric field. Furthermore, hot carriers accelerated by a high electric field may be injected into the inside of the gate insulating film 11 to degrade the insulation of the gate insulating film 11 and cause a decrease in reliability.
与此相对，本实施方式的半导体元件100中，通过设置栅极电极15能够增大栅极漏极电容。由此，也能够减小栅极电极12向n型柱4的突出量，以提高可靠性。In contrast, in the semiconductor element 100 of the present embodiment, the gate-drain capacitance can be increased by providing the gate electrode 15 . Accordingly, the amount of protrusion of the gate electrode 12 onto the n-type pillar 4 can also be reduced to improve reliability.
在栅极电极15的下部，成为耗尽层扩展到与栅极绝缘膜14相接触的漂移层3的表面的状态。然而，栅极电极15的正下方因为由被保持为低电位的p型基极区域6夹着，所以与漂移层3的中央相比，栅极电极15的正下方是低电场。因此，热载流子不会注入到栅极绝缘膜14中，也不会使栅极绝缘膜14的绝缘性降低。Below the gate electrode 15 , a depletion layer spreads to the surface of the drift layer 3 which is in contact with the gate insulating film 14 . However, the electric field directly below the gate electrode 15 is lower than that of the center of the drift layer 3 because the directly below the gate electrode 15 is sandwiched by the p-type base region 6 held at a low potential. Therefore, hot carriers are not injected into the gate insulating film 14 and the insulating properties of the gate insulating film 14 are not lowered.
接下来，参照图3～图8来说明半导体元件100的制造过程。Next, a manufacturing process of the semiconductor element 100 will be described with reference to FIGS. 3 to 8 .
图3(a)是表示图1的Ia-Ia剖面的示意图，表示了在n型漏极层2上设置的漂移层3的表面形成着沟槽13的状态。FIG. 3( a ) is a schematic view showing a cross-section taken along line Ia-Ia in FIG. 1 , showing a state where trenches 13 are formed on the surface of drift layer 3 provided on n-type drain layer 2 .
n型漏极层2及漂移层3例如能够设置在硅基板上。n型漏极层2能够使用高浓度地掺杂了n型杂质的硅层。漂移层3包含由p型柱5与n型柱4所构成的超结结构。The n-type drain layer 2 and the drift layer 3 can be provided, for example, on a silicon substrate. A silicon layer doped with n-type impurities at a high concentration can be used for the n-type drain layer 2 . The drift layer 3 includes a super junction structure composed of p-type pillars 5 and n-type pillars 4 .
超结结构例如可以采用RIE(Reactive Ion Etching，反应离子蚀刻)法在浓度比n型漏极层2低的n型硅层的表面形成沟槽后，通过使p型硅在沟槽的内部外延生长而形成。For example, the super junction structure can use RIE (Reactive Ion Etching, reactive ion etching) method to form a trench on the surface of the n-type silicon layer with a concentration lower than that of the n-type drain layer 2, and then make the p-type silicon epitaxial in the trench. grow and form.
然后，在设置着沟槽13的漂移层3的表面，隔着绝缘膜24而形成成为栅极电极12及15的导电层22。Then, on the surface of the drift layer 3 where the trench 13 is provided, a conductive layer 22 serving as the gate electrodes 12 and 15 is formed via an insulating film 24 .
绝缘膜24例如可以使用将硅层的表面热氧化而形成的二氧化硅膜(SiO2膜)，成为栅极绝缘膜11及栅极绝缘膜14。As the insulating film 24, for example, a silicon dioxide film (SiO2 film) formed by thermally oxidizing the surface of a silicon layer can be used to form the gate insulating film 11 and the gate insulating film 14.
导电层22例如可以使用采用CVD(Chemical Vapor Deposition，化学气相沉积)法而形成的多晶硅层。The conductive layer 22 can be, for example, a polysilicon layer formed by CVD (Chemical Vapor Deposition, chemical vapor deposition) method.
图4是表示继图3之后的制造过程的示意图，且表示了对导电层22刻画图案而形成着栅极电极12及15的状态。FIG. 4 is a schematic diagram showing a manufacturing process subsequent to FIG. 3 , and shows a state where the conductive layer 22 is patterned to form the gate electrodes 12 and 15 .
这里，图4(a)表示图1(b)的Ia-Ia剖面的结构，图4(b)表示IVb-IVb剖面的结构。以下，到图8为止均相同。Here, FIG. 4( a ) shows the structure of the Ia-Ia cross-section in FIG. 1( b ), and FIG. 4( b ) shows the structure of the IVb-IVb cross-section. Hereinafter, it is the same up to FIG. 8 .
例如，如图4(b)所示，保留填埋在沟槽13的内部的部分，对漂移层3上的导电层22进行蚀刻。由此，栅极电极12形成为所谓的沟槽栅极。For example, as shown in FIG. 4( b ), the conductive layer 22 on the drift layer 3 is etched while leaving the portion buried inside the trench 13 . Thus, the gate electrode 12 is formed as a so-called trench gate.
另一方面，栅极电极15可以通过对漂移层3上的导电层22进行选择性地蚀刻，并如图4(a)所示那样将相邻的栅极电极12之间相连而设置。On the other hand, the gate electrode 15 can be provided by selectively etching the conductive layer 22 on the drift layer 3 and connecting adjacent gate electrodes 12 as shown in FIG. 4( a ).
然后，在设置着栅极电极12及15的漂移层3的表面，将例如作为p型杂质的硼(B)离子注入，从而形成p型基极区域6。Then, boron (B) ions are implanted, for example, as a p-type impurity into the surface of the drift layer 3 where the gate electrodes 12 and 15 are provided, thereby forming the p-type base region 6 .
如图5(a)及图5(b)所示，在除由栅极电极15覆盖的部分以外的漂移层3的表面注入硼(B)，从而形成p型基极区域6。As shown in FIG. 5( a ) and FIG. 5( b ), boron (B) is implanted into the surface of the drift layer 3 except the portion covered by the gate electrode 15 to form the p-type base region 6 .
然后，如图6(a)、图6(b)所示，在漂移层3的表面，将例如作为n型杂质的砷(As)选择性地离子注入，从而形成n型源极区域7。此外，将作为p型杂质的硼(b)选择性地离子注入，从而形成p+接触区域8。Next, as shown in FIGS. 6( a ) and 6 ( b ), for example, arsenic (As) as an n-type impurity is selectively ion-implanted on the surface of drift layer 3 to form n-type source region 7 . In addition, boron (b) as a p-type impurity is selectively ion-implanted, thereby forming p+ contact region 8 .
如图6(a)所示，在除由栅极电极15覆盖的部分以外的漂移层3的表面，设置着n型源极区域7及p+接触区域8。As shown in FIG. 6( a ), n-type source region 7 and p+ contact region 8 are provided on the surface of drift layer 3 excluding the portion covered by gate electrode 15 .
如图6(b)所示，在未设置栅极电极15的部分形成着与图14所示的半导体元件600相同的沟槽栅极结构的MOSFET。As shown in FIG. 6( b ), a MOSFET having the same trench gate structure as that of the semiconductor element 600 shown in FIG. 14 is formed in a portion where the gate electrode 15 is not provided.
其次，如图7(a)及图7(b)所示，在栅极电极12及栅极电极15、n型源极区域7、p+接触区域8上形成层间绝缘膜23。Next, as shown in FIGS. 7( a ) and 7 ( b ), interlayer insulating film 23 is formed on gate electrode 12 and gate electrode 15 , n-type source region 7 , and p+ contact region 8 .
层间绝缘膜23例如能够使用采用CVD法而形成的SiO2膜。For the interlayer insulating film 23, for example, a SiO2 film formed by a CVD method can be used.
然后，如图8(a)及图8(b)所示，在栅极电极12及15上保留层间绝缘膜23，对n型源极区域7及p+接触区域8的表面的绝缘膜24与层间绝缘膜23进行选择性地蚀刻。Then, as shown in FIG. 8(a) and FIG. 8(b), the interlayer insulating film 23 remains on the gate electrodes 12 and 15, and the insulating film on the surface of the n-type source region 7 and the p+ contact region 8 24 and the interlayer insulating film 23 are selectively etched.
之后，在由层间绝缘膜23覆盖的栅极电极12及15上、以及n型源极区域7及p+接触区域8的表面形成源极电极19。Thereafter, source electrode 19 is formed on gate electrodes 12 and 15 covered with interlayer insulating film 23 and on the surfaces of n-type source region 7 and p+ contact region 8 .
而且，形成与n型漏极层2电连接的漏极电极17，从而可以完成半导体元件100的结构。Furthermore, the drain electrode 17 electrically connected to the n-type drain layer 2 is formed, so that the structure of the semiconductor element 100 can be completed.
图9是示意性地表示本实施方式的变形例的半导体元件200的结构的立体图。FIG. 9 is a perspective view schematically showing the structure of a semiconductor element 200 according to a modified example of the present embodiment.
半导体元件200与半导体元件100的不同点在于，设置成条纹状的n型柱4及p型柱5的延伸方向与填埋着栅极电极12的沟槽13的延伸方向正交。The semiconductor element 200 differs from the semiconductor element 100 in that the extending direction of the n-type pillars 4 and the p-type pillars 5 arranged in stripes is perpendicular to the extending direction of the trench 13 in which the gate electrode 12 is buried.
半导体元件200中，例如设置在p型柱5上的栅极电极15的下部被作为p型柱5的一部分的p型区域5b所占据，直到p型柱5耗尽为止不会有助于栅极漏极间电容Cgd。而且，如图2中所示，在p型柱5耗尽且漂移层3整体成为耗尽层时，开始有助于Cgd，使Cgd随着漏极电压Vds的上升而增加。In the semiconductor element 200, for example, the lower portion of the gate electrode 15 provided on the p-type column 5 is occupied by the p-type region 5b as a part of the p-type column 5, and will not contribute to the gate electrode until the p-type column 5 is exhausted. Electrode-drain capacitance Cgd . Moreover, as shown in FIG. 2 , when the p-type column 5 is depleted and the drift layer 3 becomes a depletion layer as a whole, it starts to contribute to Cgd , so that Cgd increases as the drain voltage Vds rises.
图10是示意性地表示本实施方式的另一变形例的半导体元件300的结构的立体图。FIG. 10 is a perspective view schematically showing the structure of a semiconductor element 300 according to another modified example of the present embodiment.
半导体元件300中，p型柱35的形成方法与半导体元件100不同。p型柱35例如能够通过重复进行如下步骤而形成：在高阻抗的外延层选择性地将n型杂质及p型杂质离子注入，并实施热处理而使该n型杂质及p型杂质扩散之后，进一步堆积高阻抗的外延层，进行n型杂质及p型杂质的离子注入并实施热处理。In the semiconductor element 300 , the method of forming the p-type pillar 35 is different from that of the semiconductor element 100 . The p-type column 35 can be formed by, for example, repeating the steps of selectively ion-implanting n-type impurities and p-type impurities into a high-resistance epitaxial layer, performing heat treatment to diffuse the n-type impurities and p-type impurities, Further, a high-resistance epitaxial layer is deposited, ion implantation of n-type impurities and p-type impurities is performed, and heat treatment is performed.
图11是表示本实施方式的变形例的栅极电极的配置的俯视图。FIG. 11 is a plan view showing the arrangement of gate electrodes in a modified example of the present embodiment.
可以如图11(a)所示，将栅极电极15设置成条纹状，且与栅极电极12及n型柱4、p型柱5的延伸方向交叉地设置。As shown in FIG. 11( a ), the gate electrode 15 may be provided in a stripe shape, and may be provided so as to cross the extending direction of the gate electrode 12 and the n-type column 4 and the p-type column 5 .
也可如图11(b)所示，将栅极电极12设置在p型柱5的两侧，栅极电极15以横跨n型柱4而将栅极电极12相连的方式设置。在该情况下，因为在栅极电极15下方未设置p型柱5，所以栅极电极15直接有助于栅极漏极间电容Cgd。Alternatively, as shown in FIG. 11( b ), the gate electrodes 12 may be provided on both sides of the p-type column 5 , and the gate electrodes 15 may be provided so as to straddle the n-type column 4 and connect the gate electrodes 12 . In this case, since the p-type pillar 5 is not provided under the gate electrode 15, the gate electrode 15 directly contributes to the inter-gate-drain capacitance Cgd .
此外，还可以将栅极电极12设置在沿着漂移层3的表面的一方向上相隔开的多个部分。而且，栅极电极15可设置成在栅极电极12的间隔部将多个部分相连。结果，栅极电极12与栅极电极15交替串列地设置。In addition, gate electrode 12 may also be provided at a plurality of portions spaced apart in one direction along the surface of drift layer 3 . Furthermore, the gate electrode 15 may be provided so as to connect a plurality of parts at the interval of the gate electrode 12 . As a result, the gate electrodes 12 and the gate electrodes 15 are alternately arranged in series.
图11(c)所示的例中，栅极电极12在p型柱5的两侧沿p型柱5的延伸方向相隔开而设置。栅极电极15包含横跨n型柱4而将相邻的栅极电极12相连的部分(第一接合部15b)、及将栅极电极12的间隔部ΔU相连的部分(第二接合部15a)。而且，栅极电极12与栅极电极15在n型柱4及p型柱5的延伸方向上串列地设置。如图11(c)所示，第二接合部15a在n型柱4上将相隔开的第一接合部15b连接，且将栅极电极12的多个部分电连接。In the example shown in FIG. 11( c ), gate electrodes 12 are provided on both sides of p-type pillar 5 at intervals along the extending direction of p-type pillar 5 . The gate electrode 15 includes a portion connecting adjacent gate electrodes 12 across the n-type column 4 (first joint portion 15 b ), and a portion connecting the spacer ΔU of the gate electrodes 12 (second joint portion 15 a ). ). Furthermore, the gate electrode 12 and the gate electrode 15 are arranged in series in the extending direction of the n-type column 4 and the p-type column 5 . As shown in FIG. 11( c ), the second junction portion 15 a connects the spaced apart first junction portions 15 b on the n-type pillar 4 and electrically connects a plurality of parts of the gate electrode 12 .
图12是表示包含图11(a)所示的栅极电极15的半导体元件400的示意图。图12(a)是示意性地表示半导体元件400的结构的立体图，图12(b)是表示XIIb-XIIb剖面的结构的示意图。FIG. 12 is a schematic diagram showing a semiconductor element 400 including the gate electrode 15 shown in FIG. 11( a ). FIG. 12( a ) is a perspective view schematically showing the structure of the semiconductor element 400 , and FIG. 12( b ) is a schematic view showing the structure of the XIIb-XIIb cross section.
半导体元件400中，n型柱4及p型柱5设置成条纹状，栅极电极15也设置成与多个n型柱4及多个p型柱5交叉的条纹形状。如图12(a)及图12(b)所示，栅极电极12在n型柱4的表面沿该n型柱4的延伸方向设置。栅极电极15与多个栅极电极12交叉，且在这个交点处电相连。而且，因为在栅极电极15下方未设置p型基极区域6，所以该栅极电极15隔着栅极绝缘膜11而与多个n型柱4及p型柱5的表面相向。In the semiconductor element 400 , the n-type columns 4 and the p-type columns 5 are provided in a stripe shape, and the gate electrode 15 is also provided in a stripe shape intersecting a plurality of n-type columns 4 and a plurality of p-type columns 5 . As shown in FIG. 12( a ) and FIG. 12( b ), the gate electrode 12 is provided on the surface of the n-type pillar 4 along the extending direction of the n-type pillar 4 . The gate electrode 15 intersects the plurality of gate electrodes 12 and is electrically connected at this intersection point. Furthermore, since the p-type base region 6 is not provided under the gate electrode 15 , the gate electrode 15 faces the surfaces of the plurality of n-type columns 4 and p-type columns 5 via the gate insulating film 11 .
由此，与在栅极电极15下方形成着p型基极区域6的情况相比，能够增大栅极漏极间电容Cgd。另外，对n型柱4与p型柱5之间的pn结施加反向偏置电压(reverse bias voltage)，n型柱4及p型柱5一并耗尽时的栅极漏极间电容Cgd也会变大。Thereby, compared with the case where the p-type base region 6 is formed under the gate electrode 15, it is possible to increase the gate-drain capacitance Cgd . In addition, a reverse bias voltage (reverse bias voltage) is applied to the pn junction between the n-type column 4 and the p-type column 5, and the gate-drain capacitance when the n-type column 4 and the p-type column 5 are exhausted together Cgd also gets bigger.
在相邻的栅极电极15之间的漂移层3的表面，设置着p型基极区域6。而且，在该p型基极区域6的表面选择性地设置着n型源极区域7与p+接触区域8。n型源极区域7隔着栅极绝缘膜11而与栅极电极12的侧面相向。p+接触区域8与p型基极区域6连接而设置，将p型基极区域6与源极电极19(参照图8(b))维持为相同电位。A p-type base region 6 is provided on the surface of the drift layer 3 between adjacent gate electrodes 15 . Furthermore, n-type source region 7 and p+ contact region 8 are selectively provided on the surface of p-type base region 6 . N-type source region 7 faces side surfaces of gate electrode 12 with gate insulating film 11 interposed therebetween. The p+ contact region 8 is provided in connection with the p-type base region 6 , and maintains the p-type base region 6 and the source electrode 19 (see FIG. 8( b )) at the same potential.
如图12(a)所示，n型源极区域7与栅极电极15下方的漂移层3相隔开地设置。即，如图12(a)所示，在n型源极区域7与栅极电极15之间夹着p+接触区域8的一部分8a，使延伸到栅极电极15下方的p型基极区域6的外缘(扩散部)6a与n型源极区域7分离。由此，抑制经由形成在栅极电极15下方的反型层而流通的漏极电流，避免电流集中。也就是，如果n型源极区域7与p型基极区域6的外缘(扩散部)6a相连，那么可能产生以下问题：经由形成在栅极电极15下方的阈值电压低的反型层流通漏极电流从而产生电流集中。As shown in FIG. 12( a ), the n-type source region 7 is spaced apart from the drift layer 3 below the gate electrode 15 . That is, as shown in FIG. 12(a), a part 8a of the p+ contact region 8 is sandwiched between the n-type source region 7 and the gate electrode 15, so that the p-type base region extending below the gate electrode 15 An outer edge (diffusion portion) 6 a of 6 is separated from n-type source region 7 . Accordingly, the drain current flowing through the inversion layer formed under the gate electrode 15 is suppressed, and current concentration is avoided. That is, if the n-type source region 7 is connected to the outer edge (diffusion portion) 6a of the p-type base region 6, there may arise a problem of current flow via an inversion layer having a low threshold voltage formed under the gate electrode 15. The drain current thus creates a current concentration.
以上，第一实施方式中，将与栅极电极12电连接的栅极电极15隔着栅极绝缘膜11而设置在漂移层3的表面。而且，通过在栅极电极15下方不设置p型基极区域，而增大栅极漏极电容并降低开关噪声。此外，使n型源极区域7与栅极电极15相隔开地形成，以抑制流经栅极电极15下方的阈值电压低的反型层的电流。由此，使漏极电流在包含栅极电极12的沟槽栅极中流通，从而缓和电流集中。As described above, in the first embodiment, the gate electrode 15 electrically connected to the gate electrode 12 is provided on the surface of the drift layer 3 via the gate insulating film 11 . Furthermore, by not providing a p-type base region under the gate electrode 15, the gate-drain capacitance is increased and switching noise is reduced. In addition, the n-type source region 7 is formed to be spaced apart from the gate electrode 15 to suppress the current flowing through the inversion layer below the gate electrode 15 having a low threshold voltage. Accordingly, the drain current flows through the trench gate including the gate electrode 12 , thereby reducing current concentration.
(第二实施方式)(second embodiment)
图13是表示第二实施方式的半导体元件500的结构的示意图。图13(a)是表示除源极电极19及层间绝缘膜23(参照图8)以外的半导体元件500的芯片面的一部分的俯视图。图13(b)是示意性地表示半导体元件500的结构的立体图。FIG. 13 is a schematic diagram showing the structure of a semiconductor element 500 according to the second embodiment. FIG. 13( a ) is a plan view showing part of the chip surface of the semiconductor element 500 excluding the source electrode 19 and the interlayer insulating film 23 (see FIG. 8 ). FIG. 13( b ) is a perspective view schematically showing the structure of the semiconductor element 500 .
半导体元件500中，在n型柱4的表面沿该n型柱4的延伸方向设置着栅极电极12。而且，栅极电极15隔着栅极绝缘膜11而形成在设置着n型柱4及p型柱5的漂移层3的区域的大致整个面。In the semiconductor element 500 , the gate electrode 12 is provided on the surface of the n-type pillar 4 along the direction in which the n-type pillar 4 extends. Furthermore, the gate electrode 15 is formed on substantially the entire surface of the region of the drift layer 3 where the n-type column 4 and the p-type column 5 are provided with the gate insulating film 11 interposed therebetween.
p型基极区域6设置成当进行与n型漏极层2的主面2a平行的俯视观察时散布在漂移层3的表面。而且，栅极电极15中设置着从该栅极电极15的表面贯通到p型基极区域6的多个开口31。The p-type base regions 6 are provided scattered on the surface of the drift layer 3 when viewed in plan view parallel to the main surface 2 a of the n-type drain layer 2 . Furthermore, a plurality of openings 31 penetrating from the surface of the gate electrode 15 to the p-type base region 6 are provided in the gate electrode 15 .
此外，在形成开口31的底面的p型基极区域6的表面，选择性地设置着n型源极区域7及与n型源极区域7相邻接的p+接触区域8。p型基极区域6设置在p型柱5上。而且，p+接触区域8与p型基极区域6连接地形成。In addition, n-type source region 7 and p+ contact region 8 adjacent to n-type source region 7 are selectively provided on the surface of p-type base region 6 forming the bottom surface of opening 31 . The p-type base region 6 is provided on the p-type pillar 5 . Furthermore, p+ contact region 8 is formed to be connected to p-type base region 6 .
半导体元件500中，在施加了栅极电压的情况下，在隔着栅极绝缘膜11而与栅极电极15相向的p型基极区域6的表面形成着反型层，在源极漏极间流通着漏极电流。此外，在隔着栅极绝缘膜11而与栅极电极15相向的p型柱5的表面也形成着反型层。由此，在n型柱4整体内流通着漏极电流，从而降低导通阻抗。In the semiconductor element 500, when a gate voltage is applied, an inversion layer is formed on the surface of the p-type base region 6 facing the gate electrode 15 via the gate insulating film 11, and an inversion layer is formed on the source and drain electrodes. A drain current flows between them. In addition, an inversion layer is also formed on the surface of the p-type column 5 facing the gate electrode 15 via the gate insulating film 11 . As a result, the drain current flows through the entire n-type pillar 4, thereby reducing the on-resistance.
另一方面，在n型柱4的表面设置着栅极电极12。与单纯的平面栅极(planar portal)结构相比，能够增大栅极漏极间电容Cgd。由此，能够增加输出电容并降低开关噪声。On the other hand, gate electrode 12 is provided on the surface of n-type pillar 4 . Compared with a simple planar portal structure, the gate-drain capacitance Cgd can be increased. Thus, it is possible to increase the output capacitance and reduce switching noise.
如所述实施方式所示，栅极电极12及15可配合n型柱4及p型柱5的结构以及所期望的栅极漏极间电容Cgd，适当选择优选的配置而设置。As shown in the above-described embodiment, the gate electrodes 12 and 15 can be provided by appropriately selecting a preferred configuration in accordance with the structure of the n-type column 4 and the p-type column 5 and the desired gate-drain capacitance Cgd .
所述实施方式中，已对n型柱4及p型柱5设置成条纹状的示例进行了说明，但并不限定于此，还可以应用于构成为格子状、点状等的超结结构。而且，对沟槽栅极的结构也设置成条纹状的示例进行了说明，但只要为与将低电容的沟槽栅极结构与高电容的表面栅极结构组合的实施方式的主旨一致的结构即可，不限定于所述示例。In the above-mentioned embodiment, the example in which the n-type columns 4 and the p-type columns 5 are arranged in a stripe shape has been described, but the present invention is not limited to this, and it can also be applied to a super junction structure configured in a lattice shape, a dot shape, or the like. . Furthermore, an example in which the structure of the trench gate is also provided in stripes has been described, but the structure should be consistent with the gist of the embodiment in which the trench gate structure of low capacitance and the surface gate structure of high capacitance are combined. That is, it is not limited to the examples described above.
以上，参照本发明的一实施方式说明了本发明，但本发明并不限定于这些实施方式。例如本领域技术人员基于申请时的技术水准而能够完成的设计变更、或材料的变更等技术思想与本发明相同的实施方式也包括在本发明的技术范围内。As mentioned above, although this invention was demonstrated with reference to one embodiment of this invention, this invention is not limited to these embodiment. For example, embodiments with the same technical idea as the present invention, such as design changes or material changes that can be accomplished by those skilled in the art based on the technical level at the time of application, are also included in the technical scope of the present invention.
所述实施方式中，将以硅为材料的纵式功率MOSFET作为示例进行了说明，但只要为MOS(Metal Oxide Semiconductor，金属氧化物半导体)栅极结构及具有n型柱、p型柱的结构，便可使用。例如可以应用于横式器件、或IGBT等其他开关器件。材料并不限定于硅，使用SiC、GaN之类的材料也可以取得同样的效果。In the above-described embodiments, the vertical power MOSFET made of silicon is described as an example, but as long as it has a MOS (Metal Oxide Semiconductor, Metal Oxide Semiconductor) gate structure and a structure with n-type columns and p-type columns , and you can use it. For example, it can be applied to other switching devices such as horizontal devices or IGBTs. The material is not limited to silicon, and the same effect can be obtained by using materials such as SiC and GaN.
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| JP2010210476 | 2010-09-21 | ||
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