CN102411535A - Navigating-SoC (System On Chip) simulating, verifying and debugging platform - Google Patents

Abstract

Translated fromChinese

本发明公开一种导航SoC芯片仿真、验证和调试平台，它包括集成了RISC处理器和FPGA的导航SoC验证板，以及协助设计人员调试和分析的PC主机环境。在FPGA上实现导航IP，并加入对挂起/运行模式的支持。根据硬件挂起/运行状态，导航中断程序分为硬件挂起和运行两个时期，在挂起时期PC主机通过UDP/USB协议完成中频数据向SoC验证板的导入，紧接着SoC验证板将调试信息传送回PC主机。本发明还利用SoC验证板上的定时器资源来精确分析代码在RISC处理器上的运行时间，可以对软硬件的实时性进行分析。PC主机端包含GUI界面、UDP/USB通信线程和后台数据库，为设计人员提供完善的验证环境。

The invention discloses a navigation SoC chip emulation, verification and debugging platform, which includes a navigation SoC verification board integrated with a RISC processor and an FPGA, and a PC host environment that assists designers in debugging and analyzing. Implement navigation IP on FPGA and add support for suspend/run mode. According to the hardware suspend/run state, the navigation interrupt program is divided into two periods: hardware suspend and run. During the suspend period, the PC host completes the import of IF data to the SoC verification board through the UDP/USB protocol, and then the SoC verification board will debug The information is sent back to the host PC. The invention also utilizes the timer resources on the SoC verification board to accurately analyze the running time of codes on the RISC processor, and can analyze the real-time performance of software and hardware. The PC host side includes GUI interface, UDP/USB communication thread and background database, providing a complete verification environment for designers.

Description

Translated fromChinese

导航SoC芯片仿真、验证和调试平台Navigation SoC chip simulation, verification and debugging platform

技术领域technical field

本发明涉及SoC（System On Chi，片上系统）验证调试领域，特别是一种能够用来进行导航SoC芯片仿真、验证和调试的装置平台。The invention relates to the field of SoC (System On Chi, system on chip) verification and debugging, in particular to a device platform that can be used for navigation SoC chip simulation, verification and debugging.

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背景技术Background technique

全球导航卫星定位系统（GNSS）在过去几十年间在各个领域已经得到了广泛的应用。目前GNSS包括了美国的GPS、俄罗斯的GLONASS、中国的Compass（北斗）以及欧盟的Galileo系统。在民用领域，大部分的移动设备都具备导航功能，为人们的出行提供了极大的方便。许多交通工具配备了GPS导航设备，大大简化了交通业的管理。在军事领域，导航系统更是现代化战争的重中之重，而这些设备的核心就是导航芯片。在导航芯片设计领域，国内和国外的先进水平有一定的差距，Sirf、u-blox等芯片和相应的解决方案无论在功耗、成熟度、可靠性和成本都达到了极高的水平。Global Navigation Satellite System (GNSS) has been widely used in various fields in the past few decades. At present, GNSS includes GPS of the United States, GLONASS of Russia, Compass (Beidou) of China and Galileo system of the European Union. In the civilian field, most mobile devices have navigation functions, which provide great convenience for people's travel. Many vehicles are equipped with GPS navigation equipment, which greatly simplifies the management of the transportation industry. In the military field, the navigation system is the top priority of modern warfare, and the core of these devices is the navigation chip. In the field of navigation chip design, there is a certain gap between domestic and foreign advanced levels. Chips such as Sirf and u-blox and corresponding solutions have reached extremely high levels in terms of power consumption, maturity, reliability and cost.

随着北斗二代卫星导航系统的逐步完善，导航芯片的设计和研发又成为了学术界和业界的焦点，为了不受制于国外芯片供应商，我国急需发展出有自主知识产权的含有导航IP（Intellectual Property，知识产权模块）和RSIC处理器（Reduced Instruction Set Computer，精简指令集计算机）的SoC解决方案。With the gradual improvement of the second-generation Beidou satellite navigation system, the design and development of navigation chips have become the focus of academia and industry. In order not to be restricted by foreign chip suppliers, my country urgently needs to develop navigation IP with independent intellectual property rights ( Intellectual Property, intellectual property module) and RSIC processor (Reduced Instruction Set Computer, reduced instruction set computer) SoC solution.

所谓的导航硬件加速单元，简称导航IP，指的是以网表提供的固核或者以HDL（Hardware Description Language，硬件描述语言）代码提供的软核。导航算法涉及到大量的数学运算和矩阵运算，完全采用硬件实现难度过大，难以进行修改，扩展性会受到限制，同时，导航算法还处在不断演进的过程中，硬件的灵活性无法满足要求。另一方面，纯软件实现虽然是学术界一直关注的热点，但以目前RISC的处理能力、功耗要求权衡来看，无法满足要求。因此，RISC处理器核配合硬件加速器（即导航IP）成为主流的方案，这样的导航芯片解决方案简称导航SoC（System-on-a-Chip，即片上系统）。构建这样一个SoC系统的一大难点就在于验证和调试部分，这也是耗时最长的一个部分，直接影响到上市时间。The so-called navigation hardware acceleration unit, referred to as navigation IP, refers to the solid core provided by the netlist or the soft core provided by HDL (Hardware Description Language, hardware description language) code. The navigation algorithm involves a large number of mathematical operations and matrix operations. It is too difficult to implement it completely by hardware, it is difficult to modify, and the scalability will be limited. At the same time, the navigation algorithm is still in the process of continuous evolution, and the flexibility of the hardware cannot meet the requirements. . On the other hand, although pure software implementation has been a hot spot in the academic circles, it cannot meet the requirements in terms of the current RISC processing capability and power consumption requirements. Therefore, RISC processor cores combined with hardware accelerators (ie navigation IP) have become the mainstream solution. Such navigation chip solutions are referred to as navigation SoC (System-on-a-Chip, ie system on chip). One of the difficulties in building such an SoC system lies in the verification and debugging part, which is also the part that takes the longest time and directly affects the time to market.

导航SoC芯片的运行和验证具有如下特点：The operation and verification of the navigation SoC chip has the following characteristics:

1.      导航IP需要处理器的配合，在处理器上运行软件可以提高设计的灵活性。因此，我们所要仿真验证的对象是一个软硬件协同的系统。不同的调试方案中，算法软件既可以运行在PC主机上，也可以运行在目标板的RISC处理器上，后者和实际芯片的行为更为相符。1. Navigation IP requires the cooperation of the processor, and running software on the processor can improve the flexibility of the design. Therefore, the object we want to simulate and verify is a system of software and hardware coordination. In different debugging schemes, the algorithm software can run either on the PC host or on the RISC processor of the target board, and the latter is more consistent with the behavior of the actual chip.

2.      导航SoC芯片必须关注于实时性，导航算法对导航中频数据流进行处理，这些算法都是有实时性要求。如何给设计人员提供准确的实时性信息以及完备的调试信息成为导航SoC验证的基本问题。2. The navigation SoC chip must focus on real-time performance. The navigation algorithm processes the navigation intermediate frequency data stream, and these algorithms all have real-time performance requirements. How to provide designers with accurate real-time information and complete debugging information has become a basic problem for navigating SoC verification.

3.      导航IP及SoC系统的验证对仿真速度有很高的要求。导航中频数据的采样率范围4MHz~17MHz，导航IP运行在30MHz~100MHz，处理器处理1s的数据需要上千万个时钟周期，而导航算法往往要一分钟的数据才能解算出结果，如果要模拟一些特殊的场景，需要几十分钟的数据，完全采用HDL仿真器去仿真耗时将会非常的长。3. The verification of navigation IP and SoC system has high requirements on simulation speed. The sampling rate of navigation intermediate frequency data ranges from 4MHz to 17MHz, and the navigation IP runs at 30MHz to 100MHz. The processor needs tens of millions of clock cycles to process 1s of data, and the navigation algorithm often needs one minute of data to calculate the result. If you want to simulate Some special scenarios require dozens of minutes of data, and it will take a very long time to fully use the HDL simulator to simulate.

4.      导航中频数据的存储量很大，以5.714MHz的采样率2bit精度为例，1分钟的数据就需要85.71MB的数据；如果需要对不同场景下的捕获、跟踪和解算等流程进行仿真，往往需要5分钟甚至更长时间，数据量将达到400多MB，因此高效的数据存储、导入和回放机制也是调试平台必须解决的问题。数据的导入还要保证时间上的准确性，错开一个采样点都会影响整个系统运行的准确性。4. The storage capacity of navigation intermediate frequency data is very large. Taking the sampling rate of 5.714MHz with 2bit precision as an example, 1 minute of data requires 85.71MB of data; if you need to simulate the processes of capture, tracking and calculation in different scenarios, It often takes 5 minutes or even longer, and the amount of data will reach more than 400 MB. Therefore, an efficient data storage, import and playback mechanism is also a problem that must be solved by the debugging platform. The import of data also needs to ensure the accuracy of time, and a staggered sampling point will affect the accuracy of the entire system operation.

5.      图1是典型的导航SoC程序运行流程，定时器每隔一段时间触发处理器一次中断，典型间隔为520us。而导航IP以采样的间隔时间输入中频数据，典型采样率为40/7MHz或者16.368MHz。中断函数返回后，根据标志位的结果，会定期地调用主函数。中断服务程序主要和硬件加速单元（导航IP）进行交互。如图所示的程序执行流程是导航芯片的主流工作模式。5. Figure 1 is a typical navigation SoC program running process. The timer triggers an interrupt to the processor at regular intervals, with a typical interval of 520us. The navigation IP inputs IF data at sampling intervals, and the typical sampling rate is 40/7MHz or 16.368MHz. After the interrupt function returns, the main function will be called periodically according to the result of the flag bit. The interrupt service routine mainly interacts with the hardware acceleration unit (navigation IP). The program execution flow shown in the figure is the mainstream working mode of the navigation chip.

图1是导航SoC软件运行的典型流程图，在导航算法及硬件加速模块系统的仿真领域，目前主要有三种方案：Figure 1 is a typical flowchart of navigation SoC software operation. In the field of simulation of navigation algorithms and hardware acceleration module systems, there are currently three main solutions:

方案一，用硬件描述语言（HDL）描述整个系统，包括处理器核和导航IP全部采用HDL描述，处理器核运行的是编译完成的二进制可执行代码；Option 1, use the hardware description language (HDL) to describe the entire system, including the processor core and navigation IP are all described in HDL, and the processor core runs the compiled binary executable code;

方案二，采用指令集仿真器进行导航算法软件的仿真，而导航硬件加速单元通过HDL仿真器仿真，二者通过DPI机制（Direct Programming Interface，SystemVerilog与C/C++语言交互的机制）或者操作系统进程间通信机制进行交互；Solution 2: use the instruction set simulator to simulate the navigation algorithm software, and the navigation hardware acceleration unit is simulated by the HDL simulator, and the two pass the DPI mechanism (Direct Programming Interface, SystemVerilog and C/C++ language interaction mechanism) or the operating system process Interaction between communication mechanisms;

方案三，采用软硬件协同的方案，在目标板上的FPGA（现场可编程门阵列）实现导航IP，在X86主机上运行导航运算程序，PC主机和FPGA通过PCI接口进行通信；Solution 3, using the software and hardware coordination scheme, realize the navigation IP on the FPGA (Field Programmable Gate Array) on the target board, run the navigation calculation program on the X86 host, and communicate between the PC host and the FPGA through the PCI interface;

方案一可以得到最精确的仿真结果，并且通过HDL仿真器进行调试，缺点是非常的慢，HDL仿真器得到的结果也不直观，仅能在很低层次的管脚信号级别进行调试。处理器核（可综合的）的逻辑非常复杂，以及导航IP本身的复杂性，往往需要几天时间才能仿真几秒钟的数据。同时，处理器核授权的费用很高，成本过高，一般公司和学校科研单位负担不起。Option 1 can get the most accurate simulation results, and debug through the HDL emulator. The disadvantage is that it is very slow, and the results obtained by the HDL emulator are not intuitive, and can only be debugged at a very low-level pin signal level. The logic of the processor core (synthesizable) is very complex, and the complexity of the navigation IP itself often takes days to simulate a few seconds of data. At the same time, the cost of processor core authorization is very high, and the cost is too high, which cannot be afforded by ordinary companies and school research institutes.

方案二加快了处理器部分的仿真速度，但整体速度仍然受限于导航硬件加速单元RTL的仿真性能。由于软件模块是通过指令集仿真器运行的，Cache（缓存）的行为以及总线的时序没有办法精确模拟，无法真实反映SoC芯片的行为，严重干扰设计人员对实时性的评估。The second scheme speeds up the simulation speed of the processor part, but the overall speed is still limited by the simulation performance of the navigation hardware acceleration unit RTL. Since the software module is run by an instruction set simulator, the behavior of the Cache (cache) and the timing of the bus cannot be accurately simulated, which cannot truly reflect the behavior of the SoC chip, which seriously interferes with the designer's evaluation of real-time performance.

方案三不需要运行HDL仿真器，瓶颈转移到PC主机和FPGA的通信效率上。但应当认识到，软件代码运行在X86主机上所得到的结果往往和RISC处理器得到的运行结果不同，X86处理器和RISC处理器在架构上（比如指令集、Cache、内存管理单元MMU和浮点协处理器）差异很大，导致运行效率上和运行结果精度的不同，也无法对软件实时性进行评估。PCI接口协议非常复杂，往往需要专门的一台主机来运行整个系统。Solution 3 does not need to run the HDL emulator, and the bottleneck shifts to the communication efficiency between the PC host and the FPGA. However, it should be recognized that the results obtained by running software code on an X86 host are often different from those obtained by a RISC processor. Point coprocessors) are very different, resulting in differences in operating efficiency and accuracy of operating results, and it is impossible to evaluate the real-time performance of the software. The PCI interface protocol is very complex, and often requires a dedicated host computer to run the entire system.

在中频数据的回放方案上，传统的方法有两种：There are two traditional methods for playback of intermediate frequency data:

方法一：进行真正意义上的实时仿真，实现在FPGA上的导航IP直接和采样芯片的中频数据输出端口进行连接；Method 1: Carry out real-time simulation in the true sense, and realize the direct connection between the navigation IP on the FPGA and the intermediate frequency data output port of the sampling chip;

方法二：通过PCI-E接口或者USB接口来支持数据的回放，按照一定时序将中频数据导入到FPGA中；Method 2: Support data playback through the PCI-E interface or USB interface, and import the IF data into the FPGA according to a certain timing;

方法一不支持数据的回放。可重现特性一直是SoC验证领域的基本要求。外界的场景往往处在不断地变化当中，问题的出现时间往往是随机的，这就给调试带来很大的困难。因此支持数据的回放是导航调试功能的前提，它使得设计人员可以反复对同一批数据和同一个问题进行全方位的剖析，从而找到系统中的缺陷。排除天气、地点等外界因素带来的干扰，把数据的采集和SoC系统的调试验证这两个步骤分开。Method 1 does not support data playback. Reproducible characterization has always been a fundamental requirement in the field of SoC verification. The external scene is often in constant change, and the occurrence time of the problem is often random, which brings great difficulties to debugging. Therefore, supporting data playback is the premise of the navigation debugging function, which allows designers to repeatedly analyze the same batch of data and the same problem in all directions, so as to find defects in the system. Eliminate the interference caused by external factors such as weather and location, and separate the two steps of data collection and SoC system debugging and verification.

虽然方法二所用的协议比较复杂，并且都是用PC主机上的x86处理器来运行导航算法的软件部分，尽管能对硬件的实时性进行分析，却无法对软件的实时性进行精确定量的分析，而软件的实时性才是导航算法设计中的难点。Although the protocol used in the second method is more complicated, and the x86 processor on the host computer is used to run the software part of the navigation algorithm, although the real-time performance of the hardware can be analyzed, it is impossible to analyze the real-time performance of the software accurately and quantitatively. , and the real-time nature of the software is the difficulty in the design of the navigation algorithm.

经过对现有技术文献的检索发现，申请号为“200610012061.5”，名称为“导航卫星信号处理系统”，该专利提供一种导航卫星处理系统，能够实时、连续、长时间的采集导航卫星信号，传送到计算机，并且通过USB等高速接口将采样数据回放。该平台仅仅关注于回放功能，并没有为调试提供解决方案。After searching the existing technical documents, it is found that the application number is "200610012061.5" and the name is "Navigation Satellite Signal Processing System". This patent provides a navigation satellite processing system, which can collect navigation satellite signals in real time, continuously and for a long time. Transfer to the computer, and playback the sampling data through high-speed interfaces such as USB. The platform only focuses on playback functionality and does not provide a solution for debugging.

检索中还发现，授权公告号为CN 100526910C，名称为“用于卫星导航接收机研发的平台系统”，该专利中的平台系统将导航接收机分为硬件部分和软件部分，软件部分运行于计算机上，硬件部分通过计算机接口通过计算机接口连接于所述计算机。由于软件运行于x86计算机上，软件实时性的分析就无法进行，因为x86处理器核嵌入式处理器存在着很大的差异。因此，该平台的运行和导航SoC真实芯片的运行情况存在很大差异的，很多嵌入式系统独有的问题都无法暴露出来。During the search, it was also found that the authorized announcement number is CN 100526910C, and the name is "a platform system for satellite navigation receiver research and development". The platform system in this patent divides the navigation receiver into a hardware part and a software part, and the software part runs on the computer. Above, the hardware part is connected to the computer through the computer interface. Since the software runs on an x86 computer, the real-time analysis of the software cannot be carried out, because there are great differences between x86 processors and embedded processors. Therefore, there is a big difference between the operation of the platform and the operation of the real chip of the navigation SoC, and many unique problems of the embedded system cannot be exposed.

目前已有的方案都只是关注于导航算法本身的软硬件划分，仅仅用FPGA对硬件加速模块进行验证，不关注与RISC处理器和导航硬件单元之间交互的时序，没有为SoC和芯片设计提供调试和验证机制。这些已有的方案无法评估导航算法在真实RISC处理器的实时性，尤其是中断的实时性。众所周知，中断处理是影响系统稳定性和运行效率很关键的因素。这些已有的方案所给出的软件代码在后期下载到RISC处理器时，会出现很难调试的漏洞，严重影响设计进度。The existing solutions only focus on the software and hardware division of the navigation algorithm itself, and only use the FPGA to verify the hardware acceleration module, without paying attention to the timing of the interaction between the RISC processor and the navigation hardware unit, and do not provide for SoC and chip design. Debugging and verification mechanisms. These existing solutions cannot evaluate the real-time performance of navigation algorithms on real RISC processors, especially the real-time performance of interrupts. As we all know, interrupt processing is a key factor affecting system stability and operating efficiency. When the software codes provided by these existing solutions are downloaded to the RISC processor in the later stage, loopholes that are difficult to debug will appear, seriously affecting the design progress.

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发明内容Contents of the invention

针对现有技术中存在的技术问题，本发明提供一种高效率的、可对软硬件实时性定量分析的、信号体制无关的基于UDP/USB协议的导航SoC芯片仿真、验证和调试平台。Aiming at the technical problems existing in the prior art, the present invention provides a UDP/USB protocol-based navigation SoC chip emulation, verification and debugging platform with high efficiency, real-time quantitative analysis of software and hardware, and signal system-independent.

为实现上述的目的，本发明采用的技术方案如下：本发明是为导航芯片设计开发服务的，关注的是片上系统的验证和调试。首先定制一块SoC系统验证板，板上带有RISC处理器和FPGA，配备有以太网接口或USB接口。与已有的大多数PC/FPGA协同仿真机制不同的是，本平台中导航程序运行在RISC处理器上。为硬件加入挂起模式，在中断程序中的某个阶段将导航加速器硬件和中断定时器挂起。在硬件挂起阶段PC主机将中频数据通过UDP协议或者USB协议导入到FPGA中的FIFO（先入先出队列），并完成调试信息的收集，之后导航IP恢复运行。为了支持实时性的精确评估，所有这些网络通信代码、调试信息收集代码都放在Non-Cacheable（不可缓存）的区域，降低对原有系统的干扰。主机建立完善的调试GUI程序和后台数据库，让设计人员可以利用这些调试信息对导航SoC芯片进行分析，进一步完善已有的算法架构和硬件设计。In order to achieve the above purpose, the technical solution adopted by the present invention is as follows: the present invention serves for the design and development of the navigation chip, focusing on the verification and debugging of the system on chip. First, customize a SoC system verification board with RISC processor and FPGA on the board, equipped with Ethernet interface or USB interface. Different from most existing PC/FPGA co-simulation mechanisms, the navigation program in this platform runs on the RISC processor. Add a suspend mode to the hardware, and suspend the navigation accelerator hardware and interrupt timer at a certain stage in the interrupt routine. In the hardware suspension stage, the PC host imports the IF data to the FIFO (first-in-first-out queue) in the FPGA through the UDP protocol or the USB protocol, and completes the collection of debugging information, and then the navigation IP resumes operation. In order to support accurate evaluation of real-time performance, all these network communication codes and debugging information collection codes are placed in the Non-Cacheable (non-cacheable) area to reduce interference to the original system. The host has established a complete debugging GUI program and background database, so that designers can use these debugging information to analyze the navigation SoC chip, and further improve the existing algorithm architecture and hardware design.

本发明提供一种导航SoC芯片仿真、验证和调试平台，该平台具体包括PC主机和SoC系统验证板，它们之间的通信通过UDP（用户数据包协议）或USB（通用串行总线）协议进行，所述PC主机通过UDP或者USB协议和握手机制完成中频数据向SoC系统验证板的导入，SoC系统验证板采集调试信息并返回给PC主机。The invention provides a navigation SoC chip emulation, verification and debugging platform, the platform specifically includes a PC host and a SoC system verification board, and the communication between them is carried out through UDP (User Data Packet Protocol) or USB (Universal Serial Bus) protocol , the PC host completes the import of intermediate frequency data to the SoC system verification board through the UDP or USB protocol and the handshake mechanism, and the SoC system verification board collects debugging information and returns it to the PC host.

所述SoC系统验证板上包括RISC处理器和FPGA芯片，其中FPGA与RISC处理器以总线方式或者短延时的接口进行通信。导航IP以RTL形式提供，综合实现在FPGA上。FPGA硬件上实现带有挂起模式的导航IP，RISC处理器上运行导航算法，在导航IP的辅助下完成定位解算功能。The SoC system verification board includes a RISC processor and an FPGA chip, wherein the FPGA communicates with the RISC processor through a bus or a short-delay interface. The navigation IP is provided in the form of RTL, and the synthesis is implemented on the FPGA. The navigation IP with suspend mode is implemented on the FPGA hardware, the navigation algorithm is run on the RISC processor, and the positioning and calculation function is completed with the assistance of the navigation IP.

所述RISC处理器通过内存管理单元MMU实现内存映射和Cache管理；RISC处理器所能控制的外设资源至少要有以太网控制器或者USB控制器，并与PC主机连接；导航所有C/C++程序都运行在RISC处理器上，主体上分为主程序和中断服务程序；中断服务程序负责与导航IP进行交互，典型中断间隔为520~800us；主程序利用中断服务程序返回的信息解算出坐标，这两条程序流互相配合完成卫星定位。The RISC processor implements memory mapping and Cache management through the memory management unit MMU; the peripheral resources that the RISC processor can control must at least have an Ethernet controller or a USB controller, and be connected to the PC host; navigate all C/C++ The programs all run on the RISC processor, and the main body is divided into the main program and the interrupt service program; the interrupt service program is responsible for interacting with the navigation IP, and the typical interrupt interval is 520~800us; the main program uses the information returned by the interrupt service program to calculate the coordinates , the two program streams cooperate with each other to complete the satellite positioning.

为了对实时性进行评估，RISC处理器应当能够访问到三个定时器资源，其中一个定时器完成固定时间的延时，另一个定时器完成中断触发，第三个定时器完成多个程序段运行时间的测量。这些定时器资源既可以分布在FPGA上，也可以处于RISC芯片内部。In order to evaluate real-time performance, the RISC processor should be able to access three timer resources, one of which completes a fixed-time delay, the other completes interrupt triggering, and the third completes multiple program segments. The measurement of time. These timer resources can be distributed on the FPGA or inside the RISC chip.

所述RISC处理器能够对导航硬件加速单元进行访问和读写，FPGA中必须根据开发板的情况配置好管脚连接。最自然的形式是FPGA与RISC处理器通过片上总线（以ARM为例，就是AMBA总线）或者PCI-E总线进行连接。The RISC processor can access and read and write the navigation hardware acceleration unit, and the pin connection must be configured in the FPGA according to the situation of the development board. The most natural form is that FPGA and RISC processor are connected through on-chip bus (taking ARM as an example, AMBA bus) or PCI-E bus.

所述导航硬件加速单元（简称导航IP）的RTL代码中必须加入对挂起模式的支持(以clk_enable时钟使能的方式实现)，外部处理器可以通过寄存器读写的方式改变导航IP的运行/挂起状态，使其暂停，然后继续执行。The RTL code of the navigation hardware acceleration unit (referred to as the navigation IP) must add support for the suspend mode (realized in the way of clk_enable clock enablement), and the external processor can change the operation of the navigation IP by register reading and writing. The suspend state causes it to pause and then resume execution.

所述RISC处理器上运行的中断函数分为硬件运行阶段和硬件挂起阶段。硬件挂起阶段PC主机通过以太网/USB接口向FPGA批量传入导航数据；FPGA上有相应的FIFO以存储这些数据；调试信息的收集和返回也是在此阶段完成。The interrupt function running on the RISC processor is divided into a hardware running phase and a hardware suspending phase. In the hardware suspend stage, the PC host sends navigation data to the FPGA in batches through the Ethernet/USB interface; there is a corresponding FIFO on the FPGA to store these data; the collection and return of debugging information is also completed at this stage.

所述PC端存储导航中频数据，PC主机与SoC验证板通过UDP或者USB协议进行握手和通信。PC主机应当带有网口或者USB接口。The PC end stores navigation intermediate frequency data, and the PC host and the SoC verification board perform handshake and communication through UDP or USB protocol. The PC host should have a network port or a USB port.

所述PC主机分为四个线程，分别是GUI图形界面线程、调试系统主控线程、数据库线程和UDP/USB通信线程。主控线程负责其它三个线程之间资源的分配、通信的冲裁。UDP/USB通信线程负责和SoC验证板进行通信。数据库线程对通信传输过来的调试信息进行分类存储，并支持用户对这些信息进行检索，数据库线程还负责中频数据数据源的调入。图形界面让设计人员可以以直观的方式查看调试信息和实时性信息、绘制波形以及控制接收机的运行。The PC host is divided into four threads, namely GUI graphic interface thread, debugging system main control thread, database thread and UDP/USB communication thread. The main control thread is responsible for resource allocation and communication punching among the other three threads. The UDP/USB communication thread is responsible for communicating with the SoC verification board. The database thread classifies and stores the debugging information transmitted by communication, and supports users to retrieve these information. The database thread is also responsible for the transfer of intermediate frequency data sources. The graphical interface allows designers to view debug and real-time information, draw waveforms, and control receiver operation in an intuitive manner.

本发明中，在中断服务程序的硬件挂起阶段，以可控的模式将导航中频数据传送到FPGA中的FIFO（先入先出队列）。FIFO被封装为处理器所在总线的外设，映射到内存中的一段区域，处理器以内存读写的方式向FIFO批量写入数据，在将来一段时期为硬件IP模块提供数据。In the present invention, in the hardware suspension stage of the interrupt service program, the navigation intermediate frequency data is transmitted to the FIFO (first-in-first-out queue) in the FPGA in a controllable mode. FIFO is encapsulated as a peripheral of the bus where the processor is located, and is mapped to a section of the memory. The processor writes data to the FIFO in batches in the form of memory reading and writing, and provides data for the hardware IP module in the future.

RISC/FPGA验证板检查中频数据FIFO的剩余，在每个中断函数中向PC端发起数据请求，PC端遵循握手机制将导航中频数据返回给SoC系统验证板。RISC处理器端的调试信息收集程序将接收机状态、调试信息、解算结果以及实时性分析等相关信息通传送到PC端进一步分析。这些调试信息将以小包的形式填充整个以太网数据包，然后再PC主机端完成这些数据包的拆分和解析，随后填入后台的数据库，GUI界面将根据设计人员的操作，完成对数据库的检索，取出这些信息以波形或者表格的形式展现这些信息，进行时间精度为中断级别的调试。The RISC/FPGA verification board checks the remainder of the IF data FIFO, and initiates a data request to the PC in each interrupt function, and the PC returns the navigation IF data to the SoC system verification board following the handshake mechanism. The debugging information collection program on the RISC processor end transmits relevant information such as receiver status, debugging information, calculation results, and real-time analysis to the PC end for further analysis. These debugging information will fill the entire Ethernet data packet in the form of small packets, and then the PC host will complete the splitting and analysis of these data packets, and then fill in the background database. The GUI interface will complete the database according to the operation of the designer. Retrieve, take out the information and display the information in the form of waveform or table, and perform debugging with time precision at the interrupt level.

这些UDP/USB通信的附加代码通过链接脚本和MMU（内存管理单元）的设定，放置于Non-Cacheable的区域，RISC处理器的Cache（高速缓冲存储器）将受到最小的干扰，这样就可以对原始的导航算法软件的实时性进行准确的估计。并且，通过时序逻辑使能的方式，使得FPGA上运行的导航IP支持挂起模式，在RISC处理器的控制下，在网络通信阶段（即运行附加代码的阶段）导航IP和定时器将处于挂起模式，此时导航算法本身的软硬件逻辑都没有运行，设计人员可以充分加入调试信息代码，调试信息可以充分的被收集，而不会受限于RISC处理器的性能，也不会影响到实时性的测量。These additional codes for UDP/USB communication are placed in the Non-Cacheable area through link scripts and MMU (memory management unit) settings, and the Cache (cache memory) of the RISC processor will be minimally disturbed, so that the The real-time performance of the original navigation algorithm software is accurately estimated. Moreover, the navigation IP running on the FPGA supports the suspend mode by enabling the sequential logic. Under the control of the RISC processor, the navigation IP and the timer will be in the suspend mode during the network communication phase (that is, the phase of running additional codes). At this time, the software and hardware logic of the navigation algorithm itself is not running, and the designer can fully add debugging information codes, and the debugging information can be fully collected without being limited by the performance of the RISC processor or affecting the real-time measurement.

这些附加代码是在Non-Cacheable的形式让RISC处理器运行的，所以处理器的性能越高、总线通信带宽越高，整个平台的仿真性能就越高。该方案是协议无关的，兼容主流的USB2.0和UDP通信协议。These additional codes are run by the RISC processor in the form of Non-Cacheable, so the higher the performance of the processor and the higher the bus communication bandwidth, the higher the simulation performance of the entire platform. The scheme is protocol-independent and compatible with mainstream USB2.0 and UDP communication protocols.

本发明的技术效果如下：Technical effect of the present invention is as follows:

本发明的导航SoC芯片仿真、验证和调试平台，在X86主机和ARM RealView Emulation Board平台（RISC处理器选择了业界最通用的ARM处理器）相互配合下能够以1:7的速度比对导航接收机进行仿真，并完成调试信息的收集，设计人员可以以中断为基本单位控制整个接收机的运行。整个平台可以高效可靠地工作，远远超过HDL仿真器RTL仿真的速度，并且支持对嵌入式系统实时性进行分析。设计人员可以通过GUI界面控制导航SoC验证板软硬件部分的运行，从数据库中检索调试信息和实时性信息，调试信息和实时性数据更好地分析整体系统的瓶颈，完善导航SoC芯片架构，调整算法和优化代码，为后期芯片实现做好充足的准备。The navigation SoC chip emulation, verification and debugging platform of the present invention can compare the navigation reception at a speed of 1:7 under the mutual cooperation of the X86 host and the ARM RealView Emulation Board platform (the RISC processor selects the most common ARM processor in the industry). The machine is simulated, and the collection of debugging information is completed, and the designer can control the operation of the entire receiver with the interrupt as the basic unit. The whole platform can work efficiently and reliably, far exceeding the speed of HDL emulator RTL simulation, and supports the real-time analysis of embedded systems. Designers can control the operation of the hardware and software of the navigation SoC verification board through the GUI interface, retrieve debugging information and real-time information from the database, and use the debugging information and real-time data to better analyze the bottleneck of the overall system, improve the architecture of the navigation SoC chip, and adjust Algorithms and optimized codes are fully prepared for later chip implementation.

附图说明Description of drawings

图1是导航SoC软件运行的典型流程图；Figure 1 is a typical flow chart of navigation SoC software operation;

图2是导航SoC芯片的系统结构图；Fig. 2 is a system structure diagram of a navigation SoC chip;

图3是本发明实施例中加入中频数据回放机制的导航SoC验证板的典型配置图；Fig. 3 is a typical configuration diagram of a navigation SoC verification board adding an intermediate frequency data playback mechanism in an embodiment of the present invention;

图4是本发明在图3的基础上加入硬件挂起模式的SoC系统验证板的结构框图；Fig. 4 is the structural block diagram of the SoC system verification board that the present invention adds hardware suspend mode on the basis of Fig. 3;

图5是本发明实施例中添加中频数据回放和调试信息传输的中断函数处理流程图；5 is a flow chart of interrupt function processing for adding intermediate frequency data playback and debugging information transmission in an embodiment of the present invention;

图6是本发明实施例中链接脚本所对应的MMU配置和内存映射框图；Fig. 6 is a block diagram of MMU configuration and memory mapping corresponding to the link script in the embodiment of the present invention;

图7是本发明实施例中PC主机程序总体框架和导航SoC系统验证板的信息通路示意图。Fig. 7 is a schematic diagram of the overall framework of the PC host program and the information path of the navigation SoC system verification board in the embodiment of the present invention.

 the

具体实施方式Detailed ways

以下对本发明的技术方案作进一步的说明，以下的说明仅为理解本发明技术方案之用，不用于限定本发明的范围，本发明的保护范围以权利要求书为准。 The technical solution of the present invention is further described below. The following description is only for understanding the technical solution of the present invention, and is not used to limit the scope of the present invention. The scope of protection of the present invention is based on the claims. the

下面结合附图对本发明的导航SoC芯片仿真、验证和调试平台进一步详细描述，以下描述均以ARM处理器和AHB总线为例，如果是其它RISC处理器或其它总线形式，请适当修改。The navigation SoC chip emulation, verification and debugging platform of the present invention will be further described in detail below in conjunction with the accompanying drawings. The following descriptions are all based on the ARM processor and the AHB bus. If it is other RISC processors or other bus forms, please modify it appropriately.

步骤一，定制导航SoC芯片验证板。如图2是导航SoC芯片的系统结构图，它直接从射频前端得到中频数据，这些数据进入硬件加速IP进行处理，RISC处理器或者DSP在硬件加速器的协助下完成坐标的定位，本实施例中不需要射频前端的支持。所定制的SoC验证板上带有ARM处理器和FPGA，跟主机通过UDP或者USB协议进行通信。Step 1, customize the navigation SoC chip verification board. Figure 2 is a system structure diagram of the navigation SoC chip, which directly obtains intermediate frequency data from the radio frequency front end, and these data enter the hardware acceleration IP for processing, and the RISC processor or DSP completes the positioning of the coordinates with the assistance of the hardware accelerator. In this embodiment No RF front-end support is required. The customized SoC verification board is equipped with ARM processor and FPGA, and communicates with the host through UDP or USB protocol.

步骤二，加入数据回放的支持。如途3所示，是本发明实施例中加入中频数据回放机制的导航SoC验证板的典型配置图。FPGA中例化FIFO模块，由于我们不会同时对FIFO进行读写操作，所以同步型或异步型的FIFO均满足要求。FIFO对应于总线的两个地址，分别是：Step 2, add support for data playback. As shown in Fig. 3, it is a typical configuration diagram of the navigation SoC verification board added with the intermediate frequency data playback mechanism in the embodiment of the present invention. The FIFO module is instantiated in the FPGA. Since we will not read and write FIFO at the same time, both synchronous and asynchronous FIFOs meet the requirements. FIFO corresponds to two addresses of the bus, which are:

l      地址0 数据写入寄存器，以目前主流的32bit数据宽度写入；l address 0 data write register, write in the current mainstream 32bit data width;

l      地址1 FIFO有效单元寄存器，返回当前FIFO中剩余字的数量，导航中断程序需要该寄存器来获得FIFO的信息，以确定下一次向PC端应该请求多少数据；l Address 1 FIFO effective unit register, which returns the number of remaining words in the current FIFO. The navigation interrupt program needs this register to obtain FIFO information to determine how much data should be requested from the PC next time;

FIFO模块和导航IP核都在FPGA中实现，ARM通过总线对其可以进行控制。Both the FIFO module and the navigation IP core are implemented in the FPGA, which can be controlled by the ARM through the bus.

步骤三，为导航IP加入硬件挂起模式的支持。导航IP以RTL的形式提供，根据处理器与FPGA连接形式的不同，该导航IP外层将具备不同的总线接口。以ARM RealView Emulation Board为例，ARM处理器对外为AHB接口，因此该导航相关器IP必须搭载AHB接口。假如是以其它方式连接的，导航IP必须搭载不同的接口逻辑。例如，如果是or1200微处理器，则可搭配wishbone接口。Step 3, add support for hardware suspend mode for navigation IP. The navigation IP is provided in the form of RTL. Depending on the connection form between the processor and the FPGA, the outer layer of the navigation IP will have different bus interfaces. Taking the ARM RealView Emulation Board as an example, the ARM processor has an external AHB interface, so the navigation correlator IP must be equipped with an AHB interface. If it is connected in other ways, the navigation IP must carry different interface logic. For example, if it is an or1200 microprocessor, it can be matched with a wishbone interface.

图4是本发明在图3的基础上加入硬件挂起模式的SoC系统验证板的结构框图。给RTL（寄存器传输级）代码加入对挂起模式的支持方法说明如下，一般来说硬件IP核的代码都是基于全同步的风格描述，以Verilog为例，每个module一般包含如下风格的描述的同步时序逻辑语句（见左栏）：FIG. 4 is a block diagram of the structure of the SoC system verification board in which the hardware suspend mode is added on the basis of FIG. 3 according to the present invention. The method of adding support for the suspend mode to the RTL (register transfer level) code is described as follows. Generally speaking, the code of the hardware IP core is based on a fully synchronous style description. Taking Verilog as an example, each module generally includes the following style description The synchronous temporal logic statement (see left column):

修改后的代码如右栏所示，在顶层预编译文件加入`define SUSPEND_SUPPORT，并且在所有包含同步时序逻辑的模块端口中加入pd_n端口（见图3）。只要是全同步描述的可综合的硬件模块都可以按照这样的方式被改造成支持挂起模式的模块。The modified code is shown in the right column. Add `define SUSPEND_SUPPORT to the top-level precompiled file, and add the pd_n port to all module ports containing synchronous timing logic (see Figure 3). All synthesizable hardware modules that are fully synchronously described can be transformed into modules that support the suspend mode in this way.

对应于挂起模式和运行模式，需要添加两个寄存器，处理器对这两个寄存器的写入就可以切换硬件IP的工作模式。这两个寄存器控制IP核的pd_n端口，对寄存器suspend_reg写入，pd_n置为低电平，使得导航IP进入挂起模式；对寄存器wakeup_reg写入，pd_n置为高电平，导航IP继续运行。Corresponding to the suspend mode and the running mode, two registers need to be added, and the processor can switch the working mode of the hardware IP by writing to these two registers. These two registers control the pd_n port of the IP core, write to the register suspend_reg, and set pd_n to low level, so that the navigation IP enters the suspend mode; write to the register wakeup_reg, set pd_n to high level, and the navigation IP continues to run.

步骤四，为验证本配置定时器资源。板上需要有三个定时器资源A、B、C，这三个资源都要能被ARM处理器利用，叙述如下：Step 4, configure timer resources for verification. There need to be three timer resources A, B, and C on the board. These three resources must be able to be used by the ARM processor. The description is as follows:

l      定时器A: 支持固定时间的延时，比如delayus()和delayms()的函数分布完成微妙级和毫秒级的延时；l Timer A: supports fixed-time delays, such as the function distribution of delayus() and delayms() to complete delays at the subtle and millisecond levels;

l      定时器B: 支持实时性的测量，以下是程序运行时间间隔测量代码例子，用以对一段代码的运行时间进行测量（定时器向下计数）：l Timer B: Supports real-time measurement. The following is an example of the program running time interval measurement code, which is used to measure the running time of a piece of code (the timer counts down):

t_start = timerB_cnt();  // 起始t_start = timerB_cnt(); // start

codeA to_measure…codeA to_measure…

codeA_duration = timerB_cnt() – t_start; // 结束codeA_duration = timerB_cnt() – t_start; // end

codeA_duration就是codeA代码所运行的时间，其精度与定时器B的最小分辨率有关，典型值为1us。codeA_duration is the running time of the codeA code, and its accuracy is related to the minimum resolution of timer B, with a typical value of 1us.

l      定时器C：中断信号定时器，如图1的软件运行流程中，需要中断信号来触发处理器进入中断服务例程；l Timer C: interrupt signal timer, in the software running process shown in Figure 1, an interrupt signal is needed to trigger the processor to enter the interrupt service routine;

步骤五，RISC处理器上软件流程的规划，特别注重实时性评估的支持。ARM处理器上的程序分为导航算法软件和网络通信软件两个部分。其中导航算法软件中包含中断处理函数，我们的网络通信软件就运行在中断处理函数的硬件挂起阶段。如图5是本发明实施例中添加中频数据回放和调试信息传输的中断函数处理流程图。网络通信软件完成中频数据的回放和调试信息的统计，这些代码相对于导航算法软件而言属于附加代码。如果不特殊处理，这些代码会干扰Cache的内容，在最差情况下，处理器Cache会随着附加代码的运行而完全替换成附加代码的内容。下一次重新执行导航算法软件的时候，处理器不得不重新从外部RAM中读入代码和数据，这和芯片实际运行的情况不符合，会干扰实时性的评估。Step five, the planning of the software process on the RISC processor, with special emphasis on the support of real-time evaluation. The program on the ARM processor is divided into two parts: navigation algorithm software and network communication software. Among them, the navigation algorithm software includes an interrupt processing function, and our network communication software runs in the hardware suspension stage of the interrupt processing function. FIG. 5 is a flow chart of interrupt function processing for adding intermediate frequency data playback and debugging information transmission in the embodiment of the present invention. The network communication software completes the playback of intermediate frequency data and the statistics of debugging information. Compared with the navigation algorithm software, these codes are additional codes. If not handled specially, these codes will interfere with the content of the Cache. In the worst case, the processor Cache will be completely replaced with the content of the additional code as the additional code runs. When the navigation algorithm software is re-executed next time, the processor has to re-read the code and data from the external RAM, which is inconsistent with the actual operation of the chip and will interfere with the real-time evaluation.

为了对实时性进行正确评估，排除附加代码所引入Cache的不确定性。在本套方案中，需要借助于MMU页管理机制来配置不同内存区域的Cache支持。根据系统板互连方式的不同，MMU也有多种配置模式。但基本思路如下（在链接文件体现）：In order to correctly evaluate the real-time performance, the uncertainty of the Cache introduced by the additional code is eliminated. In this solution, it is necessary to use the MMU page management mechanism to configure the Cache support of different memory areas. The MMU also has multiple configuration modes depending on how the system boards are interconnected. But the basic idea is as follows (reflected in the linked file):

l      内存空间在MMU中划分为可Cache和不可Cache两个区域；l The memory space in the MMU is divided into two areas that can be cached and cannot be cached;

l      附加代码的堆栈空间用得越少越好，或者堆栈也指向不可Cache的区域；l The less the stack space for the additional code is, the better, or the stack also points to a non-cacheable area;

l      附加代码映射到Non-Cacheable区域，对应于图5，即networkProcess.cpp和dataCollect.cpp编译单元放置到Non-Cacheable的区域。l The additional code is mapped to the Non-Cacheable area, corresponding to Figure 5, that is, the networkProcess.cpp and dataCollect.cpp compilation units are placed in the Non-Cacheable area.

其工作流程如图5，下面给予说明：Its workflow is shown in Figure 5, and is explained below:

定时器每隔一段时间触发一次导航中断服务程序，中断服务程序第一步就是暂停相关器和中断定时器。需要注意的是此时延迟定时器和实时性测量定时器依然在运行，即延时函数Delayus()和代码运行时间测量的机制依然被支持。本实施例中，可以在中断函数以及主程序的各个部分插入时间间隔测量代码。The timer triggers the navigation interrupt service routine every once in a while, and the first step of the interrupt service routine is to suspend the correlator and the interrupt timer. It should be noted that the delay timer and real-time measurement timer are still running at this time, that is, the delay function Delayus() and the mechanism of code running time measurement are still supported. In this embodiment, time interval measurement codes can be inserted into the interrupt function and each part of the main program.

步骤六，调试信息收集的支持，不干扰对原导航SoC芯片系统实时性的评估。增加统一的调试信息数据池，集中在同一个编译单元dataCollect。它通过extern的方式引用其它单元的数据，不需要修改其它编译单元的代码，收集到的数据将传递给主机。Step six, the support of debugging information collection does not interfere with the evaluation of the real-time performance of the original navigation SoC chip system. Add a unified debugging information data pool, which is concentrated in the same compilation unit dataCollect. It refers to the data of other units through extern, without modifying the codes of other compilation units, and the collected data will be passed to the host.

为了更好的在链接脚本中对内存空间进行划分，使得整个平台方案具有通用性。RISC这一端的编程应该做如下约定。如图5：networdProcess处理网络通信（仅在SoC验证板的中断服务发生）的内容包含有：In order to better divide the memory space in the link script, the whole platform solution is universal. The programming at this end of RISC should have the following conventions. As shown in Figure 5: the content of networkProcess processing network communication (only occurs in the interrupt service of the SoC verification board) includes:

l      导航SoC验证板向PC请求数据；l The navigation SoC verification board requests data from the PC;

l      PC向导航SoC芯片板传送导航中频数据，以支持数据回放；l The PC transmits navigation intermediate frequency data to the navigation SoC chip board to support data playback;

l      导航SoC验证板向PC机发送调试信息；l The navigation SoC verification board sends debugging information to the PC;

调试信息内容的收集在dataCollect.cpp模块中进行，在数据池中填充好内容之后，networkProcess.cpp模块会把数据池中的内容进一步处理发送给主机。图6是本发明实施例中链接脚本所对应的MMU配置和内存映射框图，其中networkProcess.cpp模块以及dataCollect.cpp模块的内容都是放在Non-Cahceable的内存区域，而导航算法中断函数（网络通信部分除外）和算法主程序都是Cacheable。The collection of debugging information is carried out in the dataCollect.cpp module. After filling the content in the data pool, the networkProcess.cpp module will further process the content in the data pool and send it to the host. Fig. 6 is the block diagram of MMU configuration and memory mapping corresponding to the link script in the embodiment of the present invention, wherein the contents of the networkProcess. Except for the communication part) and the algorithm main program are both Cacheable.

通过MMU单元管理内存页面的Cache开关。UDP/USB通信附加代码对原始系统的干扰降到最低，不会去占用Cache空间，整个系统的运行将非常接近于实际芯片内部SoC系统的运行情况。The Cache switch of the memory page is managed by the MMU unit. The UDP/USB communication additional code minimizes the interference to the original system and does not occupy the Cache space. The operation of the entire system will be very close to the operation of the SoC system inside the actual chip.

步骤六，PC主机建立完善的调试环境，与导航SoC芯片验证板配合。图7是本发明实施例中PC主机程序总体框架和导航SoC系统验证板的信息通路示意图。、仿真验证调试平台必须提供丰富的信息供设计人员查看，因此GUI界面必不可少。PC端调试平台分为四个线程：Step 6: The PC host establishes a complete debugging environment and cooperates with the navigation SoC chip verification board. Fig. 7 is a schematic diagram of the overall framework of the PC host program and the information path of the navigation SoC system verification board in the embodiment of the present invention. , The simulation verification debugging platform must provide rich information for designers to view, so the GUI interface is essential. The PC-side debugging platform is divided into four threads:

线程一：UDP/USB线程，负责向SoC系统板传送导航中频数据及接收调试信息；Thread 1: UDP/USB thread, responsible for transmitting navigation IF data to SoC system board and receiving debugging information;

线程二：数据库线程，将导航SoC芯片验证板传送过来的调试信息存储在数据库内，以方便调试人员对数据进行检索操作和存取操作；Thread 2: database thread, which stores the debugging information sent by the navigation SoC chip verification board in the database, so as to facilitate the retrieval operation and access operation of the data by the debugger;

线程三：图形界面线程，设计人员可以观看到卫星的分布、接收机的状态以及实时性信息，调试人员可以有选择的查看、筛选信息并绘制出波形；Thread 3: Graphical interface thread, designers can view satellite distribution, receiver status and real-time information, debuggers can selectively view, filter information and draw waveforms;

线程四：调试系统主控线程，用来分配其它三个线程资源的分配，以及它们之间通信的仲裁；Thread 4: The main control thread of the debugging system is used to allocate the resources of the other three threads and the arbitration of communication between them;

至此，导航SoC芯片仿真、验证和调试平台搭建完成。So far, the navigation SoC chip simulation, verification and debugging platform has been built.

整个平台是为导航接收机芯片的设计服务的，无论是算法的验证还是硬件的调试，设计人员都可以从中得到丰富的信息以修正改善原有的设计。本平台的一大亮点在于加入了对实时性的调试，从定时器的配置到MMU的设置，以及链接脚本的编写，都是为准确得到实时性而努力的，力求减少调试系统本身对原有系统（即导航SoC本身）的干扰，可以真实反映出导航芯片中SoC系统的运行结果和实时性信息，为下一步后仿真乃至流片验证做好准备。The whole platform serves for the design of the navigation receiver chip, whether it is algorithm verification or hardware debugging, designers can get rich information from it to correct and improve the original design. One of the highlights of this platform is the addition of real-time debugging. From the configuration of the timer to the setting of the MMU, and the writing of link scripts, all efforts are made to accurately obtain real-time performance, and strive to reduce the debugging system itself. The interference of the system (that is, the navigation SoC itself) can truly reflect the running results and real-time information of the SoC system in the navigation chip, and prepare for the next step of post-simulation and even tape-out verification.

利用本发明平台能够将存储在PC主机上的导航中频数据通过以太网或者USB接口有序地输入到导航IP中，而调试人员可以以中断为最小单位以single-step（单步执行）或者free-running（自由运行）的方式控制整个系统的运行，并且可以从该系统的反馈结果中得到关于软硬件实时性、导航接收机各个通道的状态和导航解算各个方面的信息，所有这些信息通过UDP或者USB协议从SoC小系统验证板传送到PC机上，随后存储在后台数据库，以便设计人员通过GUI界面（图形用户界面）从数据库中检索、读取、显示这些信息。导航算法软件运行在RISC处理器上，导航IP实现在FPGA上，整个平台运行结果尽可能接近于实际导航芯片中SoC系统的运行结果。同时，通过一种机制让导航硬件加速IP支持挂起/执行机制，该调试平台所添加的附加代码对原系统的Cache、中断实时性均无影响，在这些措施下，可以更加准确地评估软硬件的实时性。Utilizing the platform of the present invention, the navigation intermediate frequency data stored on the PC host can be sequentially input into the navigation IP through the Ethernet or USB interface, and the debugger can use the interrupt as the smallest unit to execute single-step (single-step execution) or free -running (free running) mode controls the operation of the entire system, and can obtain information about the real-time performance of software and hardware, the status of each channel of the navigation receiver, and various aspects of navigation calculations from the feedback results of the system, all of which are passed through The UDP or USB protocol is transmitted from the SoC small system verification board to the PC, and then stored in the background database, so that designers can retrieve, read and display the information from the database through the GUI interface (graphical user interface). The navigation algorithm software runs on the RISC processor, and the navigation IP is implemented on the FPGA. The running result of the whole platform is as close as possible to the running result of the SoC system in the actual navigation chip. At the same time, through a mechanism, the navigation hardware acceleration IP supports the suspend/execution mechanism. The additional code added by the debugging platform has no impact on the original system's Cache and interrupt real-time performance. Under these measures, the software can be more accurately evaluated. hardware real-time.

综上，本发明平台的硬件模型兼容由ARM、MIPS等主流的RISC处理器和Xilinx、Altera等FPGA构建的SoC系统验证板，与PC的通信基于UDP协议或者USB协议，设计和调试人员可以通过PC主机对导航SoC系统的运行进行中断级别的控制和调试信息的收集，精确评估软硬件的实时性，兼容多种导航系统，包括GPS、伽利略、北斗和GLONASS系统，是导航芯片设计验证领域强有力的工具。In summary, the hardware model of the platform of the present invention is compatible with SoC system verification boards constructed by mainstream RISC processors such as ARM and MIPS and FPGAs such as Xilinx and Altera. The communication with the PC is based on the UDP protocol or the USB protocol. Design and debugging personnel can pass The PC host controls the operation of the navigation SoC system at an interrupt level and collects debugging information, accurately evaluates the real-time performance of software and hardware, and is compatible with various navigation systems, including GPS, Galileo, Beidou and GLONASS systems. It is a strong field of navigation chip design verification. powerful tool.

以上所述仅为本发明的较佳实施例而已，并非对本发明的技术范围做任何限制，凡在本发明的精神和原则之内做的任何修改，等同替换和改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the technical scope of the present invention. Any modifications made within the spirit and principles of the present invention, equivalent replacements and improvements, etc., shall be included in this document. within the scope of protection of the invention.

Claims (10)

1. a navigation SoC chip emulation, checking and debug platform is characterized in that comprising: PC main frame and SoC system verification plate, and the communication between them is carried out through UDP or usb protocol; Said PC main frame passes through UDP or usb protocol and handshake mechanism and accomplishes the importing of intermediate frequency data to SoC system verification plate, and SoC system verification plate is gathered Debugging message and also returned to the PC main frame; Wherein:

Comprise risc processor and fpga chip on the said SoC system verification plate, said fpga chip and risc processor communicate with the interface of bus mode or short time delay, and navigation IP provides with the RTL form, comprehensively is implemented on the FPGA; Realize having the navigation IP of Suspend Mode on the FPGA hardware, move navigation algorithm on the risc processor, in the auxiliary positioning calculation function of accomplishing down of navigation IP.

2. navigation SoC chip emulation according to claim 1, checking and debug platform is characterized in that: said risc processor is realized memory-mapped and Cache management through the MMU memory management unit; The peripheral hardware resource that said risc processor can be controlled will have ethernet controller or USB controller at least, and is connected with the PC main frame; All C/C++ programs of navigating all operate on the risc processor, are divided into master routine and interrupt service routine on the main body; Interrupt service routine is responsible for carrying out alternately with navigation IP, and the information that master routine utilizes interrupt service routine to return calculates coordinate, these two program flows completion satnav of working in coordination.

3. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said risc processor is supported interrupt mechanism, and the timer resource more than three is arranged, and one of them timer is accomplished the time-delay of set time; Another timer is accomplished and is interrupted setting out; The 3rd timer accomplished the measurement of working time of a plurality of program segment, and these timer resource distributions or are in risc chip inside on FPGA.

4. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said risc processor can conduct interviews and reads and writes the hardware-accelerated unit that navigates, and FPGA is connected through sheet external bus or PCI-E bus with risc processor.

5. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said PC main frame is deposited the navigation intermediate frequency data; The PC main frame is shaken hands and is communicated by letter through UDP or usb protocol with the SoC verification system, and the PC main frame has network interface or USB interface.

6. navigation SoC chip emulation, checking and the debug platform narrated according to claim 1 or 2; It is characterized in that: add support in the RTL code of said navigation IP Suspend Mode; The mode that enables with the clk_enable clock realizes; Ppu can change operation/suspended state of navigation IP through the mode of register read-write, makes its time-out, continues then to carry out.

7. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: the interrupt service routine that moves on the said risc processor is divided into the hardware operation phase and hardware is hung up the stage, and hardware is hung up stage PC main frame and imported navigation data through Ethernet/USB interface in batches into to FPGA; FPGA is last to have corresponding FIFO to store these data; The collection of Debugging message and to return also be to accomplish in this in stage.

8. navigation SoC chip emulation according to claim 7, checking and debug platform; It is characterized in that: the hardware at interrupt service routine is hung up the stage; Be sent to the FIFO among the FPGA with the controlled pattern intermediate frequency data that will navigate, FIFO is encapsulated as the peripheral hardware of processor place bus, is mapped to one section zone in the internal memory; Processor writes data with the mode of memory read-write to FIFO in batches, for Hardware I P module provides data; The residue of systems inspection intermediate frequency data FIFO is initiated request of data to PC end in each interrupt function, the PC end is followed the handshake mechanism intermediate frequency data that will navigate and returned to SoC system verification plate; The Debugging message collection procedure of risc processor end with receiver state, Debugging message, resolve result and real-time analytical information and be sent to the PC end and further analyze; These information will be filled whole Ethernet data bag with the form of parcel; The PC host side is accomplished the fractionation and the parsing of these packets more then; Insert the database on backstage subsequently; Gui interface is accomplished the retrieval to database according to operation of designer, takes out these information and represents these information with the form of waveform or form, carries out the debugging that time precision is an interrupt levels; The extracode of these UDP/USB communications is positioned over the zone of Non-Cacheable through the setting of link script and memory management unit MMU.

9. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said risc processor is through the operation real-time quantification of timer to software and hardware; Accurately the working time of Survey Software code, debug information collection that this platform is introduced and intermediate frequency data playback extracode are through memory-mapped and Cache administrative mechanism; Noiseless basically to the navigation original program, the real-time analysis result is accurate.

10. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said PC main frame is divided into four threads; Be respectively GUI graphical interfaces thread, debug system master control thread, database thread and UDP/USB communication thread, wherein: the master control thread is responsible for the distribution of resource between other three threads, the arbitration of communication; The UDP/USB communication thread is responsible for communicating with the SoC witness plate; The Debugging message that database thread is come to communications carries out classification and storage, and supports that the user retrieves these information, and database thread also is responsible for calling in of intermediate frequency data data source; Graphical interfaces lets the designer check the operation of Debugging message and real-time information, drawing waveforms and receiver control with mode intuitively.

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