CN102403216B - Wet etching method for preparation of super-junction device - Google Patents

Abstract

Translated fromChinese

本发明公开了一种使用湿法刻蚀制备超级结器件的方法，包括：一，在硅基板上成长外延层；二，在硅片的正反面形成介质膜；三，正面用光刻胶定义图形，干法刻蚀打开介质膜；四，去除光刻胶，用介质膜作为掩膜层，使用湿法各向异性刻蚀形成垂直的深沟槽；五，清洗后在深沟槽内填充成长与步骤一外延层类型相反的外延层，以形成交替排列的P型和N型结构；六，用化学机械抛光法进行平坦化处理，停在介质膜上；七，用湿法刻蚀去除正反面的介质膜；八，后续工艺采用成熟的纵向双扩散金属氧化物半导体即可制备完整的超级结器件。本发明对硅基板损伤较小，减少PN结界面缺陷，降低漏电流，且能保证深沟槽的垂直形貌和面内形貌均匀性，还可降低生产成本。

The invention discloses a method for preparing a super junction device by wet etching, comprising: 1. growing an epitaxial layer on a silicon substrate; 2. forming a dielectric film on the front and back of a silicon wafer; Graphics, open the dielectric film by dry etching; 4. Remove the photoresist, use the dielectric film as a mask layer, and use wet anisotropic etching to form vertical deep trenches; 5. Fill the deep trenches after cleaning Growing an epitaxial layer of the opposite type to that of the epitaxial layer in step 1 to form alternately arranged P-type and N-type structures; Sixth, use chemical mechanical polishing to planarize and stop on the dielectric film; Seventh, use wet etching to remove The dielectric film on the front and back sides; Eighth, the subsequent process adopts the mature vertical double-diffused metal oxide semiconductor to prepare a complete super junction device. The invention has less damage to the silicon substrate, reduces PN junction interface defects, reduces leakage current, can ensure the vertical shape and in-plane shape uniformity of the deep groove, and can also reduce production costs.

Description

Translated fromChinese

使用湿法刻蚀制备超级结器件的方法Method for fabricating superjunction devices using wet etching

技术领域technical field

本发明属于半导体集成电路制造领域，具体涉及一种使用湿法刻蚀制备超级结器件的方法。The invention belongs to the field of semiconductor integrated circuit manufacturing, and in particular relates to a method for preparing a super junction device by wet etching.

背景技术Background technique

超级结器件的特征在于形成交替排列的P型半导体薄层和N型半导体薄层，利用P型半导体薄层和N型半导体薄层耗尽，实现电荷相互补偿的原理，使P型半导体薄层和N型半导体薄层在高掺杂浓度下能实现高的击穿电压，从而同时获得低导通电阻和高击穿电压。超级结器件结构的一种形成方式是在N型外延层上开深沟槽，然后再填入P型外延，形成交替排列的P型和N型的结构。The super junction device is characterized by the formation of alternately arranged P-type semiconductor thin layers and N-type semiconductor thin layers, using the principle of depletion of P-type semiconductor thin layers and N-type semiconductor thin layers to realize mutual charge compensation, so that the P-type semiconductor thin layers And N-type semiconductor thin layer can achieve high breakdown voltage under high doping concentration, so as to obtain low on-resistance and high breakdown voltage at the same time. One way of forming the super junction device structure is to open a deep trench on the N-type epitaxial layer, and then fill it with P-type epitaxial layers to form alternately arranged P-type and N-type structures.

在目前的工艺中，深沟槽刻蚀多采用干法刻蚀，比较容易对硅基板造成损伤，而且成本也比较高。In the current process, dry etching is mostly used for deep trench etching, which is relatively easy to cause damage to the silicon substrate, and the cost is relatively high.

发明内容Contents of the invention

本发明要解决的技术问题是提供一种使用湿法刻蚀制备超级结器件的方法，该方法对硅基板损伤较小，能保证后续的外延层生长质量较好，减少PN结界面的缺陷，降低漏电流，且能保证深沟槽的垂直形貌和面内形貌的均匀性，还可降低生产成本。The technical problem to be solved by the present invention is to provide a method for preparing a super junction device by wet etching, which has less damage to the silicon substrate, can ensure better growth quality of the subsequent epitaxial layer, and reduces defects at the PN junction interface. The leakage current is reduced, and the uniformity of the vertical shape and the in-plane shape of the deep trench can be guaranteed, and the production cost can also be reduced.

为解决上述技术问题，本发明提供一种使用湿法刻蚀制备超级结器件的方法，包括如下步骤：In order to solve the above technical problems, the present invention provides a method for preparing a super junction device using wet etching, comprising the following steps:

步骤一，在硅基板上成长外延层；Step 1, growing an epitaxial layer on a silicon substrate;

步骤二，在硅片的正面和背面同时形成介质膜；Step 2, forming a dielectric film on the front and back of the silicon wafer at the same time;

步骤三，正面用光刻胶定义图形，用干法刻蚀的方法打开介质膜；Step 3, define the pattern with photoresist on the front side, and open the dielectric film by dry etching;

步骤四，去除光刻胶，利用介质膜作为掩膜层，使用湿法各向异性刻蚀形成垂直的深沟槽结构；Step 4, removing the photoresist, using the dielectric film as a mask layer, and using wet anisotropic etching to form a vertical deep trench structure;

步骤五，清洗后在深沟槽内填充成长与步骤一的外延层类型相反的外延层，以形成交替排列的P型和N型的结构；Step 5, after cleaning, filling and growing the epitaxial layer in the deep trench with the type of epitaxial layer opposite to that ofstep 1, so as to form alternately arranged P-type and N-type structures;

步骤六，使用化学机械抛光的方法进行平坦化处理，停在介质膜上；Step 6, use chemical mechanical polishing to planarize and stop on the dielectric film;

步骤七，利用湿法刻蚀去除正反面的介质膜，即可形成P型和N型交替排列的结构；Step 7, using wet etching to remove the dielectric film on the front and back sides, to form a P-type and N-type structure alternately arranged;

步骤八，后续工艺采用成熟的纵向双扩散金属氧化物半导体即可制备完整的超级结器件。In step eight, a complete super junction device can be prepared by using a mature vertical double-diffused metal oxide semiconductor in the subsequent process.

在步骤一中，所述外延层的厚度在5-80微米之间。In step one, the thickness of the epitaxial layer is between 5-80 microns.

在步骤二中，所述形成介质膜采用扩散的方法形成热氧化膜作为介质膜，其厚度在1000埃-5000埃之间；或者采用低压化学气相沉积工艺形成氧化膜或氮化膜作为介质膜，氧化膜的厚度在2000埃-10000埃之间，氮化膜的厚度在100埃-500埃之间。In step 2, the formation of the dielectric film adopts a diffusion method to form a thermal oxide film as a dielectric film, and its thickness is between 1000 angstroms and 5000 angstroms; or a low-pressure chemical vapor deposition process is used to form an oxide film or a nitride film as a dielectric film , the thickness of the oxide film is between 2000 angstroms and 10000 angstroms, and the thickness of the nitride film is between 100 angstroms and 500 angstroms.

在步骤一中所述硅基板为晶面取向110的硅基板，则在步骤三中，用光刻胶定义图形，光刻板的设计图形开口与111晶面对齐，该111晶面指晶面取向111，该111晶面是步骤四中深沟槽侧面的晶面。Instep 1, the silicon substrate is a silicon substrate with a crystal plane orientation of 110, then instep 3, a photoresist is used to define the pattern, and the design pattern opening of the photolithographic plate is aligned with the 111 crystal plane, and the 111 crystal plane refers to the crystal plane The orientation is 111, and the 111 crystal plane is the crystal plane on the side of the deep trench in step 4.

在步骤四中，所述去除光刻胶采用灰化或者硫酸双氧水混合物来去除光刻胶。In step 4, the photoresist is removed by ashing or sulfuric acid hydrogen peroxide mixture to remove the photoresist.

在步骤四中，背面的介质膜起到保护背面单晶硅的作用，正面形成垂直的深沟槽结构，该深沟槽的深度为5-50微米；湿法药液采用氢氧化钾、四甲基氢氧铵或邻苯二酚乙二胺的碱性溶液，与去离子水的重量百分比为1%-50%；或者湿法药液使用上述碱性溶液与异丙醇的混合药液，异丙醇与碱性溶液的体积百分比比例为1%-30%。In step 4, the dielectric film on the back side plays the role of protecting the single crystal silicon on the back side, and a vertical deep groove structure is formed on the front side, and the depth of the deep groove is 5-50 microns; Alkaline solution of methylammonium hydroxide or catechol ethylenediamine, with a weight percentage of 1%-50% of deionized water; or a mixed solution of the above alkaline solution and isopropanol for wet liquid , The volume percentage ratio of isopropanol to alkaline solution is 1%-30%.

如果步骤一中成长的外延层是P型外延层，那么步骤五中成长的外延层是N型外延层；如果步骤一中成长的外延层是N型外延层，那么步骤五中成长的外延层是P型外延层。If the epitaxial layer grown instep 1 is a P-type epitaxial layer, then the epitaxial layer grown in step 5 is an N-type epitaxial layer; if the epitaxial layer grown instep 1 is an N-type epitaxial layer, then the epitaxial layer grown in step 5 is the P-type epitaxial layer.

在步骤五中，所述清洗采用硫酸双氧水+稀释氢氟酸+氨水双氧水+盐酸双氧水的湿法工艺。In step five, the cleaning adopts a wet process of sulfuric acid hydrogen peroxide + diluted hydrofluoric acid + ammonia hydrogen peroxide + hydrochloric acid hydrogen peroxide.

在步骤七中，如果介质膜是氧化膜，湿法药液使用缓冲氧化膜刻蚀剂或氢氟酸；如果介质膜是氮化膜，湿法药液使用热磷酸。In step seven, if the dielectric film is an oxide film, the wet chemical solution uses a buffered oxide film etchant or hydrofluoric acid; if the dielectric film is a nitride film, the wet chemical solution uses hot phosphoric acid.

在步骤八中，后续工艺包括如下步骤：In step eight, the follow-up process includes the following steps:

A.使用离子注入的方式分别在特定图形部分形成P阱区、N+阱区和P+源区；A. Use ion implantation to form P well region, N+ well region and P+ source region in specific pattern parts respectively;

B.使用扩散方式形成栅氧，再使用低压化学气相沉积法淀积多晶硅，并进行干法刻蚀，在特定图形部分形成多晶硅栅电极；B. Use diffusion to form gate oxide, then use low-pressure chemical vapor deposition to deposit polysilicon, and perform dry etching to form polysilicon gate electrodes in specific pattern parts;

C.使用低压化学气相沉积法、常压化学气相沉积法或等离子增强化学气相沉积法形成层间介质膜，层间介质膜的种类是氧化膜，随后进行干法刻蚀，形成多晶硅和金属电极的层间隔离以及源区和金属电极的接触孔；C. Use low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition to form an interlayer dielectric film. The type of interlayer dielectric film is an oxide film, followed by dry etching to form polysilicon and metal electrodes Interlayer isolation and contact holes for source regions and metal electrodes;

D.在硅片正面采用溅射物理气相沉积法形成正面源金属电极；D. Forming a front source metal electrode on the front side of the silicon wafer by sputtering physical vapor deposition;

E.在硅片背面采用蒸发物理气相沉积法形成背面漏金属电极。E. Forming the back drain metal electrode on the back of the silicon wafer by evaporative physical vapor deposition.

和现有技术相比，本发明具有以下有益效果：本发明利用在单晶硅上由于晶面不同取向的面上湿法刻蚀速率差异形成的各向异性刻蚀，利用湿法刻蚀的方法在N型外延层上开垂直的深沟槽，通常在晶面取向110的硅基板上进行各向异性的湿法刻蚀，可形成垂直的深沟槽，深沟槽侧面的晶面为111，这样做的好处如下：1.湿法刻蚀对硅基板损伤较小，能保证后续的外延层生长质量较好，减少PN结界面的缺陷，降低漏电流；2.湿法刻蚀的生产成本较低；3.湿法刻蚀是由晶面取向控制刻蚀速率的，可保证深沟槽的90度的垂直形貌和面内形貌的均匀性。Compared with the prior art, the present invention has the following beneficial effects: the present invention utilizes the anisotropic etching formed on the surface of single crystal silicon due to the difference in wet etching rate on the surface with different orientations of the crystal plane, and utilizes the wet etching The method is to open a vertical deep trench on the N-type epitaxial layer, and usually perform anisotropic wet etching on a silicon substrate with a crystal plane orientation of 110 to form a vertical deep trench. The crystal plane on the side of the deep trench is 111. The benefits of doing this are as follows: 1. Wet etching has less damage to the silicon substrate, which can ensure better quality of subsequent epitaxial layer growth, reduce defects at the PN junction interface, and reduce leakage current; 2. Wet etching The production cost is low; 3. The etching rate is controlled by the orientation of the crystal plane in wet etching, which can ensure the 90-degree vertical morphology of the deep trench and the uniformity of the in-plane morphology.

附图说明Description of drawings

图1是本发明方法的流程示意图；其中，Fig. 1 is a schematic flow sheet of the inventive method; Wherein,

图1A是本发明方法步骤（1）完成后的示意图；Fig. 1A is a schematic diagram after step (1) of the method of the present invention is completed;

图1B是本发明方法步骤（2）完成后的示意图；Fig. 1B is a schematic diagram after step (2) of the method of the present invention is completed;

图1C是本发明方法步骤（3）完成后的示意图；Fig. 1C is a schematic diagram after step (3) of the method of the present invention is completed;

图1D是本发明方法步骤（4）完成后的示意图；Figure 1D is a schematic diagram of the method step (4) of the present invention after completion;

图1E是本发明方法步骤（5）完成后的示意图；Figure 1E is a schematic diagram of the method step (5) of the present invention after completion;

图1F是本发明方法步骤（6）完成后的示意图；Figure 1F is a schematic diagram of the method step (6) of the present invention after completion;

图1G是本发明方法步骤（7）完成后的示意图；Fig. 1G is a schematic diagram after step (7) of the method of the present invention is completed;

图2是采用本发明方法制备的超级结器件的结构示意图。Fig. 2 is a schematic structural view of a super junction device prepared by the method of the present invention.

其中，1.是N型硅基板（110晶面），2是N型外延层，3是介质膜，4是光刻胶，5是P型外延层，6是P阱区，7是N+阱区，8是P+源区，9是层间介质膜，10是背面漏金属电极，11是正面源金属电极，12是多晶硅，13是栅氧。Among them, 1. is the N-type silicon substrate (110 crystal plane), 2 is the N-type epitaxial layer, 3 is the dielectric film, 4 is the photoresist, 5 is the P-type epitaxial layer, 6 is the P well region, and 7 is the N+ well 8 is the P+ source region, 9 is the interlayer dielectric film, 10 is the back drain metal electrode, 11 is the front source metal electrode, 12 is polysilicon, and 13 is gate oxide.

具体实施方式Detailed ways

下面结合附图和实施例对本发明作进一步详细的说明。The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

如图1和图2所示，本发明使用湿法刻蚀制备超级结器件的方法的具体步骤包括如下：As shown in Figures 1 and 2, the specific steps of the method for preparing a super junction device using wet etching in the present invention include the following:

（1）在110晶面（晶面取向110）的N型硅基板1上成长N型外延层2，N型外延层2的厚度在5-80um（微米）之间，见图1A；(1) An N-type epitaxial layer 2 is grown on an N-type silicon substrate 1 with a crystal plane of 110 (crystal plane orientation 110), and the thickness of the N-type epitaxial layer 2 is between 5-80um (micrometers), as shown in Figure 1A;

（2）在硅片的正面和背面同时形成介质膜3，可以使用扩散的方法形成热氧化膜作为介质膜3，其厚度在1000埃-5000埃之间，也可使用LPCVD（低压化学气相沉积工艺）形成氧化膜或氮化膜作为介质膜3，氧化膜的厚度在2000埃-10000埃之间，氮化膜的厚度可以在100埃-500埃之间，见图1B；(2)Dielectric film 3 is formed on the front and back of the silicon wafer at the same time. Diffusion method can be used to form a thermal oxide film asdielectric film 3 with a thickness between 1000 angstroms and 5000 angstroms. LPCVD (low pressure chemical vapor deposition) can also be used process) forming an oxide film or a nitride film as thedielectric film 3, the thickness of the oxide film is between 2000 angstroms and 10000 angstroms, and the thickness of the nitride film can be between 100 angstroms and 500 angstroms, as shown in Figure 1B;

（3）正面用光刻胶4定义图形，光刻板的设计图形开口与111晶面（晶面取向111，见图1C和图1D中深沟槽侧面的晶面）对齐，用干法刻蚀的方法打开介质膜3，见图1C；(3) The photoresist 4 is used to define the pattern on the front side, and the design pattern opening of the photoresist plate is aligned with the 111 crystal plane (crystal plane orientation 111, see the crystal plane on the side of the deep trench in Figure 1C and Figure 1D), and dry etching The method to open thedielectric film 3, see Figure 1C;

（4）去除光刻胶4，可以使用ashing（灰化）或者SPM（硫酸双氧水）混合物来去除光刻胶；利用介质膜3作为掩膜层，使用湿法各向异性刻蚀形成垂直的深沟槽结构，背面的介质膜3起到保护背面单晶硅的作用，正面形成垂直的深沟槽结构（深沟槽的深度可以为5um-50um），湿法药液可使用KOH（氢氧化钾），TMAH（四甲基氢氧铵）或EDP（邻苯二酚乙二胺）等碱性溶液，与去离子水的重量百分比为1%-50%，湿法药液也可以使用上述的碱性溶液与IPA（异丙醇）的混合药液，IPA与碱性溶液的体积百分比比例为1%-30%，见图1D；(4) To remove the photoresist 4, you can use ashing (ashing) or SPM (sulfuric acid hydrogen peroxide) mixture to remove the photoresist; use thedielectric film 3 as a mask layer, and use wet anisotropic etching to form a vertical deep Trench structure, thedielectric film 3 on the back plays the role of protecting the single crystal silicon on the back, and a vertical deep trench structure is formed on the front (the depth of the deep trench can be 5um-50um), and the wet chemical solution can use KOH (hydrogen oxide Potassium), TMAH (tetramethylammonium hydroxide) or EDP (catechol ethylenediamine) and other alkaline solutions, the weight percentage of deionized water is 1%-50%, wet liquid can also use the above The mixed solution of alkaline solution and IPA (isopropanol), the volume percentage ratio of IPA and alkaline solution is 1%-30%, see Figure 1D;

（5）清洗（清洗采用硫酸双氧水+稀释氢氟酸+氨水双氧水+盐酸双氧水的湿法工艺）和P型外延层5在深沟槽内填充成长形成交替排列的P型和N型的结构，见图1E；(5) Cleaning (wet process of sulfuric acid hydrogen peroxide + diluted hydrofluoric acid + ammonia hydrogen peroxide + hydrochloric acid hydrogen peroxide) and P-type epitaxial layer 5 is filled and grown in the deep trench to form alternately arranged P-type and N-type structures, See Figure 1E;

（6）使用化学机械抛光的方法进行平坦化处理，停在介质膜3上，见图1F；(6) Perform planarization by chemical mechanical polishing, and stop on thedielectric film 3, as shown in FIG. 1F;

（7）利用湿法刻蚀去除正反面的介质膜3，即可形成P型和N型交替排列的结构，如果介质膜3是氧化膜，湿法药液可使用BOE（缓冲氧化膜刻蚀剂）或HF（氢氟酸），如果介质膜3是氮化膜，湿法药液可使用热磷酸，见图1G；(7) Use wet etching to remove thedielectric film 3 on the front and back sides to form a P-type and N-type alternately arranged structure. If thedielectric film 3 is an oxide film, the wet chemical solution can use BOE (buffered oxide film etching agent) or HF (hydrofluoric acid), if thedielectric film 3 is a nitride film, hot phosphoric acid can be used for the wet chemical solution, see Figure 1G;

（8）后续工艺可采用成熟的纵向双扩散金属氧化物半导体即可制备完整的超级结器件，见图2。后续工艺的步骤具体如下：(8) The subsequent process can use the mature vertical double-diffused metal oxide semiconductor to prepare a complete super junction device, as shown in Figure 2. The steps of the follow-up process are as follows:

A.使用离子注入的方式分别在特定图形部分形成P阱区6（可采用硼注入），N+阱区7（可采用磷或者砷注入），P+源区8（可采用硼注入）；A. Use ion implantation to form P well region 6 (boron implantation can be used), N+ well region 7 (phosphorus or arsenic implantation can be used), and P+ source region 8 (boron implantation can be used) in specific pattern parts respectively;

B.使用扩散方式形成栅氧13，再使用低压化学气相沉积法淀积多晶硅12，并进行干法刻蚀，在特定图形部分形成多晶硅栅电极；B. Form gate oxide 13 by diffusion, then deposit polysilicon 12 by low-pressure chemical vapor deposition, and perform dry etching to form polysilicon gate electrodes in specific pattern parts;

C.使用低压化学气相沉积法，常压化学气相沉积法或等离子增强化学气相沉积法形成层间介质膜9，层间介质膜9的种类是氧化膜，随后进行干法刻蚀，形成多晶硅和金属电极的层间隔离以及源区和金属电极的接触孔；C. Use low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition to form interlayer dielectric film 9. The type of interlayer dielectric film 9 is an oxide film, followed by dry etching to form polysilicon and Interlayer isolation of metal electrodes and contact holes for source regions and metal electrodes;

D.在硅片正面采用溅射物理气相沉积法形成正面源金属电极11；D. Forming the front source metal electrode 11 on the front side of the silicon wafer by sputtering physical vapor deposition;

E.在硅片背面采用蒸发物理气相沉积法形成背面漏金属电极10。E. Forming the back drain metal electrode 10 on the back of the silicon wafer by evaporative physical vapor deposition.

本发明利用在单晶硅上由于晶面不同取向的面上湿法的各向异性刻蚀，利用湿法刻蚀的方法在N型外延层上开垂直的深沟槽，通常在晶面取向110的硅基板上进行各向异性的湿法刻蚀，可形成垂直的深沟槽，深沟槽侧面的晶面为111，这样做的好处如下：1.湿法刻蚀对硅基板损伤较小，能保证后续的外延层生长质量较好，减少PN结界面的缺陷，降低漏电流；2.湿法刻蚀的生产成本较低；3.湿法刻蚀是由晶面取向控制刻蚀速率的，可保证深沟槽的90度的垂直形貌和面内形貌的均匀性。The present invention utilizes the wet anisotropic etching on the surface of the single crystal silicon due to the different orientations of the crystal planes, and uses the wet etching method to open vertical deep grooves on the N-type epitaxial layer, usually in the crystal plane orientation Anisotropic wet etching on the 110 silicon substrate can form vertical deep grooves, and the crystal plane on the side of the deep groove is 111. The advantages of this are as follows: 1. Wet etching is less damaging to the silicon substrate Small, can ensure better growth quality of the subsequent epitaxial layer, reduce defects at the PN junction interface, and reduce leakage current; 2. The production cost of wet etching is low; 3. Wet etching is controlled by crystal plane orientation The speed can guarantee the 90-degree vertical shape of the deep trench and the uniformity of the in-plane shape.

Claims (9)

1. A method for preparing a super junction device by using wet etching is characterized by comprising the following steps:

growing an epitaxial layer on a silicon substrate;

step two, forming dielectric films on the front side and the back side of the silicon wafer simultaneously;

step three, defining a pattern on the front surface by using photoresist, and opening the dielectric film by using a dry etching method;

removing the photoresist, and forming a vertical deep groove structure by using wet anisotropic etching by using the dielectric film as a mask layer;

step five, filling the deep groove with an epitaxial layer of which the type is opposite to that of the epitaxial layer in the step one after cleaning to form a P-type structure and an N-type structure which are alternately arranged;

step six, using a chemical mechanical polishing method to carry out planarization treatment, and stopping on the dielectric film;

removing the dielectric films on the front side and the back side by wet etching to form a P-type and N-type alternately arranged structure;

step eight, the complete super junction device can be prepared by adopting a mature longitudinal double-diffusion metal oxide semiconductor in the subsequent process, and the subsequent process comprises the following steps:

A. forming a P well region, an N + well region and a P + source region on the specific pattern part respectively by using an ion implantation mode;

B. forming gate oxide by using a diffusion mode, depositing polycrystalline silicon by using a low-pressure chemical vapor deposition method, and performing dry etching to form a polycrystalline silicon gate electrode on a specific pattern part;

C. forming an interlayer dielectric film by using a low-pressure chemical vapor deposition method, a normal-pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method, wherein the interlayer dielectric film is an oxide film, and then performing dry etching to form interlayer isolation of the polycrystalline silicon and the metal electrode and contact holes of the source region and the metal electrode;

D. forming a front source metal electrode on the front surface of the silicon wafer by a sputtering physical vapor deposition method;

E. and forming a back metal leakage electrode on the back of the silicon wafer by adopting an evaporation physical vapor deposition method.

2. The method of fabricating a super junction device using wet etching as claimed in claim 1, wherein in step one, the epitaxial layer has a thickness of between 5-80 μm.

3. The method for manufacturing a super junction device by wet etching according to claim 1, wherein in the second step, the forming of the dielectric film adopts a diffusion method to form a thermal oxide film as the dielectric film, and the thickness of the thermal oxide film is between 1000 angstroms and 5000 angstroms; or forming an oxide film or a nitride film as a dielectric film by adopting a low-pressure chemical vapor deposition process, wherein the thickness of the oxide film is between 2000 and 10000 angstroms, and the thickness of the nitride film is between 100 and 500 angstroms.

4. The method according to claim 1, wherein in the first step, the silicon substrate is a silicon substrate with a crystal plane orientation of 110, and in the third step, the photoresist is used to define the pattern, the opening of the design pattern of the photolithography plate is aligned with a 111 crystal plane, the 111 crystal plane refers to the crystal plane orientation of 111, and the 111 crystal plane is a crystal plane at the side of the deep trench in the fourth step.

5. The method for manufacturing a super junction device using wet etching as claimed in claim 1, wherein in the fourth step, the removing the photoresist uses ashing or a sulfuric acid hydrogen peroxide mixture to remove the photoresist.

6. The method of claim 1, wherein in the fourth step, the dielectric film on the back side plays a role of protecting the single crystal silicon on the back side, and a vertical deep trench structure is formed on the front side, wherein the deep trench has a depth of 5-50 μm; the wet-process liquid medicine adopts alkaline solution of potassium hydroxide, tetramethyl ammonium hydroxide or pyrocatechol ethylene diamine, and the weight percentage of the alkaline solution and deionized water is 1-50 percent; or the wet-process liquid medicine is mixed liquid medicine of the alkaline solution and isopropanol, and the volume percentage ratio of the isopropanol to the alkaline solution is 1-30%.

7. The method of manufacturing a super junction device using wet etching as claimed in claim 1, wherein if the epitaxial layer grown in the first step is a P-type epitaxial layer, the epitaxial layer grown in the fifth step is an N-type epitaxial layer; if the epitaxial layer grown in step one is an N-type epitaxial layer, then the epitaxial layer grown in step five is a P-type epitaxial layer.

8. The method for manufacturing a super junction device by using wet etching as claimed in claim 1, wherein in the fifth step, the cleaning adopts a wet process of sulfuric acid hydrogen peroxide + diluted hydrofluoric acid + ammonia hydrogen peroxide + hydrochloric acid hydrogen peroxide.

9. The method of fabricating a super junction device using wet etching as claimed in claim 1, wherein in the seventh step, if the dielectric film is an oxide film, the wet chemical solution uses a buffered oxide film etchant or hydrofluoric acid; if the dielectric film is a nitride film, hot phosphoric acid is used as the wet chemical.

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