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CN102402633A - A Method of Establishing a Program for Generating Parameterized Device Physical Layout Units - Google Patents

A Method of Establishing a Program for Generating Parameterized Device Physical Layout Units
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CN102402633A
CN102402633ACN2010102850106ACN201010285010ACN102402633ACN 102402633 ACN102402633 ACN 102402633ACN 2010102850106 ACN2010102850106 ACN 2010102850106ACN 201010285010 ACN201010285010 ACN 201010285010ACN 102402633 ACN102402633 ACN 102402633A
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吴玉平
陈岚
叶甜春
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Institute of Microelectronics of CAS
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本发明公开了一种建立参数化器件物理版图单元生成程序的方法,属于集成电路设计自动化技术领域。所述方法包括:利用图形编辑器输入器件的物理图形,在物理图形上标出图形及图形之间的设计规则参数、器件参数与图形的对应关系和选项区域;扫描物理图形,确定基本物理图形之间的位置关系和位置依赖关系;根据基本物理图形之间的位置关系和位置依赖关系,建立各基本物理图形的生成顺序和程序流程,生成程序。本发明可以自动生成参数化器件物理版图单元生成程序。

The present invention discloses a method for establishing a parameterized device physical layout unit generation program, and belongs to the technical field of integrated circuit design automation. The method comprises: using a graphic editor to input a physical graphic of a device, marking the graphic and the design rule parameters between the graphics, the corresponding relationship between the device parameters and the graphics, and the option area on the physical graphic; scanning the physical graphic to determine the positional relationship and positional dependency between the basic physical graphics; according to the positional relationship and positional dependency between the basic physical graphics, establishing the generation order and program flow of each basic physical graphic, and generating a program. The present invention can automatically generate a parameterized device physical layout unit generation program.

Description

A kind of method of setting up parametrization device physics domain unit generator program
Technical field
The present invention relates to the IC design technical field of automation, particularly a kind of method of setting up parametrization device physics domain unit generator program.
Background technology
Device physics domain unit design is the important step of Analogous Integrated Electronic Circuits design.For the design of faster devices physical pattern unit, generally adopt parametrization device physics domain unit generator program.For the consistent same types of devices of physical arrangement; By means of parametrization device physics domain unit generator program; Import the physical pattern unit that concrete device parameters value promptly can generate respective devices automatically; Can avoid the physical layout of the hand-designed device of repeatability like this, thereby improve design efficiency, need set up parametrization device physics domain unit generator program for this reason.
At present, set up parametrization device physics domain unit generator program and mainly contain two kinds of methods: the one, the peopleware analyzes manual written-out program according to the device physics domain to hand-designed, and its shortcoming is an inefficiency, and the code maintenance difficulty; Another kind method is to utilize program that the fundamental figure of forming the device physical layout is carried out scanning analysis; According to analysis result; Interactively adds parameter, and its shortcoming is to support the retractility of device effectively, and the fundamental figure generating algorithm is simply based on coordinate; Support parameterization well, the code of generation are difficult to safeguard and use.Therefore need improve to overcome these shortcomings this existent method.
Summary of the invention
In order to solve that the existing method efficient of setting up device physics domain unit generator program is low, code maintenance is difficult and problem such as support parameterization well; The invention provides a kind of method of setting up parametrization device physics domain unit generator program, said method comprises:
Utilize the physical graph of graphic editor entering apparatus, go out the corresponding relation and the option area of design rule parameter, device parameters and figure between figure and the figure at said physical graph subscript;
Scan said physical graph, confirm position relation and position dependence between the basic physical graph;
According to relation of the position between the said basic physical graph and position dependence, set up the genesis sequence and the program circuit of each basic physical graph, generator program.
Said method also comprises adds the figure coordinate relocatable program, specifically comprises: all basic physical graphs of traversal device physical layout calculate horizontal stroke, the minimum coordinate points of ordinate; The reference origin of said device physics domain is moved to said horizontal stroke, the minimum coordinate points of ordinate.
The said step of confirming that the position between the basic physical graph concerns specifically comprises:
According to the area magnitude relationship of each basic physical graph, confirm the encirclement relation between each basic physical graph;
Said basic physical graph is carried out accessible figure and the analysis of obstacle graphic array is arranged;
Said basic physical graph is carried out left and right sides ordinal relation and ordinal relation analysis up and down.
The said step that said basic physical graph is carried out accessible graphic array analysis specifically comprises:
According between the basic physical graph up and down and/or between left and right apart from consistance, basic physical graph is polymerized to one or several one dimensions or two-dimensional array figure;
According to the extension direction of said one dimension or two-dimensional array figure, confirm the figure figurate number of accessible graphic array;
Set up the spacing of said one dimension or two-dimensional array figure and the relation between design rule parameter and the device parameters.
Said extension direction according to the one-dimensional array figure confirms that the step of the figure figurate number of accessible graphic array is specially: the figure figurate number of one-dimensional array figure extension direction=(spacing between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of extension direction).
The step of the relation between the said spacing of setting up said one-dimensional array figure and design rule parameter and the device parameters is specially: the distance values between the said one-dimensional array figure=(spacing-array pattern between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure the physical dimension * counterparty of this direction to the figure figurate number)/(counterparty to figure figurate number-1).
Said extension direction according to said two-dimensional array figure; The step of confirming the figure figurate number of accessible graphic array is specially: said two-dimensional array figure is in the figure of directions X figurate number=(spacing between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of directions X), and said two-dimensional array figure is in the figure of Y direction figurate number=(spacing between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of Y direction).
The step of the relation between the said spacing of setting up the two-dimensional array figure and design rule parameter and the device parameters is specially: the distance values of directions X between the said two-dimensional array figure=(spacing-array pattern between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure is in the figure of the physical dimension * directions X of directions X figurate number)/(the figure figurate number-1 of directions X), the spacing of Y direction between the said two-dimensional array figure=(spacing-array pattern between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure is in the figure figurate number of the physical dimension * Y direction of Y direction)/(the figure figurate number-1 of Y direction).
The said step that said basic physical graph is carried out left and right sides ordinal relation analysis specifically comprises:
Confirm the alignment thereof of said basic physical graph, said alignment thereof comprises coboundary vertical line alignment, the alignment of central horizontal line, the alignment of lower boundary vertical line and does not have alignment up and down;
With the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure left margin coordinate figure as this array point; Confirm the left and right sides ordinal relation between the array pattern according to the magnitude relationship of X coordinate figure in the left margin coordinate figure; The little array point of X coordinate figure is on a left side, and the big array point of X coordinate figure is on the right side.
The said step that said basic physical graph is carried out up and down ordinal relation analysis specifically comprises:
Confirm the alignment thereof of said basic physical graph, said alignment thereof comprise left margin vertical line alignment, the alignment of center vertical line, the alignment of right margin vertical line and about do not have alignment;
With the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure lower boundary coordinate figure as this array point; Confirm the ordinal relation up and down between the array pattern according to the magnitude relationship of Y coordinate figure in the lower boundary coordinate figure; The little array point of Y coordinate figure is down, and the big array point of Y coordinate figure is last.
The step of the position dependence between said definite basic physical graph specifically comprises:
Encirclement relation according to each basic physical graph is set up the tree-like relation of father and son of stratification;
According to the left and right sides ordinal relation of basic physical graph and up and down ordinal relation set up with the fraternal tree-like relation of layer;
Set up the position dependence between root and the leaf from the bottom of tree derivation;
Set up with the position dependence between the layer leaf figure from same figure of tree derivation.
The step of said creation facilities program (CFP) flow process specifically comprises:
According to said graphic array analysis, the figure of graphic array and array point is generated as a sub-flow process;
Dimension and size according to graphic array in father's flow process are set up loop body, in loop body, calculate and respectively generate required reference position of each array point and input parameter;
Array pattern to generating is shifted according to RP;
Surround relation according to said basic physical graph, make up sub-process and generate besieged figure.
Compared with prior art, the present invention has the following advantages:
The present invention can seek the dependence between proximity relations between the figure, covering relation, the graph position, the ordinal relation that figure generates, the dependence between the dimension of picture etc. automatically according to the device physics layout data; And then generate parametrization device physics domain unit generator program automatically; Need not the user and confirm the above-mentioned relation data by hand, accelerated the exploitation of parametrization device physics domain unit.
Description of drawings
Fig. 1 is the method flow diagram of setting up parametrization device physics domain unit generator program that the embodiment of the invention provides.
Embodiment
In order to understand the present invention in depth, the present invention is elaborated below in conjunction with accompanying drawing and specific embodiment.
Referring to Fig. 1, the embodiment of the invention provides a kind of method of setting up parametrization device physics domain unit generator program, comprises the steps:
Step 101: the physical graph that utilizes the graphic editor entering apparatus;
The physical layout of device is made up of the some basic physical graph that is closely related with device architecture; Each basic physical graph comprises information such as type, coordinate points and process layer, utilizes graphic editor to import the information such as process layer at the type of basic physical graph, coordinate points and basic physical graph place;
Step 102: go out the design rule parameter of figure, corresponding relation and the option area etc. of design rule parameter, device parameters and figure between the figure at the physical graph subscript;
Step 103: scan basic physical graph, confirm the position relation between the basic physical graph;
Position relation between the basic physical graph comprises:
1, figure surrounds relationship analysis
Figure A is surrounded by another figure B on how much fully, and promptly A is in B, and we are referred to as figure A and are subordinated to figure B, and figure surrounds the judgement of relation and can confirm according to the simple plane geometrical calculation;
2, array pattern relationship analysis
Array relation comprise other figures are arranged between the accessible array pattern that do not have other figures between the array point and the array point the obstacle array pattern arranged;
2.1 accessible array pattern analysis
2.1.1 confirming of accessible array pattern: for having the identical basic physical graph of the shape and size parameter that belongs to same process layer that same direct father surrounds; About between the basic physical graph of foundation and/or between left and right apart from consistance, these basic physical graphs are polymerized to one or several one dimensions or two-dimensional array figure; It should be noted that does not have figure at the same level or advanced figure to isolate between the array pattern;
2.1.2 surround concern reconstruct: with the figure in virtual these array patterns of the circumscribed covering of grand plan shape; With the array pattern in this direct father's encirclement of this virtual grand plan shape replacement; Just, surround the virtual grand plan shape of increase one deck between figure and the former array pattern same direct father;
2.1.3 confirm the figure figurate number of accessible array pattern
2.1.3.1 for the one-dimensional array figure, the figure figurate number of array extension direction=(spacing between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of extension direction);
2.1.3.2 for the two-dimensional array figure; In the figure of directions X figurate number=(spacing between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of directions X), in the figure of Y direction figurate number=(spacing between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of Y direction);
2.1.4 set up the spacing of array pattern in the accessible array pattern and the relation between design rule parameter and the device parameters: the spacing between the accessible array pattern should satisfy maximum, minimum or the settled principle of design rule parameter, this depends on the design rule file that concrete technology is corresponding; Under the spacing settled principle, the distance values between the accessible array pattern is exactly the given numerical value of design rule file; In maximum, minimum principle but not under the settled principle; Distance values between the accessible array pattern except that with the design rule relating to parameters; Also relevant with the parameter value of device, this parameter is relevant with the outside figure that the restriction array extends, and seeks immediate figure along the array bearing of trend; Thereby seek out the device parameters of this figure of control, this device parameters is exactly the device parameters of indirect array of controls size;
For the one-dimensional array figure, the distance values between the accessible array pattern is: the distance values between the accessible array pattern=(spacing-array pattern between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure the physical dimension * counterparty of this direction to the figure figurate number)/(counterparty to figure figurate number-1);
To the two-dimensional array figure; Spacing between the accessible array pattern is: the distance values of directions X between the accessible array pattern=(spacing-array pattern between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure is in the figure of the physical dimension * directions X of directions X figurate number)/(the figure figurate number-1 of directions X), the spacing of Y direction between the accessible array pattern=(spacing-array pattern between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure is in the figure figurate number of the physical dimension * Y direction of Y direction)/(the figure figurate number-1 of Y direction);
2.2 the analysis of obstacle array pattern is arranged
There is the analysis of obstacle array pattern after accessible array pattern analysis, to carry out, have other figure obstacles between the array pattern, but the obstacle figure do not done any influence to these fundamental figure forming arrays; There is the dot matrix size of array pattern of obstacle relevant with device parameters;
2.2.1 confirming of obstacle array pattern: for having the identical figure of shape and size parameter that belongs to same process layer that same direct father surrounds; According between the obstacle array pattern up and down and/or between left and right apart from consistance, these obstacle array patterns are polymerized to one or several one dimensions or two-dimensional array figure; It should be noted that has figure at the same level or senior compound virtual pattern to isolate between the obstacle array pattern, constitute the array pattern of obstacle between the many fingers gate figure like MOSFET;
2.2.2 confirming of obstacle array of figure figurate number: for having the identical basic physical graph of the shape and size parameter that belongs to same process layer that same direct father surrounds; About between the basic physical graph of foundation and/or between left and right apart from consistance, these basic physical graphs are polymerized to one or several one dimensions or two-dimensional array figure; It should be noted that has figure at the same level or advanced figure to isolate between the array pattern; According to parameter identification, confirm the size of array with a device parameters or a plurality of device parameters again;
2.2.3 confirming of obstacle figure: the coordinate figure with the minimum boundary rectangle of figure is confirmed the figure between the array point figure; List the figure between the array point figure in the obstacle figure; The obstacle figure can be a fundamental figure; Also can be the array that fundamental figure is formed, can be directly linked to corresponding virtual grand plan shape;
2.2.4 confirm the distance values between the obstacle array pattern: distance values=obstacle figure is in size+2 * obstacle figure of figure spacing direction and the spacing between the array point figure;
2.3 array pattern left and right sides ordinal relation is analyzed
2.3.1 confirm the alignment thereof between the figure of the left and right sides in the array pattern: the alignment of coboundary vertical line, central horizontal line align, the lower boundary vertical line aligns and do not have alignment up and down;
2.3.2 with the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure left margin coordinate figure as this array point; Confirm the left and right sides ordinal relation between the array pattern according to the magnitude relationship of X coordinate figure in the left margin coordinate figure; The little array point of X coordinate figure is on a left side, and the big array point of X coordinate figure is on the right side;
2.4 array pattern ordinal relation analysis up and down
2.4.1 confirm in the array pattern alignment thereof between the figure up and down: the alignment of left margin vertical line, the alignment of center vertical line, the alignment of right margin vertical line and about do not have alignment;
2.4.2 with the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure lower boundary coordinate figure as this array point; Confirm the ordinal relation up and down between the array pattern according to the magnitude relationship of Y coordinate figure in the lower boundary coordinate figure; The little array point of Y coordinate figure is down, and the big array point of Y coordinate figure is last;
2.5 the analysis of the line figure between the array point
With the connected graph is the Analysis of Topological Structure of basis to line; Analyze the size of line figure in conjunction with design rule; Analyze the covering of line, thereby confirm the position reference figure of line figure figure; In conjunction with design rule, the relation between analysis line figure and other figures is to calculate spacing; Confirm the coordinate formula of line figure;
2.6 option pattern analysis
The option figure is controlled by the option parameter of control device physical layout, according to option sign and option parameter, is the option figure of this option parameter with the logotype in the option area;
Step 104: confirm the position dependence between each basic physical graph;
Set up the tree-like relation of father and son of stratification according to the figure relation of surrounding; Set up with a layer fraternal tree-like relation according to the left and right sides ordinal relation of basic physical graph and ordinal relation up and down; Set up the position dependence between root and the leaf from the bottom of tree derivation; Set up with the position dependence between the layer leaf figure from same of tree derivation figure, so as with one with the position of layer leaf figure as a reference, other move to the relative position place of regulation with layer leaf figure and inner body thereof;
Step 105: the genesis sequence of setting up each basic physical graph;
Set up the genesis sequence of basic physical graph according to relation, upper and lower relation, reference relation etc. about the hierarchical relationship of setting up, same level, its principle is:
1) according to hierarchical relationship: the inner bottom figure generates and surrounds figure prior to direct father;
2) according to reference relation: preferential by its genesis sequence of the figure of reference;
3) according to relation about same level: order generates from left to right;
4) according to the upper and lower relation of same level: order generates from the bottom up;
Step 106: creation facilities program (CFP) flow process;
1, the foundation of flow process stratification relation is surrounded relationship analysis according to array pattern analysis and figure: according to the array pattern analysis, with the figure generation of array pattern and array point as a sub-flow process; Dimension and size according to array pattern in father's flow process are set up loop body, in loop body, calculate and respectively generate required reference position of each array point and input parameter etc., call this sub-process, and then the array pattern that generates is shifted according to RP; Surround relation according to figure, make up sub-process and generate besieged figure;
2, the foundation of flow process relation in the same level
2.1, confirm that the order of program circuit is carried out relation according to the genesis sequence of basic physical graph;
2.2 make up condition judgment and condition execution branch according to option figure and controlled variable thereof, promptly judge nest relation;
2.3 make up the loop blocks flow process with array pattern, carry out the loop nesting relation;
2.4 according to the dependence between the fundamental figure, calculate position coordinates, and generate fundamental figure according to position coordinates with reference to figure;
Step 107: according to the program circuit generator program;
Utilize the order in the existing CASE technical basis flow process to carry out relation, judge that nest relation, loop nesting relation, redirect nest relation etc. are automatically converted to detailed source program code; The language of program can be SKILL, Tcl/tk, Python, C/C++ etc.; The fundamental figure generating function of calling in the source program is derived from the predefine of system;
Step 108: add figure translation program;
The lower left corner with the device housing is that reference origin (0,0) is one of basic demand of parametrization device physics domain, can realize through the figure translation; Specifically comprise: all fundamental figures of traversal device physical layout; Calculate (Xmin, Ymin) with (Xmax, Ymax); To the coordinate point value in the attribute of all fundamental figures (X, Y) change and replace (Xnew=X-Xmin, thus Ynew=Y-Ymin) reference origin is moved to original (Xmin, Ymin) point.
Above-described specific embodiment has carried out further explain to the object of the invention, technical scheme and beneficial effect.Will be appreciated that the above content is merely embodiment of the present invention, is not limited to the present invention.All within essence of the present invention and ultimate principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (12)

Translated fromChinese
1.一种建立参数化器件物理版图单元生成程序的方法,其特征在于,所述方法包括:1. A method for setting up a parameterized device physical layout unit generating program, characterized in that, the method comprises:利用图形编辑器输入器件的物理图形,在所述物理图形上标出图形及图形之间的设计规则参数、器件参数与图形的对应关系和选项区域;Utilize the graphic editor to input the physical graphics of the device, mark the graphics and the design rule parameters between the graphics, the corresponding relationship between the device parameters and the graphics, and the option area on the physical graphics;扫描所述物理图形,确定基本物理图形之间的位置关系和位置依赖关系;Scanning the physical graphics to determine the positional relationship and position dependence between the basic physical graphics;根据所述基本物理图形之间的位置关系和位置依赖关系,建立各基本物理图形的生成顺序和程序流程,生成程序。According to the positional relationship and positional dependence among the basic physical figures, the generation sequence and program flow of each basic physical figure are established, and the program is generated.2.如权利要求1所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述方法还包括添加图形坐标重定位程序,具体包括:遍历器件物理版图的所有基本物理图形,计算得到横、纵坐标最小的坐标点;将所述器件物理版图的参考原点平移到所述横、纵坐标最小的坐标点。2. The method for establishing a parameterized device physical layout unit generation program according to claim 1, wherein the method also includes adding a graphics coordinate relocation program, specifically comprising: traversing all basic physical graphics of the device physical layout, The coordinate point with the smallest horizontal and vertical coordinates is obtained through calculation; the reference origin of the physical layout of the device is translated to the coordinate point with the smallest horizontal and vertical coordinates.3.如权利要求1或2所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述确定基本物理图形之间的位置关系的步骤具体包括:3. The method for establishing a parameterized device physical layout unit generation program as claimed in claim 1 or 2, wherein the step of determining the positional relationship between the basic physical graphics specifically comprises:根据各个基本物理图形的面积大小关系,确定各个基本物理图形之间的包围关系;According to the area size relationship of each basic physical figure, determine the enclosing relationship between each basic physical figure;对所述基本物理图形进行无障碍图形和有障碍图形阵列分析;Performing barrier-free graphics and barrier-free graphics array analysis on the basic physical graphics;对所述基本物理图形进行左右顺序关系和上下顺序关系分析。The left-right sequence relationship and the up-down sequence relationship analysis are performed on the basic physical graphics.4.如权利要求3所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述对所述基本物理图形进行无障碍图形阵列分析的步骤具体包括:4. The method for establishing a parameterized device physical layout unit generation program as claimed in claim 3, wherein the step of carrying out barrier-free graphics array analysis to the basic physical graphics specifically includes:根据基本物理图形之间的上下和/或左右间距一致性,将基本物理图形聚合为一个或若干个一维或二维阵列图形;Aggregate basic physical graphics into one or several one-dimensional or two-dimensional array graphics according to the consistency of up-down and/or left-right spacing between basic physical graphics;根据所述一维或二维阵列图形的延展方向,确定无障碍图形阵列的图形数;Determine the number of graphics in the barrier-free graphics array according to the extension direction of the one-dimensional or two-dimensional array graphics;建立所述一维或二维阵列图形的间距与设计规则参数和器件参数之间的关系。The relationship between the pitch of the one-dimensional or two-dimensional array pattern, design rule parameters and device parameters is established.5.如权利要求4所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述根据一维阵列图形的延展方向,确定无障碍图形阵列的图形数的步骤具体为:所述一维阵列图形延展方向的图形数=(对应延展方向的器件参数-2×阵列图形和外包图形之间的间距)/(阵列图形在延展方向的几何尺寸+设计规则允许的阵列图形最小间距)。5. The method for establishing a program for generating a parameterized device physical layout unit as claimed in claim 4, wherein, according to the extension direction of the one-dimensional array graphics, the step of determining the number of graphics of the barrier-free graphics array is specifically: The number of graphics in the extension direction of the one-dimensional array graphics=(device parameters corresponding to the extension direction-2*the spacing between the array graphics and the outsourcing graphics)/(the geometric size of the array graphics in the extension direction+the minimum spacing of the array graphics allowed by the design rules ).6.如权利要求5所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述建立所述一维阵列图形的间距与设计规则参数和器件参数之间的关系的步骤具体为:所述一维阵列图形之间的间距值=(对应延展方向的器件参数-2×阵列图形和外包图形之间的间距-阵列图形在该方向的几何尺寸×对应方向的图形数)/(对应方向的图形数-1)。6. The method for establishing a parameterized device physical layout unit generation program as claimed in claim 5, wherein the step of establishing the relationship between the spacing of the one-dimensional array graphic and the design rule parameter and the device parameter is specific It is: the spacing value between the one-dimensional array graphics=(device parameter corresponding to the extension direction-2×the spacing between the array graphics and the outsourcing graphics-the geometric size of the array graphics in this direction×the number of graphics in the corresponding direction)/ (Number of graphics corresponding to the direction - 1).7.如权利要求4所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述根据所述二维阵列图形的延展方向,确定无障碍图形阵列的图形数的步骤具体为:所述二维阵列图形在X方向的图形数=(对应X方向的器件参数-2×阵列图形和外包图形之间的间距)/(阵列图形在X方向的几何尺寸+设计规则允许的阵列图形最小间距),所述二维阵列图形在Y方向的图形数=(对应Y方向的器件参数-2×阵列图形和外包图形之间的间距)/(阵列图形在Y方向的几何尺寸+设计规则允许的阵列图形最小间距)。7. The method for establishing a program for generating a parameterized device physical layout unit as claimed in claim 4, wherein the step of determining the number of graphics of the barrier-free graphics array according to the extension direction of the two-dimensional array graphics is specifically: : the number of graphics in the X direction of the two-dimensional array graphics=(the device parameter corresponding to the X direction-2×the spacing between the array graphics and the outsourcing graphics)/(the geometric size of the array graphics in the X direction+the array allowed by the design rules Graphic minimum spacing), the number of graphics in the Y direction of the two-dimensional array graphics=(the device parameter corresponding to the Y direction-2×the spacing between the array graphics and the outsourcing graphics)/(the geometric size of the array graphics in the Y direction+design The minimum spacing of array graphics allowed by the rules).8.如权利要求7所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述建立二维阵列图形的间距与设计规则参数和器件参数之间的关系的步骤具体为:所述二维阵列图形之间X方向的间距值=(对应X方向的器件参数-2×阵列图形和外包图形之间的间距-阵列图形在X方向的几何尺寸×X方向的图形数)/(X方向的图形数-1),所述二维阵列图形之间Y方向的间距=(对应Y方向的器件参数-2×阵列图形和外包图形之间的间距-阵列图形在Y方向的几何尺寸×Y方向的图形数)/(Y方向的图形数-1)。8. the method for setting up parameterized device physical layout unit generating program as claimed in claim 7, is characterized in that, the step of described setting up the spacing of two-dimensional array figure and the relation between design rule parameter and device parameter is specifically: The spacing value in the X direction between the two-dimensional array graphics=(device parameters corresponding to the X direction-2×Spacing between the array graphics and the outsourcing graphics-The geometric size of the array graphics in the X direction×The number of graphics in the X direction)/ (figure number-1 in the X direction), the spacing in the Y direction between the two-dimensional array graphics=(corresponding device parameters in the Y direction-2× spacing between the array graphics and the outsourcing graphics-the geometry of the array graphics in the Y direction Size×number of graphics in the Y direction)/(number of graphics in the Y direction-1).9.如权利要求3所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述对所述基本物理图形进行左右顺序关系分析的步骤具体包括:9. The method for establishing a program for generating a parameterized device physical layout unit as claimed in claim 3, wherein the step of analyzing the left-right sequence relationship of the basic physical graphics specifically includes:确定所述基本物理图形的对齐方式,所述对齐方式包括上边界垂线对齐、中心水平线对齐、下边界垂线对齐和上下无对齐;Determining the alignment of the basic physical graphics, the alignment includes vertical alignment on the upper boundary, horizontal alignment on the center, vertical alignment on the lower boundary, and no alignment above and below;以阵列点图形的最小外接矩形其左下角的点坐标值作为该阵列点的左边界坐标值,根据左边界坐标值中X坐标值的大小关系确定阵列图形之间的左右顺序关系,X坐标值小的阵列点在左,X坐标值大的阵列点在右。Take the point coordinate value of the lower left corner of the smallest circumscribed rectangle of the array point graphics as the left boundary coordinate value of the array point, and determine the left and right order relationship between the array graphics according to the size relationship of the X coordinate value in the left boundary coordinate value, and the X coordinate value Smaller array points are on the left, and array points with larger X coordinate values are on the right.10.如权利要求3所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述对所述基本物理图形进行上下顺序关系分析的步骤具体包括:10. The method for establishing a program for generating a parameterized device physical layout unit as claimed in claim 3, wherein the step of analyzing the upper and lower order relationship of the basic physical graphics specifically comprises:确定所述基本物理图形的对齐方式,所述对齐方式包括左边界垂线对齐、中心垂线对齐、右边界垂线对齐和左右无对齐;Determine the alignment of the basic physical graphics, the alignment includes left border vertical alignment, center vertical alignment, right border vertical alignment and left and right no alignment;以阵列点图形的最小外接矩形其左下角的点坐标值作为该阵列点的下边界坐标值,根据下边界坐标值中Y坐标值的大小关系确定阵列图形之间的上下顺序关系,Y坐标值小的阵列点在下,Y坐标值大的阵列点在上。Take the point coordinate value of the lower left corner of the smallest circumscribed rectangle of the array point graphics as the lower boundary coordinate value of the array point, and determine the upper and lower order relationship between the array graphics according to the size relationship of the Y coordinate value in the lower boundary coordinate value, and the Y coordinate value Smaller array points are at the bottom, and array points with larger Y coordinate values are at the top.11.如权利要求3所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述确定基本物理图形之间的位置依赖关系的步骤具体包括:11. The method for establishing a parameterized device physical layout unit generation program as claimed in claim 3, wherein the step of determining the position dependence between basic physical graphics specifically comprises:根据各个基本物理图形的包围关系建立层次化的父子树形关系;Establish a hierarchical parent-child tree relationship according to the enclosing relationship of each basic physical figure;根据基本物理图形的左右顺序关系和上下顺序关系建立同层兄弟树形关系;According to the left-right sequence relationship and the up-down sequence relationship of the basic physical graphics, establish the sibling tree relationship of the same layer;从树形图的底层建立根和叶子之间的位置依赖关系;Establish position dependencies between roots and leaves from the bottom layer of the dendrogram;从树形图的同根的图形建立同层叶子图形之间的位置依赖关系。The position dependence relationship between the leaf graphs of the same layer is established from the graphs of the same root in the dendrogram.12.如权利要求3所述的建立参数化器件物理版图单元生成程序的方法,其特征在于,所述建立程序流程的步骤具体包括:12. The method for establishing a program for generating a parameterized device physical layout unit as claimed in claim 3, wherein the step of establishing a program flow specifically comprises:根据所述图形阵列分析,将图形阵列和阵列点的图形生成作为一个子流程;According to the graphic array analysis, the graphic generation of the graphic array and array points is regarded as a sub-process;在父流程中根据图形阵列的维数和大小建立循环体,在循环体中计算各生成各阵列点所需的参考位置和输入参数;In the parent process, a loop body is established according to the dimension and size of the graphics array, and the reference positions and input parameters required to generate each array point are calculated in the loop body;对生成的阵列图形依据参考点进行移位;Shift the generated array graphics according to the reference point;根据所述基本物理图形包围关系,构建子流程生成被包围的图形。According to the enclosing relationship of the basic physical graphics, the construction sub-process generates the enclosed graphics.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN104423821A (en)*2013-08-302015-03-18上海博科资讯股份有限公司Four-line aligning mode for dragging picture
CN106156381A (en)*2015-04-022016-11-23台湾积体电路制造股份有限公司The parameter determination method of array of semiconductor devices and device
CN106649894A (en)*2015-10-282017-05-10北京华大九天软件有限公司Method for quickly generating device array in integrated circuit layout
CN106897504A (en)*2017-02-082017-06-27上海华虹宏力半导体制造有限公司The method to form parameterized units is developed to IP modules

Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5097422A (en)*1986-10-101992-03-17Cascade Design Automation CorporationMethod and apparatus for designing integrated circuits
CN1521833A (en)*2002-11-182004-08-18三洋电机株式会社Integrated circuit designing apparatus, designing method and designing program
JP2007334549A (en)*2006-06-142007-12-27Seiko Epson Corp Manufacturing method of integrated circuit device
CN101308375A (en)*2008-07-162008-11-19四川普什宁江机床有限公司Numerical control longitudinal cutting machine tool machining program simulated realization method and its system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5097422A (en)*1986-10-101992-03-17Cascade Design Automation CorporationMethod and apparatus for designing integrated circuits
CN1521833A (en)*2002-11-182004-08-18三洋电机株式会社Integrated circuit designing apparatus, designing method and designing program
JP2007334549A (en)*2006-06-142007-12-27Seiko Epson Corp Manufacturing method of integrated circuit device
CN101308375A (en)*2008-07-162008-11-19四川普什宁江机床有限公司Numerical control longitudinal cutting machine tool machining program simulated realization method and its system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN104423821A (en)*2013-08-302015-03-18上海博科资讯股份有限公司Four-line aligning mode for dragging picture
CN106156381A (en)*2015-04-022016-11-23台湾积体电路制造股份有限公司The parameter determination method of array of semiconductor devices and device
CN106156381B (en)*2015-04-022019-07-05台湾积体电路制造股份有限公司The parameter determination method and device of array of semiconductor devices
CN106649894A (en)*2015-10-282017-05-10北京华大九天软件有限公司Method for quickly generating device array in integrated circuit layout
CN106897504A (en)*2017-02-082017-06-27上海华虹宏力半导体制造有限公司The method to form parameterized units is developed to IP modules

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