Summary of the invention
The technical problem that the present invention will solve provides a kind of silicon Germanium source/drain structure and manufacturing approach thereof, with further raising channel stress and hole mobility, improves transistorized performance.
For solving the problems of the technologies described above, the present invention provides a kind of silicon Germanium source/drain structure, comprising:
Substrate;
Be positioned at the grid structure on the said substrate;
Be formed in the substrate, be positioned at the stepped ramp type silicon Germanium source/drain region of said grid structure both sides; Said stepped ramp type silicon Germanium source/drain region comprises first degree of depth germanium-silicon layer and second degree of depth germanium-silicon layer at least; The degree of depth of said first degree of depth germanium-silicon layer is greater than said second degree of depth germanium-silicon layer; Adjacent said first degree of depth germanium-silicon layer of said second degree of depth germanium-silicon layer, said second degree of depth germanium-silicon layer compared to said first degree of depth germanium-silicon layer more near said grid structure.
Optional, the degree of depth of said first degree of depth germanium-silicon layer is 450~800 dusts.
Optional, the degree of depth of said second degree of depth germanium-silicon layer is 100~250 dusts.
Optional, the transverse width of said second degree of depth germanium-silicon layer is 1nm~30nm.
The present invention also provides a kind of manufacturing approach of silicon Germanium source/drain structure, comprising:
Form grid structure at substrate surface, form insulating gap wall in the both sides of said grid structure;
Said substrate is carried out etching, form source/drain region first depressed part in the both sides of said insulating gap wall;
Said insulating gap wall is carried out etching, its transverse width is reduced, form new insulating gap wall and expose a part of substrate that is positioned at originally under the insulating gap wall;
The said substrate that exposes is carried out etching, formation source/drain region second depressed part, said source/drain region second depressed part is close to said source/drain region first depressed part, and the degree of depth of said source/drain region second depressed part is shallower than said source/drain region first depressed part;
Growth forms stepped ramp type silicon Germanium source/drain region in said source/drain region first depressed part and said source/drain region second depressed part;
Mixed in said stepped ramp type silicon Germanium source/drain region.
Optional, the transverse width of said insulating gap wall is 5nm~60nm.
Optional, the degree of depth of said source/drain region first depressed part is 450~800 dusts.
Optional, the degree of depth of said source/drain region second depressed part is 100~250 dusts.
Optional, the transverse width of said source/drain region second depressed part is 1nm~30nm.
Because germanium-silicon layer can improve the stress of raceway groove more the closer to raceway groove; Therefore in silicon Germanium source/drain structure of the present invention; Make transistorized raceway groove can bear bigger stress and can not reduce the extension junction characteristic through the silicon Germanium source/drain structure that forms the stepped ramp type shape; Therefore can further improve hole mobility, improve transistorized performance.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Silicon Germanium source/drain structure of the present invention and manufacturing approach thereof multiple substitute mode capable of using realizes; Be to explain below through preferred embodiment; Certainly the present invention is not limited to this specific embodiment, and the general replacement that the one of ordinary skilled in the art knew is encompassed in protection scope of the present invention undoubtedly.
Secondly, the present invention utilizes sketch map to describe in detail, and when the embodiment of the invention was detailed, for the ease of explanation, sketch map disobeyed that general ratio is local amplifies, should be with this as to qualification of the present invention.
Please with reference to Fig. 1, Fig. 1 is the cross section structure sketch map of silicon Germanium source/drain structure of the present invention.As shown in Figure 1, silicon Germanium source/drain structure of the present invention comprises:
Substrate 100;
Be positioned at thegrid structure 110 on the saidsubstrate 100;
Be formed in thesubstrate 100; Be positioned at the stepped ramp type silicon Germanium source/drain region 120 of saidgrid structure 110 both sides; Said stepped ramp type silicon Germanium source/drain region 120 comprises first degree of depth germanium-silicon layer 121 and second degree of depth germanium-silicon layer 122 at least; The degree of depth of said first degree of depth germanium-silicon layer 121 is greater than said second degree of depth germanium-silicon layer 122; Said second degree of depth germanium-silicon layer, 121 adjacent said first degree of depth germanium-silicon layers 122, said second degree of depth germanium-silicon layer 122 compared to said first degree of depth germanium-silicon layer 121 more near saidgrid structure 110.
The degree of depth of said first degree of depth germanium-silicon layer 121 is 450~800 dusts, and the degree of depth of said second degree of depth germanium-silicon layer 122 is 100~250 dusts, and horizontal (direction that is parallel to said substrate) width of said second degree of depth germanium-silicon layer 122 is 1nm~30nm.
Please with reference to Fig. 2 a-Fig. 2 e, Fig. 2 a-Fig. 2 e is the manufacturing approach sketch map of preparation a kind of silicon Germanium source/drain structure shown in Figure 1.
At first, shown in Fig. 2 a, insubstrate 100,form isolation structure 101, on saidsubstrate 100,form grid structure 110 again, also forminsulating gap wall 113 in the both sides of saidgrid structure 110.
Wherein, saidsubstrate 100 can be a silicon substrate, and saidisolation structure 101 can be the silica fleet plough groove isolation structure.Saidgrid structure 110 from bottom to top comprises gatedielectric layer 111 andgate electrode 112, and the material of said gatedielectric layer 111 can be a silica, and the material of saidgate electrode 112 can be DOPOS doped polycrystalline silicon, metal, metal silicide or other conductor.Said insulatinggap wall 113 can be insulating material such as silica, the silicon nitride of individual layer, or the insulating material of multilayer.The transverse width of saidinsulating gap wall 113 is thicker slightly compared to the thickness of common insulating gap wall, is 5nm~60nm.
Subsequently, shown in Fig. 2 b, saidsubstrate 100 is carried out etching, form source/drain region firstdepressed part 102 in the both sides of said insulating gap wall 110.The degree of depth of said source/drain region first depressed part is 450~800 dusts.
Then, shown in Fig. 2 c, saidinsulating gap wall 113 is carried out etching, its transverse width that is parallel on the saidsubstrate 100 is reduced, form new insulating gap wall 113 ' and expose a part of substrate that is positioned at originally under the insulating gap wall 113.Said lithographic method can be dry etching or wet etching.
Follow again; Shown in Fig. 2 d; The said substrate that exposes is carried out etching; Both sides at said new insulating gap wall 113 ' form source/drain region seconddepressed part 103; Said source/the drain region of second depressed part, 103 next-door neighbours, said source/drain region firstdepressed part 102, the degree of depth of said source/drain region seconddepressed part 103 are shallower than said source/drain region firstdepressed part 102 and said source/drain region seconddepressed part 103, and firstdepressed part 102 more approaches said new insulating gap wall 113 ' compared to said source/drain region.The transverse width of said source/drain region seconddepressed part 103 is 1nm~30nm, and the degree of depth of said source/drain region second depressed part is 100~250 dusts.
Then, shown in Fig. 2 e, growth forms stepped ramp type silicon Germanium source/drain region 120 in said source/drain region firstdepressed part 102 and said source/drain region second depressed part 103.Said stepped ramp type silicon Germanium source/drain region 120 comprises first degree of depth germanium-silicon layer 121 and second degree of depth germanium-silicon layer 122 at least; The degree of depth of said first degree of depth germanium-silicon layer 121 is greater than said second degree of depth germanium-silicon layer 122; Said second degree of depth germanium-silicon layer, 121 adjacent said first degree of depth germanium-silicon layers 122, said second degree of depth germanium-silicon layer 122 compared to said first degree of depth germanium-silicon layer 121 more near saidgrid structure 110.
Forming said stepped ramp type silicon Germanium source/drain region can adopt chemical gas-phase deposition method to form.
At last, mixed to adjust its electricity and chemical attribute in said stepped ramp type silicon Germanium source/drain region 200.Doping can be used various dopants and adopt various doping techniques to carry out.Can adopt p type impurity such as boron to be mixed in source/drain region 200, to form the PMOS transistor.Those skilled in the art is when knowing that also available other technology is mixed to source/drain region 200.
Because germanium-silicon layer can improve the stress of raceway groove more the closer to raceway groove; Therefore in silicon Germanium source/drain structure of the present invention; Make transistorized raceway groove can bear bigger stress and can not reduce the extension junction characteristic through the silicon Germanium source/drain structure that forms the stepped ramp type shape; Therefore can further improve hole mobility, improve transistorized performance.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.