技术领域technical field
下面的描述涉及一种半导体装置及其制造方法，更具体地讲，涉及一种具有高介电常数的金属-绝缘体-金属(MIM)电容器及其制造方法。The following description relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a metal-insulator-metal (MIM) capacitor having a high dielectric constant and a method of manufacturing the same.
背景技术Background technique
通常，半导体装置需要在高速度操作同时在功能方面需要具有高存储容量。In general, a semiconductor device is required to operate at a high speed while being required to have a high memory capacity in terms of functions.
为此目的，已经开发出制造半导体装置的技术来提高集成的程度、响应速度和可靠性。为了提高半导体装置的充电特性，包括在半导体装置中的诸如电容器之类的组成元件的静电容量值应该是高的。To this end, techniques for manufacturing semiconductor devices have been developed to increase the degree of integration, response speed, and reliability. In order to improve the charging characteristics of a semiconductor device, the capacitance value of constituent elements such as capacitors included in the semiconductor device should be high.
然而，近年来，随着半导体装置变得高度集成，单位单元面积不断减小。因此，半导体装置的单元静电容量也降低，使得难以确保装置操作所需的静电容量。However, in recent years, as semiconductor devices have become highly integrated, unit cell areas have been decreasing. Therefore, the cell electrostatic capacity of the semiconductor device also decreases, making it difficult to secure an electrostatic capacity required for device operation.
通常，通过增大对电极的面积、提高电极之间的介电体的相对介电常数和减小介电体的厚度来增加电容器的静电电容。因此，电容器的结构被多样化同时减小介电体的厚度，以获得合适的静电电容。Generally, the electrostatic capacitance of a capacitor is increased by increasing the area of the counter electrode, increasing the relative permittivity of the dielectric between the electrodes, and reducing the thickness of the dielectric. Therefore, the structure of the capacitor is diversified while reducing the thickness of the dielectric body to obtain a suitable electrostatic capacitance.
另一方面，已经开展了应用具有高介电常数的材料来代替迄今为止所使用的氮化硅介电层来获得合适的静电容量的研究。具有高介电常数的材料包括氧化铪、氧化铝和氧化钽。On the other hand, research has been conducted to obtain a suitable electrostatic capacity by applying a material having a high dielectric constant instead of the silicon nitride dielectric layer used hitherto. Materials with high dielectric constants include hafnium oxide, aluminum oxide, and tantalum oxide.
然而，当将高介电常数(高-k)材料用作MIM电容器的绝缘层时，其后续工艺将由于蚀刻MIM电容器的上电极之后剩余的绝缘层而受到影响。However, when a high dielectric constant (high-k) material is used as the insulating layer of the MIM capacitor, its subsequent process will be affected due to the remaining insulating layer after etching the upper electrode of the MIM capacitor.
此外，由于不充分的光致抗蚀剂(PR)余量、由剩余的高介电常数绝缘层产生的金属聚合物以及在后续通孔蚀刻工艺中通孔内部金属聚合物的残余，导致金属布线的轮廓劣化。由于这样的问题，通孔电阻增大，从而降低了电容器的可靠性。In addition, due to insufficient photoresist (PR) margin, metal-polymer generated by the remaining high-k insulating layer, and metal-polymer residue inside the via hole during the subsequent via etching process, metal The outline of the wiring deteriorates. Due to such a problem, via resistance increases, thereby reducing reliability of the capacitor.
此外，如果增加后续的通孔过蚀刻对象来去除剩余的绝缘层，则发生击穿电压特性劣化。Furthermore, if a subsequent via hole is added to remove the remaining insulating layer through the etching target, breakdown voltage characteristic degradation occurs.
发明内容Contents of the invention
总的方面涉及一种金属-绝缘体-金属(MIM)电容器以及一种被构造为制造MIM电容器的方法，在该MIM电容器中，可靠性提高，对后续工艺的影响被最小化，并且通过将MIM电容器与外部环境隔离防止了由通孔过蚀刻对象引起的击穿电压劣化。General aspects relate to a metal-insulator-metal (MIM) capacitor and a method configured to manufacture the MIM capacitor, in which reliability is improved, influence on subsequent processes is minimized, and by incorporating the MIM Isolation of the capacitor from the external environment prevents degradation of the breakdown voltage caused by vias through etched objects.
为了实现上述目的，根据本发明实施例的一种MIM电容器可以包括：下电极和上电极，形成在基板上；介电层，具有高介电常数并且形成在下电极和上电极之间；第一保护层，围绕上电极的侧表面和上表面；第二保护层，围绕介电层的侧表面和第一保护层的侧表面，其中，介电层的宽度大于上电极的宽度，第一保护层和第二保护层由蚀刻速率不同的材料制成。In order to achieve the above objects, a MIM capacitor according to an embodiment of the present invention may include: a lower electrode and an upper electrode formed on a substrate; a dielectric layer having a high dielectric constant and formed between the lower electrode and the upper electrode; a first The protective layer surrounds the side surface and the upper surface of the upper electrode; the second protective layer surrounds the side surface of the dielectric layer and the side surface of the first protective layer, wherein the width of the dielectric layer is greater than the width of the upper electrode, and the first protective layer layer and the second protective layer are made of materials with different etch rates.
为了实现上述目的，根据本发明实施例的一种制造MIM电容器的方法可以包括：在基板上形成下电极；在下电极上形成介电层；在介电层的区域上形成上电极和硬掩模；在介电层的侧表面、上电极的侧表面和硬掩模的侧表面形成分隔件。In order to achieve the above object, a method of manufacturing a MIM capacitor according to an embodiment of the present invention may include: forming a lower electrode on a substrate; forming a dielectric layer on the lower electrode; forming an upper electrode and a hard mask on a region of the dielectric layer ; forming spacers on side surfaces of the dielectric layer, side surfaces of the upper electrode, and side surfaces of the hard mask.
为了实现上述目的，根据本发明实施例的一种制造MIM电容器的方法可以包括：在基板上形成第一金属层；在第一金属层上顺序地层压介电层、第二金属层和硬掩模绝缘体；将硬掩模绝缘体和第二金属层图案化，以形成硬掩模和上电极；在包括硬掩模、上电极和介电层的整个基板上形成分隔件绝缘体；蚀刻分隔件绝缘体的整个表面，以在硬掩模的侧表面、上电极的侧表面和介电层的侧表面处形成分隔件；在分隔件、硬掩模和第一金属层上形成缓冲绝缘层；将缓冲绝缘层和第一金属层图案化，以形成下电极。In order to achieve the above object, a method of manufacturing a MIM capacitor according to an embodiment of the present invention may include: forming a first metal layer on a substrate; sequentially laminating a dielectric layer, a second metal layer and a hard mask on the first metal layer pattern insulator; pattern hard mask insulator and second metal layer to form hard mask and top electrode; form spacer insulator on entire substrate including hard mask, top electrode and dielectric layer; etch spacer insulator to form spacers at the side surfaces of the hard mask, the side surfaces of the upper electrode, and the side surfaces of the dielectric layer; a buffer insulating layer is formed on the spacers, the hard mask, and the first metal layer; the buffer The insulating layer and the first metal layer are patterned to form a lower electrode.
在一个总的方面，提供了一种半导体装置，该半导体装置包括：下电极，形成在基板上；介电层，包括形成在下电极上的蚀刻的介电区域和照常生长的介电区域；上电极，形成在照常生长的介电区域上；硬掩模，形成在上电极上；分隔件，形成在硬掩模的侧表面和上电极的侧表面处以及蚀刻的介电区域上方；缓冲绝缘层，形成在硬掩模和分隔件上。In one general aspect, there is provided a semiconductor device comprising: a lower electrode formed on a substrate; a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode; An electrode formed on the as-grown dielectric region; a hard mask formed on the upper electrode; a spacer formed at the side surface of the hard mask and the side surface of the upper electrode and over the etched dielectric region; buffer insulation layer, formed on the hard mask and spacers.
所述装置还可提供：介电层包括原子层沉积(ALD)高kHfO2/Al2O3膜堆叠件。The apparatus may further provide that the dielectric layer comprises an atomic layer deposition (ALD) highkHfO2 /Al2O3 film stack.
所述装置还可提供：使用同一掩模将硬掩模和上电极图案化，以使硬掩模和上电极具有相同的形状。The apparatus may further provide that the hard mask and the upper electrode are patterned using the same mask so that the hard mask and the upper electrode have the same shape.
所述装置还可提供：分隔件将硬掩模的侧表面与上电极的侧表面隔离。The apparatus may further provide that the spacer isolates side surfaces of the hard mask from side surfaces of the upper electrode.
所述装置还可提供：照常生长的介电区域将下电极与上电极分开。The device may also provide that an as-grown dielectric region separates the lower electrode from the upper electrode.
所述装置还可提供：下电极的长度大于上电极的长度。The device may also provide that the length of the lower electrode is greater than the length of the upper electrode.
所述装置还可提供：下电极包括TiN/Ti，上电极包括TiN。The device may further provide that the lower electrode comprises TiN/Ti and the upper electrode comprises TiN.
所述装置还可提供：蚀刻的介电区域从照常生长的区域延伸并大约在分隔件的端部终止，分隔件的所述端部形成在分隔件的一侧，所述一侧与分隔件的与硬掩模和上电极的侧表面接触的一侧相对，并且蚀刻的介电区域的厚度小于照常生长的介电区域的厚度。The apparatus may further provide that the etched dielectric region extends from the as-grown region and terminates approximately at the end of the spacer, the end of the spacer being formed on a side of the spacer that is in contact with the side of the spacer The side of the hard mask that is in contact with the side surface of the upper electrode is opposite, and the thickness of the etched dielectric region is smaller than that of the normally grown dielectric region.
所述装置还可提供：分隔件的所述端部被缓冲绝缘层和蚀刻的介电区域限定。The apparatus may further provide that the ends of the spacer are bounded by a buffer insulating layer and an etched dielectric region.
所述装置还可提供形成在照常生长的介电区域和蚀刻的介电区域之间的弯曲的介电区域。The device may also provide a curved dielectric region formed between the as-grown dielectric region and the etched dielectric region.
所述装置还可提供：分隔件形成在弯曲的介电区域上方。The apparatus may further provide that the spacer is formed over the curved dielectric region.
所述装置还可提供：蚀刻的介电区域从弯曲的区域延伸并大约在分隔件的端部终止，分隔件的所述端部形成在分隔件一侧，所述一侧与分隔件的与硬掩模和上电极的侧表面接触的一侧相对；弯曲的介电区域被构造为连接蚀刻的介电区域和照常生长的介电区域；蚀刻的介电区域的厚度小于照常生长的介电区域和弯曲的介电区域的厚度。The apparatus may further provide that the etched dielectric region extends from the curved region and terminates approximately at an end of the spacer formed on a side of the spacer that is connected to the side of the spacer and The side of the hard mask and the side surface contact of the upper electrode is opposite; the curved dielectric region is configured to connect the etched dielectric region and the as-grown dielectric region; the thickness of the etched dielectric region is smaller than the as-grown dielectric region area and the thickness of the curved dielectric area.
所述装置还可提供，缓冲绝缘层包括SiON。The device may further provide that the buffer insulating layer includes SiON.
在另一方面，提供了一种制造半导体装置的方法。所述方法包括以下步骤：在基板上形成第一金属层；在第一金属层上顺序地层压介电层、第二金属层、硬掩模绝缘体；选择性地蚀刻硬掩模绝缘体、第二金属层和介电层，以形成硬掩模、上电极及具有蚀刻的介电区域和照常生长的介电区域的介电层图案；在硬掩模的上表面和侧表面、上电极的侧表面以及介电层图案的蚀刻的介电区域上形成分隔件绝缘体；蚀刻分隔件绝缘体，以在硬掩模的侧表面、上电极的侧表面以及介电层的蚀刻的介电区域上形成分隔件；在分隔件、硬掩模和第一金属层上形成缓冲绝缘层；将缓冲绝缘层和第一金属层图案化，以形成下电极。In another aspect, a method of manufacturing a semiconductor device is provided. The method includes the steps of: forming a first metal layer on a substrate; sequentially laminating a dielectric layer, a second metal layer, a hard mask insulator on the first metal layer; selectively etching the hard mask insulator, the second metal layer and dielectric layer to form a hard mask, upper electrode and dielectric layer pattern with etched dielectric regions and as-used grown dielectric regions; on the upper and side surfaces of the hard mask, the sides of the upper electrode forming spacer insulators on the etched dielectric regions of the surface and dielectric layer pattern; a buffer insulating layer is formed on the spacer, the hard mask, and the first metal layer; and the buffer insulating layer and the first metal layer are patterned to form a lower electrode.
所述方法还可提供，选择性地蚀刻硬掩模绝缘体、第二金属层和介电层的步骤包括蚀刻第二金属层下方的蚀刻的介电区域的一部分。The method may also provide that the step of selectively etching the hard mask insulator, the second metal layer, and the dielectric layer includes etching a portion of the etched dielectric region below the second metal layer.
所述方法还可提供，蚀刻所述一部分包括在照常生长的介电区域和蚀刻的介电区域之间形成弯曲的介电区域。The method may also provide that etching the portion includes forming a curved dielectric region between the as-grown dielectric region and the etched dielectric region.
所述方法还可提供：分隔件的下表面接触蚀刻的介电区域，分隔件的侧表面接触硬掩模和上电极，分隔件的弯曲的表面分别接触缓冲绝缘层和弯曲的介电区域。The method may further provide that a lower surface of the spacer contacts the etched dielectric region, side surfaces of the spacer contact the hard mask and the upper electrode, and curved surfaces of the spacer contact the buffer insulating layer and the curved dielectric region, respectively.
所述方法还可提供：分隔件的下表面接触蚀刻的介电区域，分隔件的侧表面接触硬掩模和上电极。The method may further provide that a lower surface of the spacer contacts the etched dielectric region, and a side surface of the spacer contacts the hard mask and the upper electrode.
所述方法还可提供：蚀刻的介电区域的厚度小于照常生长的介电区域的厚度。The method may also provide that the thickness of the etched dielectric region is less than the thickness of the as-grown dielectric region.
所述方法还可提供，缓冲绝缘层包括SiON。The method may further provide that the buffer insulating layer includes SiON.
总的方面可提供一种与外部环境隔离开并免于各种缺陷的MIM电容器，从而确保良好的漏电流特性。The general aspect can provide a MIM capacitor isolated from the external environment and free from various defects, thereby ensuring good leakage current characteristics.
此外，总的方面可提供，沉积在金属层上的上部分上的SiON在蚀刻过程中对蚀刻对象进行缓冲，从而防止MIM电容器的击穿电压特性劣化。In addition, the general aspect may provide that SiON deposited on the upper portion on the metal layer buffers an etching target during etching, thereby preventing degradation of breakdown voltage characteristics of the MIM capacitor.
结果，当使用根据总的方面制造的MIM电容器的工艺时，可以在诸如击穿电压、缺陷密度等可靠性方面具有优异的特性。As a result, when the process of manufacturing the MIM capacitor according to the general aspect is used, it can have excellent characteristics in terms of reliability such as breakdown voltage, defect density, and the like.
其他特征和方面可从下面的详细描述、附图和权利要求来看是明显的。Other features and aspects will be apparent from the following detailed description, drawings, and claims.
附图说明Description of drawings
图1A示出了包括互连区域和MIM电容器区域的半导体装置的示例的示意性剖视图。FIG. 1A shows a schematic cross-sectional view of an example of a semiconductor device including an interconnect region and a MIM capacitor region.
图1B示出了图1A的介电层107的附近区域的示例的示意性放大剖视图。FIG. 1B shows a schematic enlarged cross-sectional view of an example of the vicinity of the dielectric layer 107 of FIG. 1A .
图2A至图2R示出了制造MIM电容器的示例的剖视图。2A to 2R show cross-sectional views of examples of fabricating a MIM capacitor.
除非另有描述，否则在整个附图和详细描述中，相同的附图标号将被理解为表示相同的元件、特征和结构。为了清晰、说明和方便起见，会夸大这些元件的相对尺寸和描述。Unless otherwise described, like drawing reference numerals will be understood to refer to like elements, features and structures throughout the drawings and detailed description. The relative size and description of these elements may be exaggerated for clarity, illustration, and convenience.
具体实施方式detailed description
提供下面的详细描述来帮助阅读者获得对在此描述的方法、设备和/或系统的全面理解。因此，本领域普通技术人员应该想到在此描述的系统、设备和/或方法的各种改变、修改和等同物。此外，为了提高清晰和简练程度，会省略对公知功能和构造的描述。The following detailed description is provided to assist the reader in gaining an overall understanding of the methods, devices and/or systems described herein. Accordingly, various changes, modifications, and equivalents of the systems, devices, and/or methods described herein will occur to those of ordinary skill in the art. Also, descriptions of well-known functions and constructions may be omitted for increased clarity and conciseness.
要理解的是，本公开的特征可以以不同的形式来实施，且不应该解释为局限于在这里所提出的示例实施例。相反，提供这些实施例使得本公开将是彻底和完全的，并将把本公开的全部范围传达给本领域技术人员。附图可以不一定符合比例，在一些示例中，可以夸大比例来清晰地示出实施例的特征。当第一层被称作“在”第二层上或“在”基板“上”时，不仅可以指第一层直接形成在第二层或基板上的情形，而是还可以指第三层存在于第一层和第二层之间或者第一层和基板之间的情形。It should be understood that the features of the disclosure may be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the full scope of the disclosure to those skilled in the art. The drawings are not necessarily to scale and in some instances, scale may have been exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it may mean not only the case where the first layer is directly formed on the second layer or the substrate, but also a third layer A case that exists between the first layer and the second layer or between the first layer and the substrate.
在下文中，将参照附图来详细描述具有MIM电容器的半导体装置的结构的示例。Hereinafter, an example of the structure of a semiconductor device having a MIM capacitor will be described in detail with reference to the accompanying drawings.
图1A示出了包括互连区域200和MIM电容器区域300的半导体装置的示例的示意性剖视图。在互连区域200中，下互连层可由下互连金属层103b和下互连覆盖层105b形成。上互连层可设置在下互连层上方，并且在上互连层和下互连层之间设置有金属间绝缘层131。上互连层可由上互连金属层139c和上互连覆盖层141c形成。上互连层可通过金属塞137c电连接到下互连层。FIG. 1A shows a schematic cross-sectional view of an example of a semiconductor device including an interconnect region 200 and a MIM capacitor region 300 . In the interconnection region 200, a lower interconnection layer may be formed of a lower interconnection metal layer 103b and a lower interconnection capping layer 105b. An upper interconnection layer may be disposed over the lower interconnection layer, and an intermetal insulating layer 131 is disposed between the upper interconnection layer and the lower interconnection layer. An upper interconnection layer may be formed of an upper interconnection metal layer 139c and an upper interconnection capping layer 141c. The upper interconnection layer may be electrically connected to the lower interconnection layer through the metal plug 137c.
参照图1A，根据本发明的MIM电容器可以包括：下电极105a，形成在基板101上；介电层107，形成在下电极105a上，具有高介电常数并且包括第一区域和介电层突出部分107a，介电层突出部分107a是从第一区域突出的第二区域；上电极109a，形成在介电层107的第一区域上；分隔件121a，形成在介电层107的侧表面和上电极109a的侧表面处。Referring to FIG. 1A, a MIM capacitor according to the present invention may include: a lower electrode 105a formed on a substrate 101; a dielectric layer 107 formed on the lower electrode 105a having a high dielectric constant and including a first region and a dielectric layer protruding portion 107a, the dielectric layer protruding portion 107a is a second region protruding from the first region; an upper electrode 109a is formed on the first region of the dielectric layer 107; a spacer 121a is formed on the side surface and the upper surface of the dielectric layer 107. at the side surface of the electrode 109a.
这里，介电层107可以包括与上电极109a叠置的第一区域和从所述第一区域延伸并突出的介电层突出部分107a。此时，形成的介电层的水平长度(或宽度)比形成在介电层107上的上电极109a的水平长度(或宽度)长。可以通过形成比上电极更为宽阔的介电层而使上电极与下电极很好地分开，从而有助于抑制漏电流的产生。如果介电层和上电极具有相同的宽度，则上电极和下电极之间的长度短，因此很可能通过沿上下电极的侧表面的电场产生漏电流。相反，如果如上所述介电层的宽度大于上电极的宽度，则能够防止这样的问题。Here, the dielectric layer 107 may include a first region overlapping the upper electrode 109a and a dielectric layer protruding portion 107a extending and protruding from the first region. At this time, the horizontal length (or width) of the formed dielectric layer is longer than the horizontal length (or width) of the upper electrode 109 a formed on the dielectric layer 107 . The upper electrode can be well separated from the lower electrode by forming a wider dielectric layer than the upper electrode, thereby contributing to suppression of leakage current generation. If the dielectric layer and the upper electrode have the same width, the length between the upper electrode and the lower electrode is short, so leakage current is likely to be generated by an electric field along the side surfaces of the upper and lower electrodes. On the contrary, if the width of the dielectric layer is larger than that of the upper electrode as described above, such a problem can be prevented.
下结构形成在基板101上。下结构可以包括焊盘、塞、导电层图案、介电层图案、栅结构、晶体管等。此外，基板101可以包括半导体基板或金属氧化物单晶基板。例如，基板101可以包括硅基板、锗基板、SOI基板、GOI基板、氧化铝单晶基板、氧化钛单晶基板等。The lower structure is formed on the substrate 101 . The lower structure may include pads, plugs, conductive layer patterns, dielectric layer patterns, gate structures, transistors, and the like. In addition, the substrate 101 may include a semiconductor substrate or a metal oxide single crystal substrate. For example, the substrate 101 may include a silicon substrate, a germanium substrate, an SOI substrate, a GOI substrate, an alumina single crystal substrate, a titanium oxide single crystal substrate, and the like.
此外，绝缘结构(未示出)置于基板101和电容器之间。绝缘结构可以具有由氧化物层制成的单层结构。例如，可以利用硼磷硅酸盐玻璃(BPSG)、磷硅酸盐玻璃(PSG)、未掺杂硅酸盐玻璃(USG)、旋涂式玻璃(SOG)、可流动氧化物(FOX)、原硅酸四乙酯(TEOS)、等离子体增强(PE)-TEOS、高密度等离子体-化学气相沉积(HDP-CVD)氧化物等形成绝缘结构(未示出)。另一方面，绝缘结构(未示出)可以具有形成在基板101上的多层结构，所述多层结构包括至少一层氧化物层、至少一层氮化物层和/或至少一层氧氮化物层。这里，可以使用氧化硅来形成氧化物层，可以使用氮化硅来形成氮化物层，可以使用氧氮化硅来形成氧氮化物层。Furthermore, an insulating structure (not shown) is interposed between the substrate 101 and the capacitor. The insulating structure may have a single-layer structure made of an oxide layer. For example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicate glass (USG), spin-on glass (SOG), flowable oxide (FOX), Tetraethyl orthosilicate (TEOS), plasma enhanced (PE)-TEOS, high density plasma-chemical vapor deposition (HDP-CVD) oxide, etc. form an insulating structure (not shown). On the other hand, the insulating structure (not shown) may have a multilayer structure formed on the substrate 101, the multilayer structure including at least one oxide layer, at least one nitride layer and/or at least one layer of oxynitride compound layer. Here, silicon oxide may be used to form the oxide layer, silicon nitride may be used to form the nitride layer, and silicon oxynitride may be used to form the oxynitride layer.
参照图1A，MIM电容器区域300中的MIM电容器400的示例包括金属布线103a、金属布线103a上的下电极105a、介电层107和上电极109a。金属布线103a可由与下互连金属层103b的材料相同的材料制成并按与下互连金属层103b的制造步骤相同的制造步骤形成。下电极105a可由与下互连覆盖层105b的材料相同的材料制成并按与下互连覆盖层105b的制造步骤相同的制造步骤形成。Referring to FIG. 1A, an example of the MIM capacitor 400 in the MIM capacitor region 300 includes a metal wiring 103a, a lower electrode 105a on the metal wiring 103a, a dielectric layer 107, and an upper electrode 109a. The metal wiring 103a may be made of the same material as that of the lower interconnect metal layer 103b and formed in the same manufacturing steps as those of the lower interconnect metal layer 103b. The lower electrode 105a may be made of the same material as that of the lower interconnection covering layer 105b and formed in the same manufacturing steps as those of the lower interconnection covering layer 105b.
金属布线103a可由铝(Al)、铜(Cu)，或者Al和Cu的组合组成。在一个总的方面，金属布线103a可由AlCu组成。可通过使用金属、合金或者导电金属化合物来形成下电极105a。例如，下电极105a可以是选自于由Ru、Pt、TaN、WN、TiN、TiAlN、Co、Cu、Hf、Cu或它们的合金组成的组中的至少一种，或者可以以单个方式或混合方式来使用这些材料中的每种。在一个总的方面，下电极105a可由TiN(顶)/Ti(底)层组成。可能需要Ti层来提高TiN和AlCu之间的粘着。The metal wiring 103a may be composed of aluminum (Al), copper (Cu), or a combination of Al and Cu. In one general aspect, metal wiring 103a may be composed of AlCu. The lower electrode 105a may be formed by using metal, alloy, or conductive metal compound. For example, the lower electrode 105a may be at least one selected from the group consisting of Ru, Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, Cu, or alloys thereof, or may be formed in a single or mixed manner. ways to use each of these materials. In one general aspect, the lower electrode 105a may consist of a TiN(top)/Ti(bottom) layer. A Ti layer may be required to improve adhesion between TiN and AlCu.
可形成介电层107来提高MIM电容器400的电容。在一个总的方面，介电层107可由包括氮化硅(SiN)、氧化钽(Ta2O5)、氧化铪(HfO2)、氧化铝(Al2O3)等在内的任一种绝缘材料组成。在另一总的方面，介电层107可由诸如HfO2/Al2O3层(反之亦然)的堆叠结构形成。在又一总的方面，介电层107可由高kHfO2/Al2O3膜堆叠件的重复结构形成。此外，HfO2层在减少漏电流方面可为有效的。在一个总的方面，可使用原子层沉积(ALD)高kHfO2/Al2O3膜堆叠件的重复结构来表现出4fF/μm2和12fF/μm2之间的电容密度。Dielectric layer 107 may be formed to increase the capacitance of MIM capacitor 400 . In a general aspect, the dielectric layer 107 can be made of any one including silicon nitride (SiN), tantalum oxide (Ta2 O5 ), hafnium oxide (HfO2 ), aluminum oxide (Al2 O3 ), etc. Composition of insulating materials. In another general aspect, the dielectric layer 107 may be formed of a stack structure such as HfO2 /Al2 O3 layers (or vice versa). In yet another general aspect, the dielectric layer 107 can be formed from a repeating structure of high kHfO2 /Al2 O3 film stacks. In addition, theHfO2 layer can be effective in reducing leakage current. In one general aspect, repeating structures of atomic layer deposition (ALD) high kHfO2 /Al2 O3 film stacks can be used to exhibit capacitance densities between 4 fF/μm2 and 12 fF/μm2 .
可使用金属、合金或导电金属化合物来形成上电极109a。例如，上电极109a可以是选自于由Ru、Pt、TaN、WN、TiN、TiAlN、Co、Cu、Hf、Cu或它们的合金组成的组中的至少一种，或者可以以单个方式或混合方式来使用这些材料中的每种。在一个总的方面，上电极109a可由TiN层组成。下电极105a可由TiN(顶)/Ti(底)层组成。因此，上电极109a可包括与下电极105a的材料不同的材料。The upper electrode 109a may be formed using a metal, an alloy, or a conductive metal compound. For example, the upper electrode 109a may be at least one selected from the group consisting of Ru, Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, Cu, or alloys thereof, or may be formed in a single or mixed manner. ways to use each of these materials. In a general aspect, the upper electrode 109a may consist of a TiN layer. The lower electrode 105a may consist of a TiN(top)/Ti(bottom) layer. Accordingly, the upper electrode 109a may include a material different from that of the lower electrode 105a.
如上面提到的，下电极105a的Ti层可起到提高下电极和金属布线103a的AlCu层之间的粘着的粘合层的作用。然而，因为介电层107直接在下电极109a下方，所以上电极109a不需要在TiN层之下使用Ti层。上电极109a和介电层107之间不需要Ti粘合层。As mentioned above, the Ti layer of the lower electrode 105a may function as an adhesive layer improving adhesion between the lower electrode and the AlCu layer of the metal wiring 103a. However, because the dielectric layer 107 is directly under the lower electrode 109a, the upper electrode 109a does not need to use a Ti layer under the TiN layer. A Ti adhesive layer is not required between the upper electrode 109a and the dielectric layer 107 .
此外，可在上电极109a的上表面上形成硬掩模111a，以获得形成在上电极109a的侧面的充足的高度的侧壁分隔件。仅上电极109a的高度可能太小而不能限定上电极109a的侧面的侧壁分隔件。因此，会需要硬掩模111a来使侧壁分隔件形成在硬掩模111a和上电极109a的侧面。In addition, a hard mask 111a may be formed on the upper surface of the upper electrode 109a to obtain a sufficient height of sidewall spacers formed at the sides of the upper electrode 109a. Only the height of the upper electrode 109a may be too small to define sidewall spacers at the sides of the upper electrode 109a. Therefore, the hard mask 111a may be required for the sidewall spacers to be formed on the sides of the hard mask 111a and the upper electrode 109a.
此外，硬掩模111a减少了上电极109a的TiN层的蚀刻过程中聚合物的产生。如果用光致抗蚀剂图案代替硬掩模来作为掩模，则在上电极109a的侧壁上和介电层107的过蚀刻部分的上表面上产生大量的聚合物。由于产生的聚合物包含从上电极109a传输的金属性组分，所以产生的聚合物会表现得像电极。介电层107的过蚀刻部分比介电层107的照常生长的部分(as-grownportion)薄。因此，从金属性聚合物到介电层107的变薄的部分发生漏电流，从而使MIM电容器的可靠性劣化。然而，使用硬掩模111a的蚀刻工艺可阻止在上电极109a的侧壁上产生聚合物，并防止发生上述问题。In addition, the hard mask 111a reduces polymer generation during etching of the TiN layer of the upper electrode 109a. If a photoresist pattern is used as a mask instead of the hard mask, a large amount of polymer is generated on the sidewall of the upper electrode 109a and on the upper surface of the overetched portion of the dielectric layer 107 . Since the resulting polymer contains metallic components transported from the upper electrode 109a, the resulting polymer will behave like an electrode. The overetched portion of the dielectric layer 107 is thinner than the as-grown portion of the dielectric layer 107 . Therefore, leakage current occurs from the metallic polymer to the thinned portion of the dielectric layer 107, thereby deteriorating the reliability of the MIM capacitor. However, the etching process using the hard mask 111a can prevent polymers from being generated on the sidewalls of the upper electrode 109a and prevent the above-mentioned problems from occurring.
可按由氧化物层制成的单层结构来形成硬掩模111a。例如，硬掩模111a可由诸如BPSG、PSG、USG、SOG、FOX、TEOS、PE-TEOS、HDP-CVD氧化物等氧化硅基材料组成，或者由诸如SiN和SiON的氮化硅基材料组成。硬掩模111a可具有包括至少一个氧化物层、至少一个氮化物层和/或至少一个氮氧化物层的多层结构。在一个总的方面，可使用氧化硅来形成氧化物层，可使用氮化硅来形成氮化物层，可使用氮氧化硅来形成氮氧化物层。硬掩模111a的厚度可在大约至的范围内。The hard mask 111a may be formed in a single layer structure made of an oxide layer. For example, the hard mask 111a may be composed of a silicon oxide-based material such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, or a silicon nitride-based material such as SiN and SiON. The hard mask 111a may have a multilayer structure including at least one oxide layer, at least one nitride layer, and/or at least one oxynitride layer. In a general aspect, silicon oxide can be used to form the oxide layer, silicon nitride can be used to form the nitride layer, and silicon oxynitride can be used to form the oxynitride layer. The thickness of the hard mask 111a can be approximately to In the range.
此外，可按由氧化物层制成的单层结构来形成分隔件121a。例如，分隔件121a可由诸如BPSG、PSG、USG、SOG、FOX、TEOS、PE-TEOS、HDP-CVD氧化物等氧化硅基材料组成，或者由诸如SiN和SiON的氮化硅基材料组成。分隔件121a的材料可以是氧化硅而不是氮化硅，这是因为氮化硅比氧化硅会更容易在上电极109a和下电极105a之间引起不期望的边缘电容。Also, the spacer 121a may be formed in a single layer structure made of an oxide layer. For example, the spacer 121a may be composed of a silicon oxide-based material such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, or a silicon nitride-based material such as SiN and SiON. The material of the spacer 121a may be silicon oxide instead of silicon nitride because silicon nitride is more likely than silicon oxide to cause undesired fringe capacitance between the upper electrode 109a and the lower electrode 105a.
缓冲绝缘层123可存在于互连区域200和MIM电容器区域300中。缓冲绝缘层123可覆盖硬掩模111a的上表面、分隔件121a的侧表面、下电极105a的暴露的表面。由于上电极109a被分隔件121a和硬掩模111a围绕，所以缓冲绝缘层123不与上电极109a接触。缓冲绝缘层123可由含有氮原子的氧化硅层(即，氮氧化硅(SiON))组成。因此，在后续的金属图案化过程中，缓冲绝缘层123可执行被构造为增大光刻工艺的余量的抗反射层的作用。The buffer insulating layer 123 may exist in the interconnection region 200 and the MIM capacitor region 300 . The buffer insulating layer 123 may cover the upper surface of the hard mask 111a, the side surfaces of the spacer 121a, and the exposed surface of the lower electrode 105a. Since the upper electrode 109a is surrounded by the spacer 121a and the hard mask 111a, the buffer insulating layer 123 does not contact the upper electrode 109a. The buffer insulating layer 123 may be composed of a silicon oxide layer (ie, silicon oxynitride (SiON)) containing nitrogen atoms. Therefore, in a subsequent metal patterning process, the buffer insulating layer 123 may perform the role of an anti-reflection layer configured to increase a margin of a photolithography process.
此外，缓冲绝缘层123可同时执行被构造为对通孔蚀刻对象进行缓冲的缓冲层的作用。此外，还可将缓冲绝缘层123用作被构造为蚀刻金属布线层103和第一金属层105(在图2A至图2E中示出)的硬掩模。为了蚀刻金属布线层103和第一金属层105，将光致抗蚀剂(PR)用作掩模。然而，PR掩模不足以蚀刻金属布线层103和第一金属层105。在一个总的方面，缓冲绝缘层123的厚度可以在至的范围内。另一方面，可使用有机底部抗反射涂层(BARC)代替无机SiON来形成缓冲绝缘层123。In addition, the buffer insulating layer 123 may simultaneously perform the role of a buffer layer configured to buffer a via etching target. In addition, the buffer insulating layer 123 may also be used as a hard mask configured to etch the metal wiring layer 103 and the first metal layer 105 (shown in FIGS. 2A to 2E ). In order to etch the metal wiring layer 103 and the first metal layer 105, a photoresist (PR) is used as a mask. However, the PR mask is insufficient to etch the metal wiring layer 103 and the first metal layer 105 . In a general aspect, the thickness of the buffer insulating layer 123 can be between to In the range. On the other hand, the buffer insulating layer 123 may be formed using an organic bottom anti-reflective coating (BARC) instead of inorganic SiON.
此外，可在缓冲绝缘层123上方形成金属间绝缘层131。可在金属间绝缘层131上方形成第一焊盘139a和第二焊盘139b以及第一抗反射层141a和第二抗反射层141b。第一焊盘139a可通过第一塞137a电连接到下电极105a，第二焊盘139b可通过第二塞137b电连接到上电极109a。第一塞137a和第二塞137b可包括钨(W)、铜等。在一个总的方面，第一塞137a和第二塞137b可包括钨(W)。此外，可在基板101和金属布线103a之间插入前金属绝缘层(未示出)。In addition, an intermetal insulating layer 131 may be formed over the buffer insulating layer 123 . The first pad 139 a and the second pad 139 b and the first anti-reflection layer 141 a and the second anti-reflection layer 141 b may be formed over the insulating intermetal layer 131 . The first pad 139a may be electrically connected to the lower electrode 105a through the first plug 137a, and the second pad 139b may be electrically connected to the upper electrode 109a through the second plug 137b. The first plug 137a and the second plug 137b may include tungsten (W), copper, or the like. In one general aspect, the first plug 137a and the second plug 137b may include tungsten (W). In addition, a front metal insulating layer (not shown) may be interposed between the substrate 101 and the metal wiring 103a.
图1B示出了图1A的介电层107的附近区域的示例的示意性放大剖视图。可将介电层107划分为三个区域。第一区域可以是蚀刻的介电区域107a，该区域的蚀刻厚度小于照常生长的介电区域107b的照常生长厚度。蚀刻的介电区域107a可以从照常生长的介电区域107b延伸。弯曲的(或阶梯状的)介电区域107c可以位于蚀刻的介电区域107a和照常生长的介电区域107b之间的相邻部分。FIG. 1B shows a schematic enlarged cross-sectional view of an example of the vicinity of the dielectric layer 107 of FIG. 1A . The dielectric layer 107 can be divided into three regions. The first region may be an etched dielectric region 107a having an etched thickness that is less than the as-grown thickness of the as-grown dielectric region 107b. The etched dielectric region 107a may extend from the as-grown dielectric region 107b. The curved (or stepped) dielectric region 107c may be located in an adjacent portion between the etched dielectric region 107a and the as-grown dielectric region 107b.
蚀刻的介电区域107a的厚度可小于照常生长的介电区域107b的厚度，从而增大了电容。也就是说，由于蚀刻的介电区域107a的厚度减小，所以电容增大。因此，由于蚀刻的介电区域107a的存在而可以获得该效果。The thickness of the etched dielectric region 107a may be smaller than the thickness of the as-grown dielectric region 107b, thereby increasing capacitance. That is, since the thickness of the etched dielectric region 107a is reduced, the capacitance is increased. Thus, this effect can be obtained due to the presence of the etched dielectric region 107a.
因为上电极109a和硬掩模111a彼此不同，所以可以实现弯曲的介电区域107c。可在MIM电容器400中形成分隔件121a来减小上电极109a和下电极105a之间的漏电流。分隔件121a可覆盖硬掩模111a、上电极109a的侧表面以及介电层107的暴露的表面。在一个总的方面，介电层107的暴露的表面可包括蚀刻的介电区域107a的表面和弯曲的介电区域107c的表面。Since the upper electrode 109a and the hard mask 111a are different from each other, a curved dielectric region 107c can be realized. The spacer 121a may be formed in the MIM capacitor 400 to reduce leakage current between the upper electrode 109a and the lower electrode 105a. The spacer 121 a may cover the hard mask 111 a, side surfaces of the upper electrode 109 a, and exposed surfaces of the dielectric layer 107 . In one general aspect, the exposed surface of the dielectric layer 107 may include the surface of the etched dielectric region 107a and the surface of the curved dielectric region 107c.
下电极105a的水平长度(或宽度)可大于上电极109a的水平长度(或宽度)。通过形成介电层107，上电极109a可很好地与下电极105a分开，从而有助于抑制漏电流的产生。如果下电极105a和上电极109a具有相同的宽度，很可能通过沿它们的侧表面的电场产生漏电流。相反，如上所述，如果下电极105a的宽度大于上电极109a的宽度，则防止这样的问题是可能的。The horizontal length (or width) of the lower electrode 105a may be greater than the horizontal length (or width) of the upper electrode 109a. By forming the dielectric layer 107, the upper electrode 109a can be well separated from the lower electrode 105a, thereby helping to suppress generation of leakage current. If the lower electrode 105a and the upper electrode 109a have the same width, leakage current is likely to be generated by an electric field along their side surfaces. On the contrary, as described above, if the width of the lower electrode 105a is larger than that of the upper electrode 109a, it is possible to prevent such a problem.
如上所述，使用分隔件121a和硬掩模111a，MIM电容器400可与外部环境分离并免于各种缺陷，从而获得良好的漏电流特性。As described above, using the spacer 121a and the hard mask 111a, the MIM capacitor 400 may be isolated from the external environment and free from various defects, thereby obtaining good leakage current characteristics.
将参照图2A至图2R来描述根据总的方面的制造MIM电容器的方法。A method of manufacturing a MIM capacitor according to general aspects will be described with reference to FIGS. 2A to 2R .
图2A至图2R示出了制造MIM电容器的示例的剖视图。2A to 2R show cross-sectional views of examples of fabricating a MIM capacitor.
尽管未在附图中示出，但是首先可在基板101上形成下结构(未示出)，并将前金属介电层(未示出)沉积在下结构上。尽管未在附图中示出，但是下结构可包括焊盘、导电图案、布线、栅结构、晶体管等。Although not shown in the drawings, a lower structure (not shown) may first be formed on the substrate 101 and a pre-metal dielectric layer (not shown) deposited on the lower structure. Although not shown in the drawings, the lower structure may include pads, conductive patterns, wires, gate structures, transistors, and the like.
然后，如图2A所示，可在前金属绝缘层(未示出)上顺序地沉积金属布线层103和用于下电极的第一金属层105。可根据布线工艺所需的Rs(电阻)值来改变金属布线层103的厚度。金属布线层103可包含铝(Al)、铜等。在一个总的方面，金属布线层103包括AlCu。Then, as shown in FIG. 2A, a metal wiring layer 103 and a first metal layer 105 for a lower electrode may be sequentially deposited on the front metal insulating layer (not shown). The thickness of the metal wiring layer 103 can be changed according to the Rs (resistance) value required for the wiring process. The metal wiring layer 103 may contain aluminum (Al), copper, or the like. In one general aspect, metal wiring layer 103 includes AlCu.
第一金属层105可包括金属、合金或导电金属化合物。例如，第一金属层105可以是选自于由Ti、TaN、WN、TiN、TiAlN或任一种它们的组合组成的组的至少一种。在一个总的方面，第一金属层105包括TiN(顶)/Ti(底)层。The first metal layer 105 may include metal, alloy or conductive metal compound. For example, the first metal layer 105 may be at least one selected from the group consisting of Ti, TaN, WN, TiN, TiAlN, or any combination thereof. In one general aspect, the first metal layer 105 includes a TiN(top)/Ti(bottom) layer.
然后，可以在第一金属层105上沉积介电层107。可使用原子层沉积(ALD)工艺、溅射工艺、脉冲激光沉积工艺、电子束沉积工艺或者化学气相沉积工艺来形成介电层107。在一个总的方面，使用ALD来形成高kHfO2/Al2O3膜堆叠件的重复结构。Then, a dielectric layer 107 may be deposited on the first metal layer 105 . The dielectric layer 107 may be formed using an atomic layer deposition (ALD) process, a sputtering process, a pulsed laser deposition process, an electron beam deposition process, or a chemical vapor deposition process.In one general aspect, ALD is used to form repeating structures of highkHfO2 /Al2O3 film stacks.
如果具有高介电常数值的绝缘材料留在第一金属层105上的通孔区域中，则在形成通孔的蚀刻工艺中会出现问题，这还将在后面进行描述。然而，对于氮化硅(SiN)来说就不会出现问题，这是由于当形成通孔时，即使当其继续留在第一金属层105的侧面上时，氮化硅也易于被蚀刻。If an insulating material having a high dielectric constant value remains in the via region on the first metal layer 105, problems may arise in the etching process for forming the via, which will be described later. However, no problem arises with silicon nitride (SiN), since silicon nitride is easily etched when forming a via hole even when it remains on the side of the first metal layer 105 .
可减小SiN的厚度来增大电容器的电容。如果SiN的厚度减小，则会引起漏电流。因此，如果厚度相同，则优选地使用具有高介电常数值的材料。另一方面，在形成介电层107之后，可以对介电层107额外地执行热处理工艺、臭氧处理工艺、氧处理工艺、等离子体退火工艺等，以提高介电层107的电学特性。The thickness of SiN can be reduced to increase the capacitance of the capacitor. If the thickness of SiN is reduced, leakage current will be caused. Therefore, if the thickness is the same, it is preferable to use a material with a high dielectric constant value. On the other hand, after the dielectric layer 107 is formed, a heat treatment process, an ozone treatment process, an oxygen treatment process, a plasma annealing process, etc. may be additionally performed on the dielectric layer 107 to improve the electrical properties of the dielectric layer 107 .
介电层107可包括第一区域和第二区域。第一区域可以是蚀刻的区域，在该区域中厚度的一部分在后续工艺中被蚀刻。第二区域可以是照常生长的区域，该区域被用作MIM电容器的介电体同时是非蚀刻区域。The dielectric layer 107 may include a first region and a second region. The first region may be an etched region in which a portion of the thickness is etched in a subsequent process. The second area may be an as-grown area that is used as a dielectric for the MIM capacitor while being a non-etched area.
接下来，可在介电层107上沉积将被用作上电极的第二金属层109。可使用金属、合金或者导电金属化合物来形成第二金属层109。例如，第二金属层109可以是选自于由W、Al、Cu、Ti、TaN、WN、TiN、TiAlN或任一种它们的组合组成的组的至少一种。在一个总的方面，第二金属层109包括TiN。Next, a second metal layer 109 to be used as an upper electrode may be deposited on the dielectric layer 107 . The second metal layer 109 may be formed using metal, alloy, or conductive metal compound. For example, the second metal layer 109 may be at least one selected from the group consisting of W, Al, Cu, Ti, TaN, WN, TiN, TiAlN, or any combination thereof. In one general aspect, the second metal layer 109 includes TiN.
然后，可在第二金属层109上沉积硬掩模绝缘体111，以获得将要形成在上电极侧面的充足高度的侧壁分隔件。将被形成的上电极的高度可能太小而不能限定上电极侧面的侧壁分隔件。因此，需要硬掩模绝缘体111来使侧壁分隔件形成在硬掩模和将被形成的上电极的侧面。可以以大约至的范围内的沉积厚度来沉积硬掩模绝缘体111。Then, a hard mask insulator 111 may be deposited on the second metal layer 109 to obtain sidewall spacers of sufficient height to be formed on the sides of the upper electrode. The height of the upper electrode to be formed may be too small to define sidewall spacers flanking the upper electrode. Therefore, the hard mask insulator 111 is required for the sidewall spacers to be formed on the sides of the hard mask and the upper electrode to be formed. can be approximately to The hard mask insulator 111 is deposited with a deposition thickness in a range of .
可以利用化学气相沉积(CVD)工艺、低压化学气相沉积(LPCVD)工艺、等离子体增强化学气相沉积(PECVD)工艺或高密度等离子体化学气相沉积(HDP-CVD)工艺来形成硬掩模绝缘体111。硬掩模绝缘体111可以具有由氧化物层制成的单层结构。例如，硬掩模绝缘体111可以使用诸如BPSG、PSG、USG、SOG、FOX、TEOS、PE-TEOS、HDP-CVD氧化物等氧化硅基材料，或者可以使用诸如SiN和SiON的氮化硅基材料。此外，硬掩模绝缘体111可以具有包括至少一层氧化物层、至少一层氮化物层和/或至少一层氧氮化物层的多层结构。这里，可以使用氧化硅来形成氧化物层，可以使用氮化硅来形成氮化物层，可以使用氧氮化硅来形成氧氮化物层。The hard mask insulator 111 may be formed using a chemical vapor deposition (CVD) process, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a high density plasma chemical vapor deposition (HDP-CVD) process. . The hard mask insulator 111 may have a single layer structure made of an oxide layer. For example, the hard mask insulator 111 can use silicon oxide-based materials such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, etc., or can use silicon nitride-based materials such as SiN and SiON . In addition, the hard mask insulator 111 may have a multilayer structure including at least one oxide layer, at least one nitride layer, and/or at least one oxynitride layer. Here, silicon oxide may be used to form the oxide layer, silicon nitride may be used to form the nitride layer, and silicon oxynitride may be used to form the oxynitride layer.
接下来，如图2B和图2C所示，可在硬掩模绝缘体111上涂覆光致抗蚀剂(PR)层113然后将涂覆的光致抗蚀剂层113图案化来形成用作第一PR掩模113a的第一光致抗蚀剂层图案113a。Next, as shown in FIG. 2B and FIG. 2C, a photoresist (PR) layer 113 can be coated on the hard mask insulator 111 and then the coated photoresist layer 113 can be patterned to form a The first photoresist layer pattern 113a of the first PR mask 113a.
然后，如图2D所示，可使用同一掩模来蚀刻硬掩模绝缘体111和第二金属层109，得到硬掩模111a和上电极109a，可以将硬掩模111a和上电极109a图案化，使得它们具有相同的形状。可在介电层107停止蚀刻，以不将第一金属层105暴露到外面。当蚀刻硬掩模绝缘层体111和第二金属层109时如果第一金属层105被暴露，则产生金属聚合物，从而引起漏电流。Then, as shown in FIG. 2D, the same mask can be used to etch the hard mask insulator 111 and the second metal layer 109 to obtain the hard mask 111a and the upper electrode 109a, which can be patterned, so that they have the same shape. The etching can be stopped at the dielectric layer 107 so as not to expose the first metal layer 105 to the outside. If the first metal layer 105 is exposed when the hard mask insulating layer body 111 and the second metal layer 109 are etched, a metal polymer is generated, thereby causing leakage current.
由于可执行过蚀刻来蚀刻第二金属层109，所以可以对蚀刻的介电区域107a的一部分进行蚀刻，使得蚀刻的介电区域107a中的介电层107的厚度可形成为至少比照常生长的介电区域107b中的介电层107的厚度小。介电层107的被蚀刻后的剩余的介电区域107a的厚度为至在此，蚀刻的介电区域107a中余下的介电层107的厚度可以在大约至的范围内。此外，可以控制蚀刻的介电区域107a中余下的介电层107的厚度以提高工艺余量。当使用第一光致抗蚀剂层图案113a作为掩模层来执行蚀刻工艺时，可在蚀刻硬掩模绝缘体111过程中使用CF4/CHxFy/O2/N2/Ar等气体，可在蚀刻用于MIM电容器的上电极的第二金属层109过程中使用Cl2/BCl3，并且将N2、Ar等用作蚀刻轮廓控制的添加气体。在蚀刻后，可以通过灰化工艺来剥离第一光致抗蚀层图案113a。Since an overetch can be performed to etch the second metal layer 109, a portion of the etched dielectric region 107a can be etched such that the thickness of the dielectric layer 107 in the etched dielectric region 107a can be formed to be at least as thick as grown. The thickness of the dielectric layer 107 in the dielectric region 107b is small. The thickness of the remaining dielectric region 107a of the dielectric layer 107 after being etched is to Here, the thickness of the remaining dielectric layer 107 in the etched dielectric region 107a may be approximately to In the range. In addition, the thickness of the remaining dielectric layer 107 in the etched dielectric region 107a can be controlled to improve the process margin. When the etching process is performed using the first photoresist layer pattern 113a as a mask layer, gas such as CF4 /CHx Fy /O2 /N2 /Ar may be used in the process of etching the hard mask insulator 111. , Cl2 /BCl3 may be used in etching the second metal layer 109 for the upper electrode of the MIM capacitor, and N2 , Ar, etc. may be used as additive gases for etching profile control. After etching, the first photoresist layer pattern 113a may be stripped through an ashing process.
接下来，如图2E所示，可将分隔件绝缘体121沉积为绝缘膜，使得其覆盖硬掩模111a的上表面和侧表面、上电极109a的侧表面以及介电层107的暴露的表面。分隔件绝缘体121可具有大约至的范围内的沉积厚度。分隔件绝缘体121可使用与硬掩模绝缘体111的沉积材料相同的材料，这给分隔件绝缘体121和硬掩模绝缘体111之间遗留下粘着问题。Next, as shown in FIG. 2E , spacer insulator 121 may be deposited as an insulating film such that it covers the upper and side surfaces of hard mask 111 a, the side surfaces of upper electrode 109 a, and the exposed surface of dielectric layer 107 . The separator insulator 121 may have approximately to deposition thickness in the range of . The spacer insulator 121 may use the same material as the deposition material of the hardmask insulator 111 , which leaves an adhesion problem between the spacer insulator 121 and the hardmask insulator 111 .
可以利用化学气相沉积(CVD)工艺、低压化学气相沉积(LPCVD)工艺、等离子体增强化学气相沉积(PECVD)工艺或高密度等离子体化学气相沉积(HDP-CVD)工艺来形成分隔件绝缘体121。分隔件绝缘体121可以具有由氧化物层制成的单层结构。例如，分隔件绝缘体121可以使用诸如BPSG、PSG、USG、SOG、FOX、TEOS、PE-TEOS、HDP-CVD氧化物等氧化硅基材料，或者可以使用诸如SiN和SiON的氮化硅基材料。此外，分隔件绝缘体121可以具有包括至少一层氧化物层、至少一层氮化物层和/或至少一层氧氮化物层的多层结构。这里，可以使用氧化硅来形成氧化物层，可以使用氮化硅来形成氮化物层，可以使用氧氮化硅来形成氧氮化物层。The spacer insulator 121 may be formed using a chemical vapor deposition (CVD) process, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a high density plasma chemical vapor deposition (HDP-CVD) process. The spacer insulator 121 may have a single layer structure made of an oxide layer. For example, the spacer insulator 121 may use a silicon oxide-based material such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, or may use a silicon nitride-based material such as SiN and SiON. In addition, the spacer insulator 121 may have a multilayer structure including at least one oxide layer, at least one nitride layer, and/or at least one oxynitride layer. Here, silicon oxide may be used to form the oxide layer, silicon nitride may be used to form the nitride layer, and silicon oxynitride may be used to form the oxynitride layer.
然后，如图2F所示，可对介电层107和分隔件绝缘体121的暴露的部分回蚀刻直到第一金属层105被暴露。此外，可在硬掩模111a和上电极109a两者的侧表面、蚀刻的介电区域107a的表面以及弯曲的介电区域107c的表面上形成分隔件121a。使用过蚀刻工艺，可将留在通孔区域的介电层107完全去除。如果蚀刻的介电区域107a没有被完全去除，则蚀刻的介电区域107a的剩余部分会在用于形成通孔的后续蚀刻工艺中起到蚀刻停止件的作用，从而阻碍通孔的形成。Then, as shown in FIG. 2F , the exposed portions of the dielectric layer 107 and spacer insulator 121 may be etched back until the first metal layer 105 is exposed. In addition, spacers 121a may be formed on side surfaces of both the hard mask 111a and the upper electrode 109a, the surface of the etched dielectric region 107a, and the surface of the curved dielectric region 107c. Using an over-etch process, the dielectric layer 107 remaining in the via area can be completely removed. If the etched dielectric region 107a is not completely removed, the remaining portion of the etched dielectric region 107a acts as an etch stop in a subsequent etching process used to form the via, thereby preventing the formation of the via.
结果，通过形成分隔件121a的工艺，可将介电层107的水平长度(或宽度)形成为大于形成在介电层107上的上电极109a的水平长度(或宽度)。通过形成比上电极109a更宽的介电层107，可很好地将上电极109a与下电极105a分开，从而有助于抑制漏电流的产生。As a result, the dielectric layer 107 may be formed to have a horizontal length (or width) greater than that of the upper electrode 109a formed on the dielectric layer 107 through the process of forming the spacer 121a. By forming the dielectric layer 107 wider than the upper electrode 109a, the upper electrode 109a can be well separated from the lower electrode 105a, thereby helping to suppress generation of leakage current.
另一方面，硬掩模111a会在蚀刻分隔件绝缘体121的工艺中稍微损失。这可能是由于硬掩模111a的材料与分隔件绝缘体121的材料相同引起的。第一金属层105的暴露的上部分会在蚀刻分隔件绝缘体121的工艺中稍微损失。这可能是由于对第一金属层105的过蚀刻以确保仅保留分隔件绝缘体121的侧表面引起的。On the other hand, the hard mask 111a is slightly lost in the process of etching the spacer insulator 121 . This may be caused by the fact that the material of the hard mask 111 a is the same as that of the spacer insulator 121 . The exposed upper portion of the first metal layer 105 is slightly lost in the process of etching the spacer insulator 121 . This may be caused by overetching of the first metal layer 105 to ensure that only the side surfaces of the spacer insulator 121 remain.
当按照这种方式完成形成分隔件121a的工艺时，MIM电容器400可完全地与外部环境隔离开。结果，分隔件121a可执行保护上电极109a和硬掩模111a的侧表面的作用。蚀刻的介电区域107a可存在于分隔件121a之下，用于下电极105a的第一金属层105可存在于蚀刻的介电区域107a之下。在一个总的方面，存在于分隔件121a之下的蚀刻的介电区域107a的厚度可小于照常生长的介电区域107b的厚度。上电极109a、弯曲的介电区域107c和硬掩模111a可与分隔件121a的侧表面接触。When the process of forming the spacer 121a is completed in this way, the MIM capacitor 400 can be completely isolated from the external environment. As a result, the spacer 121a may perform a role of protecting side surfaces of the upper electrode 109a and the hard mask 111a. An etched dielectric region 107a may exist under the spacer 121a, and the first metal layer 105 for the lower electrode 105a may exist under the etched dielectric region 107a. In one general aspect, the thickness of the etched dielectric region 107a present under the spacer 121a may be less than the thickness of the as-grown dielectric region 107b. The upper electrode 109a, the curved dielectric region 107c, and the hard mask 111a may be in contact with side surfaces of the spacer 121a.
然后，如图2G所示，可将具有诸如SiON的氮化硅基材料的缓冲绝缘层123沉积为抗反射层，使得缓冲绝缘层123覆盖硬掩模111a的上表面、分隔件121a的侧表面、蚀刻的介电区域107a的侧表面以及第一金属层105的暴露的表面。缓冲绝缘层123的蚀刻速率与用在分隔件绝缘体121或硬掩模111a中的材料的蚀刻速率不同。当形成通孔时，缓冲绝缘层123可在缓冲绝缘体上诱导第一次蚀刻停止。Then, as shown in FIG. 2G, a buffer insulating layer 123 having a silicon nitride-based material such as SiON may be deposited as an anti-reflection layer so that the buffer insulating layer 123 covers the upper surface of the hard mask 111a, the side surfaces of the spacers 121a. , the side surfaces of the etched dielectric region 107 a and the exposed surface of the first metal layer 105 . The etch rate of the buffer insulating layer 123 is different from that of the material used in the spacer insulator 121 or the hard mask 111a. The buffer insulating layer 123 may induce a first etch stop on the buffer insulator when the via hole is formed.
在一个总的方面，可通过使用SiON形成缓冲绝缘层123。SiON可执行抗反射层的作用，以在后续的金属图案化过程中增大光刻工艺的余量。此外，缓冲绝缘层123可同时执行用于对通孔蚀刻对象进行缓冲的缓冲层的作用。在一个总的方面，可将缓冲绝缘层123的厚度沉积在大约至的范围内。In one general aspect, the buffer insulating layer 123 may be formed by using SiON. SiON can perform the role of an anti-reflection layer to increase the margin of the photolithography process in the subsequent metal patterning process. In addition, the buffer insulating layer 123 may simultaneously perform the role of a buffer layer for buffering via etching objects. In a general aspect, the thickness of the buffer insulating layer 123 can be deposited at about to In the range.
由于可在基板101的整个表面上沉积缓冲绝缘层123，所以缓冲绝缘层123可与用于被暴露到外部的下电极105a的第一金属层105直接接触。然而，由于上电极109a的侧表面和上表面可分别被分隔件121a和硬掩模111a围绕，所以缓冲绝缘层123不与上电极109a接触。分隔件的下表面接触蚀刻的介电区域。分隔件的侧表面接触硬掩模和上电极。分隔件的弯曲的表面分别接触缓冲绝缘层和弯曲的介电区域。Since the buffer insulating layer 123 may be deposited on the entire surface of the substrate 101, the buffer insulating layer 123 may directly contact the first metal layer 105 for the lower electrode 105a exposed to the outside. However, since the side and upper surfaces of the upper electrode 109a may be surrounded by the spacer 121a and the hard mask 111a, respectively, the buffer insulating layer 123 does not contact the upper electrode 109a. The lower surface of the spacer contacts the etched dielectric region. Side surfaces of the spacer contact the hard mask and the upper electrode. The curved surfaces of the spacer contact the buffer insulating layer and the curved dielectric region, respectively.
此外，可使用SiH4/N2O气体在350℃至420℃的温度范围内沉积用于缓冲绝缘层123的SiON。考虑到光刻工艺的余量，可将n(折射率)的值改变为1.88-22，可将k(消光系数)的值改变为0.30-0.45。可通过控制SiH4/N2O的气体比例来改变n值和k值。n值和k值可随着SiH4/N2O的气体比例减小而增大，从而起到增大N2O的份额的作用。In addition, SiON for the buffer insulating layer 123 may be deposited using SiH4 /N2 O gas within a temperature range of 350° C. to 420° C. Considering the margin of the photolithography process, the value of n (refractive index) can be changed to 1.88-22, and the value of k (extinction coefficient) can be changed to 0.30-0.45. The n and k values can be changed by controlling the SiH4 /N2 O gas ratio. The n value and the k value can be increased with decreasing SiH4 /N2 O gas ratio, thus having the effect of increasing the N2 O fraction.
此外，如果反射率高，则邻近光致抗蚀剂(PR)层会由于漫反射而消散，从而引发难以控制光显影检验(DI)临界尺寸(CD)的困难。可将有机BARC代替SiON用于缓冲绝缘层123。Furthermore, if the reflectivity is high, the adjacent photoresist (PR) layer can be dissipated due to diffuse reflection, causing difficulties in controlling the photodevelopment inspection (DI) critical dimension (CD). An organic BARC may be used for the buffer insulating layer 123 instead of SiON.
此外，当通孔过蚀刻对象小于大约时，可按大约至范围内相对低的厚度来沉积SiON，以确保光刻工艺的余量并将SiON用作用于精细图案化的抗反射层。Also, when vias are etched objects smaller than approximately , press approx. to SiON is deposited at a relatively low thickness in the range of 100 to ensure the margin of the photolithography process and SiON is used as an anti-reflection layer for fine patterning.
然而，当通孔过蚀刻对象大于大约时，可按大约至范围内的厚度来沉积SiON。此外，当蚀刻以形成通孔时，通过使用诸如C4F8、C5F8、C4F6等具有高C/F比值的化学特性的气体来提高氧化层对SiON的蚀刻选择性。SiON执行用于精细图案化的抗反射层的功能并且同时执行对通孔蚀刻对象进行缓冲的缓冲层的作用。However, when vias are etched through objects larger than approximately , press approx. to range in thickness to deposit SiON. In addition, when etching to form via holes, the etch selectivity of the oxide layer to SiON is improved by using a gas with a chemical property such as C4 F8 , C5 F8 , C4 F6 , etc., which has a high C/F ratio. SiON performs the function of an anti-reflection layer for fine patterning and at the same time performs the role of a buffer layer for buffering via-hole etching objects.
此外，还可将缓冲绝缘层123用作用于蚀刻金属布线层103和第一金属层105的硬掩模层。然而，仅PR掩模不能足以蚀刻金属布线层103和第一金属层105。在此，缓冲绝缘层123的厚度可以在大约至的范围内。In addition, the buffer insulating layer 123 can also be used as a hard mask layer for etching the metal wiring layer 103 and the first metal layer 105 . However, only the PR mask is insufficient to etch the metal wiring layer 103 and the first metal layer 105 . Here, the thickness of the buffer insulating layer 123 may be about to In the range.
接下来，如图2H和图2I所示，可以在缓冲绝缘层123上涂覆第二光致抗蚀剂层125，通过使用第二掩模130的光刻工艺对第二光致抗蚀剂层125进行曝光和显影，然后将其图案化来形成第二PR掩模125a。Next, as shown in FIG. 2H and FIG. 2I, a second photoresist layer 125 may be coated on the buffer insulating layer 123, and the second photoresist layer 125 may be coated by a photolithography process using a second mask 130. Layer 125 is exposed and developed, and then patterned to form second PR mask 125a.
然后，如图2J所示，可使用第二PR掩模125a来蚀刻缓冲绝缘层123。此外，可通过以单独或混合的方式使用CHF3、CF4和CH2F2气体来蚀刻缓冲绝缘层123。可以添加诸如N2、O2、Ar等气体来控制蚀刻速率或横截面轮廓。Then, as shown in FIG. 2J, the buffer insulating layer 123 may be etched using the second PR mask 125a. In addition, the buffer insulating layer 123 may be etched by using CHF3 , CF4 , and CH2 F2 gases in a single or mixed manner. Gases such asN2 ,O2 , Ar, etc. can be added to control etch rate or cross-sectional profile.
接下来，可在金属蚀刻设备上放置基板101。然后，利用第二PR掩模125a和缓冲绝缘层123来顺序地蚀刻第一金属层105和金属布线层103，以形成金属布线103a和下互连金属层103b、下电极105a及下互连覆盖层105b，从而完成形成MIM电容器400的工艺。此外，当蚀刻第一金属层105和金属布线层103时，可以以单独的方式使用Cl2或BCl3，并且可以使用诸如N2、C2H4、CH4、CHF3、Ar等气体来实现横截面轮廓。随后，如图2K所示，利用氧气(O2)等离子体来去除第二光致抗蚀剂层图案125a。Next, the substrate 101 may be placed on the metal etching equipment. Then, the first metal layer 105 and the metal wiring layer 103 are sequentially etched using the second PR mask 125a and the buffer insulating layer 123 to form the metal wiring 103a and the lower interconnect metal layer 103b, the lower electrode 105a and the lower interconnect covering layer 105b, thereby completing the process of forming the MIM capacitor 400. In addition, when etching the first metal layer 105 and the metal wiring layer 103, Cl2 or BCl3 may be used in a separate manner, and gases such as N2 , C2 H4 , CH4 , CHF3 , Ar, etc. may be used to Realize the cross-sectional profile. Subsequently, as shown in FIG. 2K, the second photoresist layer pattern 125a is removed using oxygen (O2 ) plasma.
接下来，如图2L所示，为了填充金属布线103a和下互连金属层103b之间的区域，可以沉积金属间绝缘层131。可以执行化学机械平坦化(CMP)工艺来使金属间绝缘层131平坦化。Next, as shown in FIG. 2L , in order to fill a region between the metal wiring 103 a and the lower interconnection metal layer 103 b , an insulating intermetal layer 131 may be deposited. A chemical mechanical planarization (CMP) process may be performed to planarize the insulating intermetal layer 131 .
随后，如图2M所示，利用掩模(未示出)通过光刻工艺对第三光致抗蚀剂层(未示出)进行曝光和显影，然后将第三光致抗蚀剂层图案化，从而形成第三光致抗蚀剂层图案133。Subsequently, as shown in FIG. 2M, a third photoresist layer (not shown) is exposed and developed by a photolithography process using a mask (not shown), and then the third photoresist layer is patterned Thus, the third photoresist layer pattern 133 is formed.
接下来，如图2N所示，可同时形成通孔135a、135b和135c来分别连接上电极109a和下电极105a。通过蚀刻层间绝缘层131和缓冲绝缘层123来形成第一开口135a，通过蚀刻层间绝缘层131、缓冲绝缘层123和硬掩模111a来形成第二开口135b。如果具有高介电常数的蚀刻的介电区域107a在形成用来形成下电极105a的通孔时保留下来，则蚀刻的介电区域107a会起到蚀刻阻挡件的作用，导致开口失效。然而，由于蚀刻的介电区域107a之前被完全去除(例如，在图2F中)，所以可以防止开口失效。Next, as shown in FIG. 2N, via holes 135a, 135b, and 135c may be formed simultaneously to connect the upper electrode 109a and the lower electrode 105a, respectively. The first opening 135 a is formed by etching the insulating interlayer 131 and the buffer insulating layer 123 , and the second opening 135 b is formed by etching the insulating interlayer 131 , the buffer insulating layer 123 and the hard mask 111 a. If the etched dielectric region 107a having a high dielectric constant remains when forming the via hole for forming the lower electrode 105a, the etched dielectric region 107a acts as an etch stopper, causing the opening to fail. However, since the etched dielectric region 107a was completely removed before (eg, in FIG. 2F ), failure of the opening can be prevented.
随后，如图2O所示，在层间绝缘层131上沉积用于填充第一开口135a和第二开口135b的第三金属层137。此时，可以利用溅射工艺、化学气相沉积工艺、原子层沉积(ALD)工艺、电子束沉积工艺、脉冲激光沉积(PLD)工艺等来形成第三金属层137。此外，可以使用钨(W)、铝(Al)、钛、钽、铜、氮化钨、氮化铝、氮化钛、氮化钛铝、氮化钽等来形成第三金属层137。在该实施例中，利用钨(W)来形成第三金属层137。Subsequently, as shown in FIG. 2O , a third metal layer 137 for filling the first opening 135 a and the second opening 135 b is deposited on the interlayer insulating layer 131 . At this time, the third metal layer 137 may be formed using a sputtering process, a chemical vapor deposition process, an atomic layer deposition (ALD) process, an electron beam deposition process, a pulsed laser deposition (PLD) process, or the like. In addition, the third metal layer 137 may be formed using tungsten (W), aluminum (Al), titanium, tantalum, copper, tungsten nitride, aluminum nitride, titanium nitride, titanium aluminum nitride, tantalum nitride, or the like. In this embodiment, the third metal layer 137 is formed using tungsten (W).
接下来，如图2P所示，通过化学机械抛光工艺使第三金属层137平坦化，从而在第一开口135a内形成第一塞137a并且在第二开口135b内形成第二塞137b。此时，第一塞137a连接到下电极105a，第二塞137b连接到上电极109a。Next, as shown in FIG. 2P, the third metal layer 137 is planarized through a chemical mechanical polishing process, thereby forming a first plug 137a in the first opening 135a and a second plug 137b in the second opening 135b. At this time, the first plug 137a is connected to the lower electrode 105a, and the second plug 137b is connected to the upper electrode 109a.
随后，如图2Q所示，在包括第一塞137a和第二塞137b的层间绝缘层131上顺序地沉积第四金属层139和抗反射层141，然后在抗反射层141上涂覆第四光致抗蚀剂层(未示出)。Subsequently, as shown in FIG. 2Q, the fourth metal layer 139 and the anti-reflection layer 141 are sequentially deposited on the interlayer insulating layer 131 including the first plug 137a and the second plug 137b, and then the second layer is coated on the anti-reflection layer 141. Four photoresist layers (not shown).
接下来，虽然没有在附图中示出，但是利用掩模(未示出)通过光刻工艺对第四光致抗蚀剂层(未示出)进行曝光和显影，并将第四光致抗蚀剂层图案化，从而形成第四光致抗蚀剂层图案143。随后，如图2R所示，利用第四光致抗蚀剂层图案143顺序地蚀刻抗反射层141和第四金属层139，以形成通过第一塞137a连接到下电极105a的第一焊盘139a和第一抗反射层图案141a并且形成通过第二塞137b连接到上电极109a的第二焊盘139b和第二抗反射层图案141b，从而完成布线形成工艺。金属塞137a连接到下电极105a、金属塞137b连接到上电极109a、金属塞137c连接到下互连覆盖层105b。在一个总的方面，可将钨(W)用于金属塞。可将第一焊盘139a形成在金属塞137a上方，可将第二焊盘139b形成在金属塞137b上方，并可将上互连金属层139c形成在金属塞137c上方，从而完成布线形成工艺。Next, although not shown in the drawings, a fourth photoresist layer (not shown) is exposed and developed through a photolithography process using a mask (not shown), and the fourth photoresist layer is The resist layer is patterned, thereby forming a fourth photoresist layer pattern 143 . Subsequently, as shown in FIG. 2R, the anti-reflection layer 141 and the fourth metal layer 139 are sequentially etched using the fourth photoresist layer pattern 143 to form a first pad connected to the lower electrode 105a through the first plug 137a. 139a and the first anti-reflection layer pattern 141a and form the second pad 139b and the second anti-reflection layer pattern 141b connected to the upper electrode 109a through the second plug 137b, thereby completing the wiring formation process. The metal plug 137a is connected to the lower electrode 105a, the metal plug 137b is connected to the upper electrode 109a, and the metal plug 137c is connected to the lower interconnection capping layer 105b. In one general aspect, tungsten (W) can be used for the metal plug. The first pad 139a may be formed over the metal plug 137a, the second pad 139b may be formed over the metal plug 137b, and the upper interconnection metal layer 139c may be formed over the metal plug 137c, thereby completing the wiring forming process.
如上所述，MIM电容器可与外部环境隔离并免于各种缺陷，从而确保良好的漏电流特性。此外，在蚀刻过程中，沉积在金属层上部分上的SiON可对蚀刻对象进行缓冲，从而防止MIM电容器的击穿电压特性劣化。As mentioned above, MIM capacitors are isolated from the external environment and free from various defects, thus ensuring good leakage current characteristics. In addition, the SiON deposited on the upper portion of the metal layer buffers the etching target during the etching process, thereby preventing the breakdown voltage characteristics of the MIM capacitor from deteriorating.
此外，下电极的水平长度(或宽度)可大于上电极的水平长度(或宽度)。通过使介电层的水平长度形成得比上电极长，上电极可很好地与下电极分开，从而有助于抑制漏电流的产生。由于实现了制造根据前面提及的总的方面的MIM电容器的方法，所以根据击穿电压、缺陷密度等而具有优异的可靠性是可能的。In addition, the horizontal length (or width) of the lower electrode may be greater than that of the upper electrode. By forming the horizontal length of the dielectric layer longer than that of the upper electrode, the upper electrode can be well separated from the lower electrode, thereby contributing to suppression of leakage current generation. Since the method of manufacturing the MIM capacitor according to the aforementioned general aspect is realized, it is possible to have excellent reliability in terms of breakdown voltage, defect density, and the like.
包括诸如“第一”、“第二”等在内的术语可以被用来描述各种元件，但是这些元件不应该受这些术语的限制。这些术语仅用来将一个元件与另一元件区别开来。例如，在不脱离权利要求的范围的情况下，第一元件可被称为第二元件，相似地，第二元件可被称为第一元件。Terms including terms such as 'first', 'second', etc. may be used to describe various elements, but the elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the claims.
应该注意的是，这里使用的术语为了描述总的方面，而不意图进行限制。还要提及的是，除非另外明确地使用，否则单数的表述也包括复数含义。在本申请中，术语“包含”、“包括”等，意图表达存在所述特征、数字、步骤、操作、元件、部件或它们的组合，但不意图排除存在或附加另一特征、数字、步骤、操作、元件、部件或它们的组合。It should be noted that the terminology used herein is for the purpose of describing general aspects and is not intended to be limiting. It is also to be mentioned that expressions in the singular also include the plural unless explicitly used otherwise. In this application, the terms "comprising", "comprising", etc., are intended to express the existence of said features, numbers, steps, operations, elements, components or their combinations, but are not intended to exclude the existence or addition of another feature, number, or step , operation, element, part or combination thereof.
除非另有定义，否则这里使用的术语(包括技术术语或科学术语)具有与本领域普通技术人员所通常理解的意思相同的意思。在这里使用的术语不仅应基于任何字典中的定义被解释，还应基于在本领域中使用的意思而被解释。此外，除非有明确定义，否则不应过于理想或者正式地解释在这里使用的术语。Unless otherwise defined, the terms (including technical terms or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms used herein should be interpreted not only based on definitions in any dictionary but also based on meanings used in the art. Furthermore, the terms used herein should not be interpreted ideally or formally unless clearly defined.
上面已经描述了一些示例。然而，将理解的是，可以进行各种修改。例如，如果所述技术以不同的顺序执行，和/或如果所描述的系统、体系、装置或电路中的组件按照不同的方式组合和/或被其他组件或它们的等同物代替或补充，则可以获得合适的结果。因此，其他实施方式在权利要求的范围内。Some examples have been described above. However, it will be understood that various modifications may be made. For example, if the techniques described are performed in a different order, and/or if components of the described system, architecture, device, or circuit are combined in a different manner and/or are replaced or supplemented by other components or their equivalents, then Appropriate results can be obtained. Accordingly, other implementations are within the scope of the following claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2010-0069232 | 2010-07-16 | ||
| KR1020100069232AKR101261969B1 (en) | 2010-07-16 | 2010-07-16 | Metal insulator metal capacitor and method for fabricating the same |
| Publication Number | Publication Date |
|---|---|
| CN102339869A CN102339869A (en) | 2012-02-01 |
| CN102339869Btrue CN102339869B (en) | 2016-01-06 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110193949.4AActiveCN102339869B (en) | 2010-07-16 | 2011-07-05 | There is semiconductor device and the manufacture method thereof of MIM capacitor |
| Country | Link |
|---|---|
| KR (1) | KR101261969B1 (en) |
| CN (1) | CN102339869B (en) |
| TW (1) | TWI529861B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751177A (en)* | 2012-07-26 | 2012-10-24 | 上海宏力半导体制造有限公司 | Capacitor structure and preparation method thereof |
| CN103187244B (en)* | 2013-04-03 | 2016-05-11 | 无锡华润上华科技有限公司 | A kind of method of improving the layering of semiconductor crystal wafer electric capacity processing procedure medium |
| CN103346081B (en)* | 2013-06-03 | 2016-05-04 | 上海华力微电子有限公司 | A kind of method of the undercutting of eliminating metal level-insulating barrier-metal level |
| CN103337456B (en)* | 2013-06-27 | 2016-01-27 | 上海华力微电子有限公司 | Improve the method for breakdown voltage of capacitor |
| US9466663B2 (en)* | 2013-10-25 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement having capacitor separated from active region |
| JP6342728B2 (en)* | 2014-06-26 | 2018-06-13 | ラピスセミコンダクタ株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US9793339B2 (en)* | 2015-01-08 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing copper contamination in metal-insulator-metal (MIM) capacitors |
| CN105632897A (en)* | 2016-02-23 | 2016-06-01 | 中航（重庆）微电子有限公司 | MIM (metal-insulator-metal) capacitor and preparation method therefor |
| US10177215B1 (en)* | 2017-10-25 | 2019-01-08 | Texas Instruments Incorporated | Analog capacitor on submicron pitch metal level |
| CN111199953B (en) | 2018-11-16 | 2022-04-08 | 无锡华润上华科技有限公司 | A kind of MIM capacitor and its manufacturing method |
| US10847201B2 (en) | 2019-02-27 | 2020-11-24 | Kepler Computing Inc. | High-density low voltage non-volatile differential memory bit-cell with shared plate line |
| US11476261B2 (en)* | 2019-02-27 | 2022-10-18 | Kepler Computing Inc. | High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor |
| CN110265762B (en)* | 2019-05-10 | 2021-07-16 | 华为技术有限公司 | Electronic device and method of making the same |
| US11659714B1 (en) | 2021-05-07 | 2023-05-23 | Kepler Computing Inc. | Ferroelectric device film stacks with texturing layer, and method of forming such |
| US11527277B1 (en) | 2021-06-04 | 2022-12-13 | Kepler Computing Inc. | High-density low voltage ferroelectric memory bit-cell |
| US12108609B1 (en) | 2022-03-07 | 2024-10-01 | Kepler Computing Inc. | Memory bit-cell with stacked and folded planar capacitors |
| US20230395134A1 (en) | 2022-06-03 | 2023-12-07 | Kepler Computing Inc. | Write disturb mitigation for non-linear polar material based multi-capacitor bit-cell |
| US12347476B1 (en) | 2022-12-27 | 2025-07-01 | Kepler Computing Inc. | Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell |
| US12334127B2 (en) | 2023-01-30 | 2025-06-17 | Kepler Computing Inc. | Non-linear polar material based multi-capacitor high density bit-cell |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6083805A (en)* | 1998-05-20 | 2000-07-04 | Mitel Corporation | Method of forming capacitors in a semiconductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4947849B2 (en)* | 2001-05-30 | 2012-06-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US6576526B2 (en) | 2001-07-09 | 2003-06-10 | Chartered Semiconductor Manufacturing Ltd. | Darc layer for MIM process integration |
| US7582901B2 (en)* | 2004-03-26 | 2009-09-01 | Hitachi, Ltd. | Semiconductor device comprising metal insulator metal (MIM) capacitor |
| JP5038612B2 (en)* | 2005-09-29 | 2012-10-03 | 富士通セミコンダクター株式会社 | Semiconductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6083805A (en)* | 1998-05-20 | 2000-07-04 | Mitel Corporation | Method of forming capacitors in a semiconductor device |
| Publication number | Publication date |
|---|---|
| CN102339869A (en) | 2012-02-01 |
| KR20120008402A (en) | 2012-01-30 |
| TWI529861B (en) | 2016-04-11 |
| TW201227879A (en) | 2012-07-01 |
| KR101261969B1 (en) | 2013-05-08 |
| Publication | Publication Date | Title |
|---|---|---|
| CN102339869B (en) | There is semiconductor device and the manufacture method thereof of MIM capacitor | |
| US11923405B2 (en) | Metal-insulator-metal structure and methods of fabrication thereof | |
| US8445991B2 (en) | Semiconductor device with MIM capacitor and method for manufacturing the same | |
| CN106935544B (en) | Semiconductor device and method for forming the same | |
| CN109560194B (en) | Semiconductor device and method for manufacturing the same | |
| US9196674B2 (en) | Insulation layer to improve capacitor breakdown voltage | |
| CN111211092B (en) | Semiconductor structure and forming method thereof | |
| TWI692889B (en) | Resistive random access memory structure and manufacturing method thereof | |
| KR20230163973A (en) | Semiconductor device and method for manufacturing the same | |
| KR20190031806A (en) | Semiconductor device and method for manufacturing the same | |
| JP2009130207A (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US6483142B1 (en) | Dual damascene structure having capacitors | |
| CN115842021A (en) | Semiconductor device and method of forming the same | |
| TWI624090B (en) | Resistive random access memory device and method for manufacturing the same | |
| CN108573912A (en) | Semiconductor structure and forming method thereof | |
| KR100650192B1 (en) | Semiconductor element and formation method thereof | |
| US7585723B2 (en) | Method for fabricating capacitor | |
| KR100723524B1 (en) | Semiconductor device with reduced insulating film erosion during metal chemical mechanical polishing process and manufacturing method thereof | |
| CN113838834B (en) | Semiconductor device, method for forming semiconductor device, and three-dimensional memory | |
| KR20110024520A (en) | Manufacturing Method of Semiconductor Device | |
| US20150221593A1 (en) | Semiconductor device and method of manufacturing the same | |
| TW202512500A (en) | Semiconductor device and fabricating method thereof | |
| KR20070020753A (en) | Semiconductor device having air gap in interlayer insulating film and method of manufacturing same | |
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| KR20050002361A (en) | A method for forming a metal line of semiconductor device |
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| TR01 | Transfer of patent right | Effective date of registration:20201023 Address after:Han Guozhongqingbeidao Patentee after:Key Foundry Co.,Ltd. Address before:Cheongju Chungbuk Korea Patentee before:Magnachip Semiconductor, Ltd. | |
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| CP03 | Change of name, title or address | Address after:Republic of Korea Patentee after:Aisi Kaifang Semiconductor Co.,Ltd. Country or region after:Republic of Korea Address before:Han Guozhongqingbeidao Patentee before:Key Foundry Co.,Ltd. Country or region before:Republic of Korea | |
| CP03 | Change of name, title or address |