CN102263554B - Phase-locked loop frequency synthesizer structure for improving in-band phase noise performance - Google Patents

Abstract

Translated fromChinese

本发明公开了一种用于提高带内相位噪声性能的锁相环频率综合器结构，该锁相环频率综合器结构由粗调谐回路和精调谐回路两个环路构成，其中，该粗调谐回路用来选择不同的频率控制字，实现环路的频率锁定，该精调谐回路用来实现环路的相位锁定。在锁定状态时，粗调谐回路被关断，仅仅精调谐回路工作。利用本发明，解决了传统结构带内相位噪声受限于分频器的问题，通过引入精调谐回路，在锁定状态时有效减少了分频器的噪声，提高了锁相环频率综合器的带内相位噪声性能。

The invention discloses a phase-locked loop frequency synthesizer structure for improving in-band phase noise performance. The phase-locked loop frequency synthesizer structure is composed of two loops, a coarse tuning loop and a fine tuning loop, wherein the coarse tuning The loop is used to select different frequency control words to realize the frequency locking of the loop, and the fine tuning loop is used to realize the phase locking of the loop. In the locked state, the coarse tuning loop is turned off, and only the fine tuning loop works. The present invention solves the problem that the in-band phase noise of the traditional structure is limited by the frequency divider. By introducing a fine tuning loop, the noise of the frequency divider is effectively reduced in the locked state, and the bandwidth of the phase-locked loop frequency synthesizer is improved. internal phase noise performance.

Description

Be used for improving the phase-locked loop frequency integrator structure of phase noise performance in the band

Technical field

The present invention relates to communication technical field, particularly relate to a kind of for the phase-locked loop frequency integrator structure that improves phase noise performance in the band.

Background technology

Phase-locked loop is a key modules in the transceiver design, and it exports a series of high accuracy frequency signals, for the frequency translation of transceiver provides local oscillation signal.In various phase-locked loop structures, charge pump phase lock loop is because of its low-power consumption, at a high speed, low jitter and cheaply good characteristic be widely used.The charge pump phase lock loop structure as shown in Figure 1, by the phase detection discriminator, charge pump, loop filter, the voltage controlled oscillator that connect successively and be connected the phase detection discriminator input and the voltage controlled oscillator output between frequency divider constitute.Differing and frequency difference between the output of phase detection discriminator comparison frequency divider and the reference signal produces U and D pulse control charge pump; Charge pump provides the charge or discharge electric current to the loop filter with low-pass characteristic; Loop filter is eliminated the HFS in the current impulse, produces control voltage of voltage-controlled oscillator; The output of voltage controlled oscillator is proportional to the radiofrequency signal of control voltage; Frequency divider produces needed frequency dividing ratio.The basic functional principle of phase-locked loop frequency integrator locks onto reference frequency with a word simplified summary, i.e. output from voltage controlled oscillator through frequency divider.

Phase noise is a main performance index of phase-locked loop frequency integrator, is divided into phase noise and the outer phase place noise of band in the band.Be with outer phase place noise mainly relevant with voltage controlled oscillator; Phase noise is relevant with phase detection discriminator with frequency divider, charge pump in the band.Improving the outer phase place noise main path of band is the electric current of optimizing the quality factor of passive device and increasing voltage controlled oscillator, a way that improves phase noise in the band is to reduce the noise of each module, a way in addition is to realize by changing loop structure, the phase-locked loop frequency integrator structure of the no frequency divider that proposes such as some documents, this structure is based on the method for sub-sampling/over-sampling, when the output signal frequency of voltage controlled oscillator and reference signal frequency kept integral multiple to concern, loop reached lock-out state.The problem that the sub-sampling method faces is that the useful signal amplitude of sampler output is too little, and more serious with reference to spuious problem, the problem of oversampler method is that frequency difference is limited, can only be applied in the very little application scenario of frequency difference between reference frequency and the pressuring controlling oscillator frequency.

Transceiver has proposed more and more harsher requirement to the noiseproof feature of phase-locked loop frequency integrator, above-mentioned factor has restricted the phase noise of conventional phase locked loops frequency synthesizer, therefore, need a kind of solution of phase-locked loop frequency integrator, can solve the problem in the above-mentioned correlation technique.

Summary of the invention

(1) technical problem that will solve

In view of this, main purpose of the present invention provides a kind of for the phase-locked loop frequency integrator structure that improves phase noise performance in the band, be subject to the problem of frequency divider with phase noise in the solution traditional structure band, by introducing the fine tuning loop, when lock-out state, effectively reduce the noise of frequency divider, improve the interior phase noise performance of band of phase-locked loop frequency integrator.

(2) technical scheme

For achieving the above object, the invention provides a kind of for the phase-locked loop frequency integrator structure that improves phase noise performance in the band, this phase-locked loop frequency integrator structure is made of two loops in coarse tuning loop and fine tuning loop, wherein, this coarse tuning loop is used for selecting different frequency control words, realize the frequency locking of loop, this fine tuning loop is used for realizing the phase place locking of loop.

In the such scheme, described coarse tuning loop is connected in sequence by coarse tuning phase detection discriminator, first charge pump 1, loop filter, voltage controlled oscillator and frequency divider, the fine tuning loop is connected in sequence by trigger, fine tuning phase detection discriminator, XOR gate, selector, second charge pump 2, loop filter and voltage controlled oscillator, and wherein voltage controlled oscillator and loop filter are that two loops are common.

In the such scheme, described fine tuning phase detection discriminator is used for comparison reference frequency and through differing between the reference frequency of voltage controlled oscillator after synchronously.

In the such scheme, when the leading feedback signal of reference signal, the output signal of selector output fine tuning phase detection discriminator, when reference signal hysteresis feedback signal, the signal behind selector output fine tuning phase detection discriminator output and the reference signal XOR.

In the such scheme, the clock signal of described trigger is the output of voltage controlled oscillator, and triggering signal is reference signal, and trigger is synchronized to reference signal the output of voltage controlled oscillator.

In the such scheme, the input signal of described second charge pump 2 is the output of selector, differing and sign bit of thick phase detection discriminator output, when phase difference signal is high level, the output of selector and sign bit form the input of second charge pump 2 by logical circuit, when phase difference signal is low level, second charge pump 2 be input as low level.

In the such scheme, when the phase place of loop was locked, the coarse tuning loop was turned off, only fine tuning loop works.

In the such scheme, when the dead band that differs by more than the coarse tuning phase detection discriminator was big or small, two loops were worked simultaneously, and the electric current that is injected into loop filter is two charge pump current sums; When differing big or small less than the dead band of coarse tuning phase detection discriminator, the coarse tuning loop automatically shuts down, only fine tuning loop works.

In the such scheme, when frequency is switched, work simultaneously in coarse tuning loop and fine tuning loop, and when approach locking, the coarse tuning loop automatically shuts down, only fine tuning loop works, and the shutoff in coarse tuning loop is that automatic smoothing carries out; When lock-out state, the coarse tuning loop is to the not influence of steady-state behaviour of system.

(3) beneficial effect

From technique scheme as can be seen, the present invention has following characteristics and good result:

Provided by the invention this for the phase-locked loop frequency integrator structure that improves phase noise performance in the band, when lock-out state, the output that comprises the coarse tuning loop of frequency divider is turned off only fine tuning loop works.The switching noise that frequency divider causes is effectively eliminated, and has reduced the in-band noise source of phase-locked loop, thereby helps to improve the interior phase noise performance of band of system.

In addition, the fine tuning loop that the present invention introduces all is operated in low-frequency range except trigger, do not increase a lot of additional power consumptions.

Description of drawings

Fig. 1 is the electrical block diagram of conventional phase locked loops frequency synthesizer;

Fig. 2 is the structural representation of phase-locked loop frequency integrator provided by the invention;

Fig. 3 is structure and the time sequence status figure of coarse tuning phase detection discriminator circuit among Fig. 2;

Fig. 4 is the structural representation of first charge pump circuit among Fig. 2;

Fig. 5 is the locking process simulation waveform of phase-locked loop frequency integrator.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

Fig. 2 shows the structural representation that improves the interior phase noise performance of band and reduce the phase-locked loop frequency integrator of power consumption provided by the invention.Phase-locked loop frequency integrator is made of two loops, i.e. coarse tuning loop and fine tuning loop.The coarse tuning loop is connected in sequence by coarse tuning phase detection discriminator, first charge pump 1, loop filter, voltage controlled oscillator and frequency divider.The fine tuning loop is connected in sequence by trigger, fine tuning phase detection discriminator, XOR gate, selector, second charge pump 2, loop filter and voltage controlled oscillator.Voltage controlled oscillator and loop filter are that two loops are total.The coarse tuning loop is used for realizing the frequency locking; The fine tuning loop is used for realizing the phase place locking.When electrification reset or frequency dividing ratio change, coarse tuning loop and fine tuning loop start simultaneously, and the coarse tuning loop plays a major role, and when loop locked near phase place, turn-offed in the coarse tuning loop, only fine tuning loop works.

Trigger is synchronized to reference signal the output of voltage controlled oscillator.The fine tuning phase detection discriminator is not to differentiate differing of reference signal and feedback signal, but is used for differentiating reference signal and by differing between the reference signal of the synchronous mistake of voltage controlled oscillator.When reference signal took the lead feedback signal, the fine tuning phase detection discriminator was output as actual differing; When reference signal hysteresis feedback signal, the output of fine tuning phase detection discriminator is not actual differing, and this output need be only actual phase difference signal with output behind the reference signal XOR.The purpose of selector is to select output according to sign bit, when sign bit is high, the output of output fine tuning phase detection discriminator, when sign bit when low, be output as the output of XOR gate.

Fig. 3 (a) is the electrical block diagram of coarse tuning phase detection discriminator.Be made of traditional phase detection discriminator and adjunct circuit, all circuit all are operated in the low frequency frequency range.Output state signal by the input signal rising edge along decision.When reference signal fref took the lead feedback signal fdiv, output up was high, will be resetted by the rising edge of back to back feedback signal fdiv.When signal fdiv took the lead reference signal fref, output signal dn put height, will be resetted by the rising edge of back to back fref signal.When reference signal fref took the lead the fdiv signal, sign bit was high level, and when reference signal fref hysteresis fdiv, sign bit is low level.Delay circuit is for generation of the signal of certain pulsewidth, this signal deciding the width in dead band.

Coarse tuning phase detection discriminator sequential chart at this moment, is supposed fref shown in Fig. 3 (b) and Fig. 3 (c), differing of fdiv signal is Δ t, and the fref signal takes the lead the fdiv signal, establishes the signal that time-delay produces the td width.When differing less than by the time-delay width td of delay circuit definition time of fref signal and fdiv signal, the output up of coarse tuning phase detection discriminator, dn are low level, and whole coarse tuning loop is turned off, and can ignore the steady-state behaviour influence of whole phase-locked loop.When fref signal and fdiv signal differ the time-delay width td that Δ t produces greater than delay circuit the time, the output up of phase detection discriminator or the width of dn output signal are actual the differing between fref signal and the fdiv signal.The output of up or dn signal put high during, discharge and recharge to loop filter opening follow-up charge pump, reach the purpose of control voltage controlled oscillator output frequency.The static phase when size in dead band must be greater than loop-locking (this is because the charge pump current mismatch, and leakage of current and phase detection discriminator output delay difference cause).If the width in dead band is less than static phase, even this is when making loop-locking, does not effectively turn-off in the coarse tuning loop yet, and this will disturb the fine tuning loop works.The size in dead band can not surpass the treatable frequency difference in coarse tuning loop.The frequency difference of reference frequency and voltage controlled oscillator output is to be subject to the fine tuning phase detection discriminator, and excessive dead band makes that the fine tuning loop can't operate as normal.

Fig. 4 is the first charge pump circuit structural representation, and it provides the charge or discharge electric current to the loop filter with low-pass characteristic, can be described as the current source that a switch switches simply.Be input as differ, selector output and sign bit.Introducing differs as the main consideration of input signal in approach locking, and trigger can not correctly be handled the sequential relationship between voltage controlled oscillator output and the reference signal.Phase difference signal is as control signal, and when phase difference signal was high level, selector output and sign bit formed up and dn signal by combinational circuit.The edge of phase difference signal high-low level conversion, up and dn signal are turn-offed effectively, thereby inoperative substantially in the fine tuning loop by the noise of frequency divider introducing, and this makes the fine tuning loop can improve phase noise performance in the band effectively.When differing to high level, selector output and sign bit work, and when differing to low level, selector output and sign bit output are turned off.When sign bit was high level, the up switch played a major role, and when sign bit was low level, the dn switch played a major role.When the up signal when low, Iup charges to loop filter, causes control voltage of voltage-controlled oscillator to raise; When the dn signal is high, loop filter discharges by Idn, causes control voltage of voltage-controlled oscillator to descend.The electric current of charge pump has direct relation with loop bandwidth, when static in order to make loop bandwidth and dynamically the time loop bandwidth keep reasonably relation, the electric current of charge pump need to select choose reasonable.

Fig. 5 is a design example of phase-locked loop frequency integrator, reference frequency is 2.046MHz, the voltage controlled oscillator reference frequency output is 2.44GHz-2.67GHz, frequency dividing ratio is 1255, first charge pump, 1 electric current is 1mA, second charge pump, 2 electric currents are 1uA, and the dead zone range of thick phase detection discriminator is 1.5ns.Emulation shows that when turn-offed in the coarse tuning loop, the fine tuning loop played a major role, because second charge pump, 2 electric currents are less, in the long time, control voltage of voltage-controlled oscillator begins trend and stablizes, and the phase place locking can be realized in this explanation fine tuning loop.

When electrification reset or frequency dividing ratio change, work simultaneously in coarse tuning loop and fine tuning loop, and what play a major role is the coarse tuning loop, and when approach locking, the coarse tuning phase detection discriminator in coarse tuning loop automatically shuts down, and the coarse tuning loop is corresponding shutoff also.This moment, reference signal fref and feedback signal fdiv realized same frequency, but did not realize same-phase, and the phase extent is relevant with the delay circuit of coarse tuning phase detection discriminator.This moment only fine tuning loop works, the electric current of second charge pump 2 avoids fine tuning loop loop bandwidth wide much smaller than the electric current of first charge pump 1.The fine tuning loop does not have frequency divider, thus loop bandwidth be coarse tuning loop loop bandwidth N doubly, N is the frequency dividing ratio of frequency divider.In order to dwindle the fine tuning loop bandwidth, need reduce the electric current of sampled charge pump, avoid the loop bandwidth gap of two loops excessive.

The present invention is better than the phase-locked loop frequency integrator of traditional structure, because when lock-out state, only fine tuning loop works is effectively turn-offed in the output of coarse tuning loop.The fine tuning loop does not comprise the frequency divider on the feedback path, this means to have lacked source of phase noise in the band.Effectively eliminated by the phase noise that frequency divider causes, thereby can be improved the interior phase noise of band of system.In addition, the fine tuning loop that the present invention introduces all is operated in low-frequency range except trigger, do not increase a lot of additional power consumptions.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (4)

Translated fromChinese

1.一种用于提高带内相位噪声性能的锁相环频率综合器结构，其特征在于，该锁相环频率综合器结构由粗调谐回路和精调谐回路两个环路构成，其中，该粗调谐回路用来选择不同的频率控制字，实现环路的频率锁定，该精调谐回路用来实现环路的相位锁定；1. A phase-locked loop frequency synthesizer structure for improving in-band phase noise performance, it is characterized in that, this phase-locked loop frequency synthesizer structure is made of coarse tuning loop and two loops of fine tuning loop, wherein, the The coarse tuning loop is used to select different frequency control words to realize the frequency locking of the loop, and the fine tuning loop is used to realize the phase locking of the loop;其中，所述粗调谐回路由粗调谐鉴相鉴频器、第一电荷泵(1)、环路滤波器、压控振荡器和分频器依次连接而成，精调谐回路由触发器、精调谐鉴相鉴频器、异或门、选择器、第二电荷泵(2)、环路滤波器和压控振荡器依次连接而成，其中压控振荡器和环路滤波器为两个环路所共有；Wherein, the coarse tuning loop is formed by sequentially connecting a coarse tuning phase detector, a first charge pump (1), a loop filter, a voltage-controlled oscillator and a frequency divider, and the fine tuning loop is composed of a flip-flop, a fine The tuned phase frequency detector, XOR gate, selector, second charge pump (2), loop filter and voltage-controlled oscillator are connected in sequence, and the voltage-controlled oscillator and loop filter are two loops shared by the road;所述精调谐鉴相鉴频器用来比较参考信号和经过压控振荡器同步后的参考信号之间的相差；The fine-tuning phase and frequency detector is used to compare the phase difference between the reference signal and the reference signal synchronized by the voltage-controlled oscillator;当参考信号超前反馈信号时，选择器输出精调谐鉴相鉴频器的输出信号，当参考信号滞后反馈信号时，选择器输出精调谐鉴相鉴频器输出与参考信号异或后的信号；When the reference signal leads the feedback signal, the selector outputs the output signal of the fine-tuning phase detector and frequency detector, and when the reference signal lags behind the feedback signal, the selector outputs the signal after the XOR output of the fine-tuning phase detector and frequency detector and the reference signal;所述触发器的时钟信号为压控振荡器的输出，而触发信号为参考信号，触发器将参考信号同步到压控振荡器的输出；The clock signal of the flip-flop is the output of the voltage-controlled oscillator, and the trigger signal is a reference signal, and the flip-flop synchronizes the reference signal to the output of the voltage-controlled oscillator;所述第二电荷泵(2)的输入信号为选择器的输出、粗鉴相鉴频器输出的相差和符号位，当相差信号为高电平时，选择器的输出和符号位通过逻辑电路形成第二电荷泵(2)的输入，当相差信号为低电平时，第二电荷泵(2)的输入为低电平。The input signal of the second charge pump (2) is the output of the selector, the phase difference and the sign bit output by the coarse phase and frequency detector, and when the phase difference signal is high level, the output of the selector and the sign bit are formed by a logic circuit The input of the second charge pump (2), when the phase difference signal is at low level, the input of the second charge pump (2) is at low level.2.根据权利要求1所述的用于提高带内相位噪声性能的锁相环频率综合器结构，其特征在于，在环路的相位被锁定时，粗调谐回路被关断，仅精调谐回路工作。2. the phase-locked loop frequency synthesizer structure that is used to improve in-band phase noise performance according to claim 1, is characterized in that, when the phase of loop is locked, coarse tuning loop is shut off, and only fine tuning loop Work.3.根据权利要求1所述的用于提高带内相位噪声性能的锁相环频率综合器结构，其特征在于，当相差大于粗调谐鉴相鉴频器的死区大小时，两个环路同时工作，注入到环路滤波器的电流为两个电荷泵电流之和；当相差小于粗调谐鉴相鉴频器的死区大小时，粗调谐回路自动关断，仅精调谐回路工作。3. the phase-locked loop frequency synthesizer structure that is used to improve in-band phase noise performance according to claim 1, is characterized in that, when phase difference is greater than the dead zone size of coarse-tuning phase-detection-frequency discriminator, two loops Working at the same time, the current injected into the loop filter is the sum of the currents of the two charge pumps; when the phase difference is less than the dead zone of the coarse tuning phase detector, the coarse tuning loop is automatically turned off, and only the fine tuning loop works.4.根据权利要求1所述的用于提高带内相位噪声性能的锁相环频率综合器结构，其特征在于，在频率切换时，粗调谐回路和精调谐回路同时工作，当接近锁定时，粗调谐回路自动关断，仅精调谐回路工作，粗调谐回路的关断是自动平滑进行的；在锁定状态时，粗调谐回路对系统的稳态性能没有影响。4. the phase-locked loop frequency synthesizer structure that is used to improve in-band phase noise performance according to claim 1, is characterized in that, when frequency switching, coarse tuning loop and fine tuning loop work simultaneously, when close to locking, The coarse tuning loop is automatically shut down, and only the fine tuning loop works, and the shutdown of the coarse tuning loop is automatic and smooth; in the locked state, the coarse tuning loop has no effect on the steady-state performance of the system.

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