CN102263019A - Method for fabricating self-aligned trench power semiconductor structure - Google Patents

Abstract

A manufacturing method of a self-aligned trench type power semiconductor structure comprises the following steps: a) forming a trench polysilicon gate structure in a silicon substrate; b) forming a self-aligned polysilicon extension structure which extends upwards from the groove type polysilicon gate structure, wherein the width of the self-aligned polysilicon extension structure is smaller than that of the groove type polysilicon gate structure; c) oxidizing the self-aligned polysilicon extension structure to form a silicon monoxide protrusion structure above the trench polysilicon gate structure; and d) forming a spacer structure (spacer) on the side of the silicon oxide protrusion structure to define a source contact in the silicon substrate. The manufacturing method provided by the invention utilizes a Self-Alignment (Self-Alignment) process to reduce the spacing distance between the trench polysilicon gate structure and the source contact window, can overcome the limit of a lithography process, is beneficial to improving the yield control of the process, improves the uniformity of the device characteristics at different positions on a Wafer (Wafer), and has low cost and high feasibility.

Description

The manufacture method of autoregistration groove power semiconductor structure

Technical field

The present invention relates to a kind of manufacture method of groove power semiconductor structure, the manufacture method of particularly a kind of autoregistration (self-aligned) trench semiconductor structure.

Background technology

Figure 1A and Fig. 1 C are the making flow process of a typical groove power semiconductor structure.Shown in Figure 1A, at first, on asilicon substrate 110, make gate trench 120.Subsequently, the inner surface alonggate trench 120 forms a grid oxic horizon 130.Next, the deposit spathic silicon material is in the surface ofsilicon substrate 110, and removes unnecessary polycrystalline silicon material in the mode of eat-backing (etching back), forms a gridpolycrystalline silicon structure 140 in thisgate trench 120.

Next, shown in Figure 1B, implant alloy insilicon substrate 110, to formbody 150 all aroundgate grooves 120 in ion implantation mode.Then, implant different conductivity type dopant inbody 150, to formsource doping region 160 in the top of body layer 150.Next, shown in Fig. 1 C, deposit adielectric layer 170 in the exposed surface ofsilicon substrate 110, and fill up gate trench 120.Then, indielectric layer 170 andbody 150, formcontact hole 180 with exposedsource doping region 160 in the lithography mode.

The development of groove power semiconductor element shrink technology can be subjected to the restriction of the limit of gold-tinted micro-photographing process.Be subject to groove and the critical width (critical dimension) of contact hole and the admissible error (tolerance) of aiming at control,gate trench 120 can't reduce arbitrarily with the distance ofcontact hole 180, otherwise is easy to generate leakage current, causes the variation or anti-snowslide (UIS) ability drop of critical voltage.

Based on this, be subject to groove and the critical width of contact hole and the range of allowable error of aiming at control, how to increase the component density of groove power semiconductor structure, be present technique field problem to be solved.

Summary of the invention

Main purpose of the present invention provides a kind of manufacture method of high-density, trench formula power semiconductor structure, utilize the mode of autoregistration (self alignment), the range of allowable error that overcomes the critical width of gate trench and contact hole and aim at control is for restriction that component density caused.

The invention provides a kind of manufacture method of autoregistration groove power semiconductor structure, comprise the following steps: a) to form a trench polysilicon grid structure in a silicon substrate; B) form an autoregistration polysilicon extended structure and extended upward by the trench polysilicon grid structure, the width of this autoregistration polysilicon extended structure is less than the width of trench polysilicon grid structure; C) the aforementioned autoregistration polysilicon of oxidation extended structure is to form the outstanding structure of silicon monoxide in trench polysilicon grid structure top; And d) forms the side of one first wall structure (spacer), to define the one source pole contact hole in silicon substrate in the outstanding structure of silica.

In other words, the invention provides a kind of manufacture method of autoregistration groove power semiconductor structure, it is characterized in that, comprise the following steps:

Form a trench polysilicon grid structure in a silicon substrate;

Form an autoregistration polysilicon extended structure and extended upward by this trench polysilicon grid structure, the width of this autoregistration polysilicon extended structure is less than the width of this trench polysilicon grid structure;

This autoregistration polysilicon extended structure of oxidation forms the outstanding structure of silicon monoxide in this trench polysilicon grid structure top; And

Form the side of one first wall structure, to define the one source pole contact hole in this silicon substrate in the outstanding structure of this silica.

Can be further understood by means of the following detailed description and accompanying drawings about the advantages and spirit of the present invention.

Description of drawings

Figure 1A and Fig. 1 C are the making flow process of a typical groove power semiconductor structure;

Fig. 2 A to Fig. 2 I is first embodiment of the manufacture method of groove power semiconductor structure of the present invention;

Fig. 3 A to Fig. 3 C is second embodiment of the manufacture method of groove power semiconductor structure of the present invention;

Fig. 4 A to Fig. 4 B is the 3rd embodiment of the manufacture method of groove power semiconductor structure of the present invention;

Fig. 5 A to Fig. 5 D is the 4th embodiment of the manufacture method of groove power semiconductor structure of the present invention.

[main element description of reference numerals]

Silicon substrate 110

Gate trench 120

Gridoxic horizon 130

Gridpolycrystalline silicon structure 140

Body 150

Source doping region 160

Dielectric layer 170

Contacthole 180

Silicon substrate 210

Cover curtain layer 220

Opening 222

Gate trench 230

Gate dielectric 232

Trenchpolysilicon grid structure 240

Thesecond wall structure 250

Autoregistration polysilicon extendedstructure 242

Silica is given prominence tostructure 260

Oxide layer 262

Body 270

Source doping region 280

Thefirst wall structure 265

Sourceelectrode contact hole 282

Heavily dopedregion 285

Source metal 290

Silicon substrate 310

Gate trench 330

Gate dielectric 332

Trenchpolysilicon grid structure 340

Thesecond wall structure 350

Autoregistration polysilicon extendedstructure 342

Protective layer 352

Thick oxide layer 362

Silicon substrate 410

Cover curtain layer 420

Gatetrench 430

Gate dielectric 432

Polysiliconstructure 440

Autoregistration polysiliconextended structure 440a

Trenchpolysilicon grid structure 440b

Silica is given prominence tostructure 460

Embodiment

Technical characterictic of the present invention utilizes hard cover curtain layer (Hard mask) and polysilicon to eat-back the formed height fall in (Polyetch back) back, forms wall structure (spacer) in the polysilicon gate top.And the space that utilizes the wall organization definition to come out, carry out a polysilicon deposition again and eat-back (Poly deposition﹠amp; Etch back) step is to have formed the outstanding structure of polysilicon.Because the outstanding thickness of structure of this polysilicon is thinner, therefore can utilize this polysilicon of thermal oxidation processing procedure (Thermaloxide process) oxidation to give prominence to structure.The high low head of outstanding structure of this thermal oxidation silica that processing procedure forms and silicon substrate just can be applicable to make the wall structure, with the position of definition contact hole.Can avoid traditional gold-tinted processing procedure to be easy to generate the shortcoming of alignment error thus.

Fig. 2 A to Fig. 2 I is first embodiment of the manufacture method of groove power semiconductor structure of the present invention.Shown in Fig. 2 A, at first, form acover curtain layer 220 in the upper surface of a silicon substrate 210.Cover curtain layer 220 has anopening 222 definition one gate trench 230.Thiscover curtain layer 220 can adopt typical hard cover curtain layer (hard mask), and its constituent material is generally silica or silicon nitride.Subsequently, bycover curtain layer 220 etchingsilicon base materials 210, to formgate trench 230 in silicon substrate 210.Next, form the inner surface of agate dielectric 232 cover gate grooves 230.Subsequently, shown in Fig. 2 B, the deposit spathic silicon material and is inserted in thegate trench 230 on silicon substrate 210.And then impose and eat-back processing procedure, to form trenchpolysilicon grid structure 240 ingate trench 230.

Shown in Fig. 2 B, after forming trenchpolysilicon grid structure 240, directly on the sidewall of theopening 222 ofcover curtain layer 220, make the second wall structure (spacer) 250.These second wall structure, 250 upper surfaces by trenchpolysilicon grid structure 240 extend upward.Next, shown in Fig. 2 C, in the second wall structure, 250 defined spaces, insert polycrystalline silicon material, to form autoregistration polysilicon extendedstructure 242 in trenchpolysilicon grid structure 240 tops.By the making of thesecond wall structure 250, the width of autoregistration polysilicon extendedstructure 242 is less than the width of trenchpolysilicon grid structure 240, and the central authorities of autoregistration polysilicon extendedstructure 242 rough alignment trenchpolysilicon grid structures 240.

Next, shown in Fig. 2 D, remove thecover curtain layer 220 and thesecond wall structure 250, make outside the upper surface of the side of autoregistration polysilicon extendedstructure 242 and trenchpolysilicon grid structure 240 is exposed to.This step can adopt the selective etch processing procedure, reaches the purpose that removes thecover curtain layer 220 and the second wall structure 250.With regard to a preferred embodiment, the aforementionedcover curtain layer 220 and thesecond wall structure 250 can utilize silica material to make, to simplify this selective etch processing procedure.

Subsequently, shown in Fig. 2 E, the exposed surface of autoregistration polysilicon extendedstructure 242 and trenchpolysilicon grid structure 240 is imposed an oxidation process, to form theoutstanding structure 260 of silicon monoxide in the top of trench polysilicon grid structure 240.Because outside the side of autoregistration polysilicon extendedstructure 242 is exposed to fully, and the width of autoregistration polysilicon extendedstructure 242 is much smaller than the width of trench polysilicon grid structure 240.Therefore, this oxidation process only can form oxide layer at the surf zone of trenchpolysilicon grid structure 240, and can not cause too much influence for the sectional dimension of trench polysilicon grid structure 240.Secondly, in the present embodiment, because outside the upper surface ofsilicon substrate 210 is exposed to, therefore, this oxidation process can be simultaneously form anoxide layer 262 at the upper surface ofsilicon substrate 210, for the usefulness of follow-up ion implantation manufacture process.

Next, shown in Fig. 2 F, implant the first conductivity type alloy insilicon substrate 210, to formbody 270 around trenchpolysilicon grid structure 240 in ion implantation mode.Then, implant the second conductivity type alloy in the surf zone ofsilicon substrate 210, to formsource doping region 280 in the top ofbody 270 in ion implantation mode.The aforementioned first conductivity type alloy and the second conductivity type alloy can be respectively P type alloy and N type alloy, or N type alloy and P type alloy.Then, shown in Fig. 2 F, form the sidewall of onefirst wall structure 265, with the position of definition source electrode contact hole in theoutstanding structure 260 of silica.

Next, shown in Fig. 2 G and Fig. 2 H, directly utilize thisfirst wall structure 265 to be shielding, etching covers theoxide layer 262 andsource doping region 280 partly onsilicon substrate 210 surfaces, extends in thesilicon substrate 210 to form source electrode contact hole 282.Subsequently, shown in Fig. 2 H, implant the bottom of the first conductivity type alloy by thefirst wall structure 265, to form a heavily dopedregion 285 inbody 270 to source electrode contact hole 282.At last, shown in Fig. 2 I, form one sourcepole metal level 290 onsilicon substrate 210, to be electrically connected to sourcedoping region 280 andbody 270.

As described above, autoregistration polysilicon extendedstructure 242 is in alignment with the central authorities of trench polysilicon grid structure 240.Therefore, theoutstanding structure 260 of oxidation autoregistration polysilicon extendedstructure 242 formed silica also can be in alignment with the centre of trench polysilicon grid structure 240.Present embodiment directly utilize the sidewall that is made in theoutstanding structure 260 of this silica thefirst wall structure 265 define the position of sourceelectrode contact hole 282, can avoid the generation of the alignment error between different micro-photographing process.In addition, in the present embodiment, the spacing distance of sourceelectrode contact hole 282 and trenchpolysilicon grid structure 240 roughly is that the thickness by thefirst wall structure 265 is determined, therefore, can avoid the restriction of the critical width of micro-photographing process.Again, present embodiment is formed at the silica of trenchpolysilicon grid structure 240 tops and gives prominence to the width of the width ofstructure 260 less than trenchpolysilicon grid structure 240, more help to reduce the spacing distance of sourceelectrode contact hole 282 and trenchpolysilicon grid structure 240, to reach the purpose that improves component density.

Fig. 3 A to Fig. 3 C is second embodiment of the manufacture method of groove power semiconductor structure of the present invention.Below only describe with regard to the difference place of present embodiment and aforementioned first embodiment.At first, as shown in Figure 3A, utilize a photoresist layer (not shown) to form a gate trench 330 in silicon substrate 310.Subsequently, form the inner surface of agate dielectric 332 cover gate grooves 330.Next, insert polycrystalline silicon material in gate trench 330 to form trench polysilicon grid structure 340.This trenchpolysilicon grid structure 340 is positioned at the following part of gate trench 330, and the upper surface of its upper surface andsilicon substrate 310 is a predeterminable range at interval.Subsequently, form thesecond wall structure 350 in gate trench 330.Thissecond wall structure 350 is positioned on the sidewall of upper part of gate trench 330.

Next, shown in Fig. 3 B, insert polycrystalline silicon material in the second wall structure, 350 defined spaces, and impose and eat-back processing procedure, to form autoregistration polysilicon extendedstructure 342 in trenchpolysilicon grid structure 340 tops.Subsequently, shown in Fig. 3 C, form the upper surface that aprotective layer 352 covers autoregistration polysilicon extended structure 342.And then, form athick oxide layer 362 in the surf zone ofsilicon substrate 310 with mode of oxidizing.Protective layer 352 is oxidized to silica in order to prevent autoregistration polysilicon extendedstructure 342 in the oxidation step of Fig. 3 C.Therefore,protective layer 352 is made of silicon nitride, silica or other materials that can effectively completely cut off oxygen atom.

Next, remove thethick oxide layer 362, thesecond wall structure 350 andprotective layer 352 that are positioned atsilicon substrate 310 upper surfaces, make outside autoregistration polysilicon extendedstructure 342 is exposed to, and protrude in the upper surface of silicon substrate 310.When thesecond wall structure 350 andprotective layer 352 all are when being made of silica, can pass through etching mode, removethick oxide layer 362,second wall structure 350 and theprotective layer 352 simultaneously.When thesecond wall structure 350 andprotective layer 352 all are when being made of silicon nitride, can utilize the mode of selective etch to removethick oxide layer 362 earlier, and then removesecond wall structure 350 and the protective layer 352.Certainly, the aforementionedsecond wall structure 350 is made of different materials with protective layer 352.The successive process of present embodiment does not repeat them here as first embodiment of the invention (please refer to Fig. 2 D).

Fig. 4 A and Fig. 4 B are the 3rd embodiment of the manufacture method of groove power semiconductor structure of the present invention.Below only describe with regard to the difference place of present embodiment and aforementioned second embodiment.The step of Fig. 4 A is accepted Fig. 3 B.Shown in Fig. 4 A,, form the upper surface that aprotective layer 352 covers autoregistration polysilicon extendedstructure 342 to form autoregistration polysilicon extendedstructure 342 after the step of trenchpolysilicon grid structure 340 tops.Next; shown in comparison diagram 3C and Fig. 4 B; present embodiment does not adopt mode of oxidizing to formthick oxide layer 362; but directly utilize theprotective layer 352 and thesecond wall structure 350 to be shielding, cut down the thickness ofsilicon substrate 310 with etching mode (for example selective etch mode) by the upper surface of silicon substrate 310.Make autoregistration polysilicon extendedstructure 342 protrude in the upper surface of silicon substrate 310.Then, remove theprotective layer 352 and thesecond wall structure 350 again, make outside autoregistration polysilicon extendedstructure 342 is exposed to.The aforesaidprotective layer 352 and thesecond wall structure 350 are made of materials such as silica or silicon nitrides, are beneficial to adopt etching mode to cut down the thickness ofsilicon substrate 310.

Previous embodiment utilizes theprotective layer 352 and thesecond wall structure 350 to be shielding etching silicon base material 310.But, the present invention is not limited to this.Present embodiment can also only utilize theprotective layer 352 that is positioned at autoregistration polysilicon extendedstructure 342 tops to be shielding, and collocation has the etching technique of directivity, as reactive ion etching (RIE), comes etchingsilicon base material 310.

Fig. 5 A to Fig. 5 D is the 4th embodiment of the manufacture method of groove power semiconductor structure of the present invention.Below only describe with regard to the difference place of present embodiment and aforementioned first embodiment.Shown in Fig. 5 A, at first, form acover curtain layer 420 in the upper surface of a silicon substrate 410.Subsequently, bycover curtain layer 420 etchingsilicon base materials 410, to formgate trench 430 in silicon substrate 410.Next, form the inner surface of agate dielectric 432 cover gate grooves 430.Subsequently, the deposit spathic silicon material and is inserted in the opening 422 ofgate trench 430 and covercurtain layer 420 on silicon substrate 410.And then polycrystalline silicon material imposed eat-back processing procedure, to form a polysilicon structure 440.Thispolysilicon structure 440 is extended upwardly in thecover curtain layer 420 bygate trench 430.

Next, shown in Fig. 5 B, removecover curtain layer 420, make outside the upper part ofpolysilicon structure 440 is exposed to.Then, utilize the exposed surface of one oxidation process oxidation polysilicon structure 440.Next, shown in Fig. 5 C,, remove the part ofpolysilicon structure 440 surface oxidations, with the width of the upper part of cutting downpolysilicon structure 440 in etched mode.As shown in FIG., outside the upper part of thispolysilicon structure 440 was exposed to, following then was to be positioned atsilicon substrate 410 partly.Therefore, behind peroxidating and etched processing procedure, upper part at thispolysilicon structure 440 can form the upper surface that the narrower autoregistration polysilicon extendedstructure 440a of a width protrudes insilicon substrate 410, and following partly then constituting a trenchpolysilicon grid structure 440b is positioned atsilicon substrate 410.

Aforementioned manufacturing process utilizes one oxidation process oxidation to be exposed toouter polysilicon structure 440 earlier, and then cuts down the width of the upper part ofpolysilicon structure 440 with etching mode.But, the present invention is not limited to this.With regard to an embodiment, please refer to shown in Fig. 5 A, after removingcover curtain layer 420, can directly carry out etching, to form the autoregistration polysilicon extendedstructure 440a shown in Fig. 5 C at being exposed toouter polysilicon structure 440.

Subsequently, shown in Fig. 5 D, carry out the once oxidation processing procedure again, make autoregistration polysilicon extendedstructure 440a oxidized fully, be covered in trenchpolysilicon grid structure 440b top to form theoutstanding structure 460 of silica.The subsequent step of present embodiment and first embodiment of the invention (please refer to Fig. 2 E) are similar, do not repeat them here.

As described above, manufacture method provided by the present invention utilizes the processing procedure of autoregistration (Self-Alignment) to dwindle spacing distance between trench polysilicon grid structure and the source electrode contact hole, therefore, can overcome the limit of micro-photographing process.Secondly, manufacture method provided by the present invention also helps to promote the yield control of processing procedure, improves the uniformity that wafer (Wafer) is gone up the element characteristic of diverse location.In addition, manufacture method provided by the present invention is also arranged in pairs or groups easily at existing groove power semiconductor processing procedure, is specially adapted to the processing procedure of narrow groove, therefore, has the advantage that cost is low and feasibility is high.

The above; it only is preferred embodiment of the present invention; when can not limiting claim protection range of the present invention with this, promptly all simple equivalent of being done according to claim of the present invention and invention description content change and revise, and all still belong in the scope that claim of the present invention contains.Arbitrary embodiment of the present invention in addition or claim must not reach disclosed whole purposes or advantage or characteristics.In addition, summary part and title only are the usefulness that is used for assisting the patent document search, are not to be used for limiting claim protection range of the present invention.

Claims (13)

Translated fromChinese

1.一种自对准沟槽式功率半导体结构的制造方法，其特征在于，包括下列步骤：1. A method for manufacturing a self-aligned trench type power semiconductor structure, characterized in that, comprising the following steps:形成一沟槽式多晶硅栅极结构于一硅基材内；forming a trenched polysilicon gate structure in a silicon substrate;形成一自对准多晶硅延伸结构由该沟槽式多晶硅栅极结构向上延伸，该自对准多晶硅延伸结构的宽度小于该沟槽式多晶硅栅极结构的宽度；forming a self-aligned polysilicon extension structure extending upward from the trenched polysilicon gate structure, the width of the self-aligned polysilicon extension structure being smaller than the width of the trenched polysilicon gate structure;氧化该自对准多晶硅延伸结构，形成一氧化硅突出结构于该沟槽式多晶硅栅极结构上方；以及Oxidizing the self-aligned polysilicon extension structure to form a silicon oxide protrusion structure above the trenched polysilicon gate structure; and形成一第一间隔层结构于该氧化硅突出结构的侧边，以定义一源极接触窗。A first spacer structure is formed on the side of the silicon oxide protruding structure to define a source contact window.2.如权利要求1所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，形成该沟槽式多晶硅栅极结构的步骤包括：2. The method for manufacturing a self-aligned trenched power semiconductor structure as claimed in claim 1, wherein the step of forming the trenched polysilicon gate structure comprises:形成一罩幕层于该硅基材的上表面，该罩幕层具有一开口定义一栅极沟槽；forming a mask layer on the upper surface of the silicon substrate, the mask layer having an opening to define a gate trench;通过该罩幕层蚀刻该硅基材，以形成该栅极沟槽于该硅基材内；etching the silicon substrate through the mask layer to form the gate trench in the silicon substrate;形成一栅极介电层覆盖该栅极沟槽的内侧表面；以及forming a gate dielectric layer covering the inner surface of the gate trench; and填入多晶硅材料于该栅极沟槽内。Filling polysilicon material into the gate trench.3.如权利要求2所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，形成该自对准多晶硅延伸结构的步骤包括：3. The method for manufacturing a self-aligned trench power semiconductor structure as claimed in claim 2, wherein the step of forming the self-aligned polysilicon extension structure comprises:形成一第二间隔层结构于该罩幕层的该开口的侧边；以及forming a second spacer structure on the side of the opening of the mask layer; and填入多晶硅材料于该开口内，以形成该自对准多晶硅延伸结构。Filling polysilicon material into the opening to form the self-aligned polysilicon extension structure.4.如权利要求3所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，该第二间隔层结构由氧化硅或氮化硅所构成。4 . The method for manufacturing a self-aligned trench power semiconductor structure as claimed in claim 3 , wherein the second spacer structure is made of silicon oxide or silicon nitride.5.如权利要求2所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，该罩幕层由氧化硅所构成。5. The method for manufacturing a self-aligned trench power semiconductor structure as claimed in claim 2, wherein the mask layer is made of silicon oxide.6.如权利要求1所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，该自对准多晶硅延伸结构完全被氧化，以形成该氧化硅突出结构突出该硅基材的上表面。6. The method for manufacturing a self-aligned trench power semiconductor structure according to claim 1, wherein the self-aligned polysilicon extension structure is completely oxidized to form the silicon oxide protruding structure protruding from the silicon substrate upper surface.7.如权利要求1所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，氧化该自对准多晶硅延伸结构的步骤同时氧化该沟槽式多晶硅栅极结构的上表面。7. The method for fabricating a self-aligned trench type power semiconductor structure as claimed in claim 1, wherein the step of oxidizing the self-aligned polysilicon extension structure simultaneously oxidizes the upper surface of the trench type polysilicon gate structure.8.如权利要求2所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，该多晶硅材料填入该栅极沟槽与该开口以形成一多晶硅结构，该多晶硅结构的一下部分构成该沟槽式多晶硅栅极结构，并且，形成该自对准多晶硅延伸结构的步骤包括：8. The method for manufacturing a self-aligned trench power semiconductor structure as claimed in claim 2, wherein the polysilicon material is filled into the gate trench and the opening to form a polysilicon structure, and the polysilicon structure has a Partially forming the trenched polysilicon gate structure, and forming the self-aligned polysilicon extension structure includes:移除该罩幕层，使该多晶硅结构的一上部份裸露于外；以及removing the mask layer to expose an upper portion of the polysilicon structure; and削减该多晶硅结构的该上部份的宽度，以形成该自对准多晶硅延伸结构突出该硅基材。The width of the upper portion of the polysilicon structure is trimmed to form the self-aligned polysilicon extension structure protruding from the silicon substrate.9.如权利要求8所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，削减该多晶硅结构的该上部份的宽度的步骤包括：9. The method of manufacturing a self-aligned trench power semiconductor structure as claimed in claim 8, wherein the step of reducing the width of the upper portion of the polysilicon structure comprises:以氧化方式，形成一氧化层于该多晶硅结构的该上部份的表面；以及forming an oxide layer on the surface of the upper portion of the polysilicon structure by oxidation; and去除该氧化层，以形成该自对准多晶硅延伸结构突出该硅基材。The oxide layer is removed to form the self-aligned polysilicon extension structure protruding from the silicon substrate.10.如权利要求1所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，形成该沟槽式多晶硅栅极结构的步骤包括：10. The method for manufacturing a self-aligned trenched power semiconductor structure as claimed in claim 1, wherein the step of forming the trenched polysilicon gate structure comprises:利用一光阻层形成一栅极沟槽于该硅基材内；forming a gate trench in the silicon substrate by using a photoresist layer;形成一栅极介电层覆盖该栅极沟槽的内侧表面；以及forming a gate dielectric layer covering the inner surface of the gate trench; and填入多晶硅材料于该栅极沟槽内，以形成该沟槽式多晶硅栅极结构于该栅极沟槽的下部份。Filling polysilicon material into the gate trench to form the trenched polysilicon gate structure at the lower part of the gate trench.11.如权利要求10所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，形成该自对准多晶硅延伸结构的步骤包括：11. The method for manufacturing a self-aligned trench power semiconductor structure according to claim 10, wherein the step of forming the self-aligned polysilicon extension structure comprises:形成一第二间隔层结构于该栅极沟槽的上部份的侧边；forming a second spacer structure on the side of the upper portion of the gate trench;填入多晶硅材料于该栅极沟槽的该上部份，以形成该自对准多晶硅延伸结构；以及filling the upper portion of the gate trench with polysilicon material to form the self-aligned polysilicon extension structure; and由该硅基材的上表面削减该硅基材的厚度，使该自对准多晶硅延伸结构突出该硅基材。The thickness of the silicon substrate is cut from the upper surface of the silicon substrate, so that the self-aligned polysilicon extension structure protrudes from the silicon substrate.12.如权利要求11所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，由该硅基材的上表面削减该硅基材的厚度的步骤包括：12. The method for manufacturing a self-aligned trench power semiconductor structure as claimed in claim 11, wherein the step of reducing the thickness of the silicon substrate from the upper surface of the silicon substrate comprises:以氧化方式，形成一厚氧化层于该硅基材的表面区域；以及forming a thick oxide layer on the surface region of the silicon substrate by oxidation; and移除该厚氧化层，使该自对准多晶硅延伸结构突出该硅基材。The thick oxide layer is removed such that the salient polysilicon extension protrudes from the silicon substrate.13.如权利要求11所述的自对准沟槽式功率半导体结构的制造方法，其特征在于，由该硅基材的上表面削减该硅基材的厚度的步骤是形成一保护层覆盖该自对准多晶硅延伸结构，并利用该保护层为屏蔽蚀刻该硅基材。13. The method for manufacturing a self-aligned trench power semiconductor structure as claimed in claim 11, wherein the step of reducing the thickness of the silicon substrate from the upper surface of the silicon substrate is to form a protective layer to cover the self-aligning polysilicon extension structures, and etching the silicon substrate using the passivation layer as a mask.

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