CN102262904A - Multi-bit 3D Mask Programmable Memory - Google Patents

Abstract

The invention provides a multi-bit-per-cell (3D-MPROM) three-dimensional mask programming memory_B) Each of which is capable of storing multiple bits (e.g., 4 bits) of information. 3D-MPROM_BThe adjustable range of the volt-ampere curve of the memory element is increased by adding a resistance film and/or a resistance element in the memory element.

Description

Translated fromChinese

多位元三维掩膜编程存储器Multi-bit 3D Mask Programmable Memory

技术领域technical field

本发明涉及集成电路领域，更确切地说，涉及掩膜编程存储器。This invention relates to the field of integrated circuits, and more specifically, to mask programmed memories.

背景技术Background technique

掩膜编程存储器(mask-programmable read-only memory，简称为mask-ROM)是指在生产过程中，尤其是光刻工艺中录入数据的存储器。三维掩膜编程存储器(three-dimensional mask-programmable memory，简称为3D-MPROM)是一种含有多个相互叠置掩膜编程存储层的mask-ROM。与其它mask-ROM相比，3D-MPROM具有极大的容量和极低的成本。Mask-programmable read-only memory (referred to as mask-ROM for short) refers to the memory for entering data in the production process, especially in the photolithography process. Three-dimensional mask-programmable memory (referred to as 3D-MPROM) is a mask-ROM containing multiple overlapping mask programming storage layers. Compared with other mask-ROMs, 3D-MPROM has enormous capacity and extremely low cost.

中国专利“三维只读存储器及其制造方法”(专利号：ZL98119572.5)提出了多种3D-MPROM。图1描述了一种典型3D-MPROM。它含有一个半导体衬底0s和一个3D-MPROM堆0。半导体衬底0s里的晶体管构成3D-MPROM的周边电路。3D-MPROM堆0堆叠在衬底0s上。在这个例子中，3D-MPROM堆0含有两个存储层100、200，存储层200叠置在存储层100上。每个存储层(如100)上含有多条地址线(如20a、20b、30a...)和多个3D-MPROM存储元(简称为3D-MPROM元)(如1aa、1ab...)。接触通道孔(如30av、30av’)将存储层(如100、200)和衬底0s耦合。The Chinese patent "Three-dimensional ROM and its manufacturing method" (Patent No.: ZL98119572.5) proposes various 3D-MPROMs. Figure 1 describes a typical 3D-MPROM. It contains a semiconductor substrate 0s and a 3D-MPROM stack 0. The transistors in the semiconductor substrate 0s form the peripheral circuits of the 3D-MPROM. A 3D-MPROM stack 0 is stacked on a substrate 0s. In this example, the 3D-MPROM stack 0 contains twostorage layers 100 , 200 , thestorage layer 200 being stacked on top of thestorage layer 100 . Each storage layer (such as 100) contains multiple address lines (such as 20a, 20b, 30a...) and multiple 3D-MPROM storage elements (referred to as 3D-MPROM elements) (such as 1aa, 1ab...) . Contact via holes (eg 30av, 30av') couple the storage layer (eg 100, 200) to the substrate 0s.

以往技术中，大多数3D-MPROM采用二进制，即3D-MPROM元具有两种状态‘1’和‘0’：处于状态‘1’的存储元(‘1’存储元)能导通电流，而处于状态‘0’的存储元(‘0’存储元)则不能。每个二进制3D-MPROM元可以存储1位信息。In the past technology, most 3D-MPROMs use binary, that is, 3D-MPROM elements have two states '1' and '0': the storage element in state '1' ('1' storage element) can conduct current, while A memory cell in state '0' ('0' memory cell) cannot. Each binary 3D-MPROM cell can store 1 bit of information.

如图2A所示，‘1’存储元1aa含有一条高地址线20a、一层ROM膜3a和一条低地址线30a。ROM膜3a含有准导通膜5。该准导通膜5具有非线性电阻特性，它在一个方向上的导电性好于另一方向。准导通膜5一般采用二极管。这里，它是一个p-i-n二极管，并含有p膜12、i膜14和n膜16。准导通膜5也可以是其它二极管，如pn二极管、肖特基二极管等。由于在绝缘介质11中含有通道孔18，当在高地址线20a上加读电压时，在低地址线30a上能测到读电流。这对应于状态‘1’。As shown in FIG. 2A, a '1' memory cell 1aa includes anupper address line 20a, a layer ofROM film 3a and alower address line 30a. TheROM film 3 a includes a quasi-conductingfilm 5 . The quasi-conductingfilm 5 has non-linear resistance characteristics, and its conductivity is better in one direction than in the other direction. The quasi-conductingfilm 5 generally adopts a diode. Here, it is a p-i-n diode, and includesp film 12 , ifilm 14 andn film 16 . The quasi-conductingfilm 5 can also be other diodes, such as pn diodes, Schottky diodes and the like. Since thevia hole 18 is included in theinsulating medium 11, when a read voltage is applied to thehigh address line 20a, a read current can be measured on thelow address line 30a. This corresponds to state '1'.

如图2B所示，‘0’存储元1ba含有一条高地址线20b、一层ROM膜3b和一条低地址线30a。ROM膜3b含有绝缘介质膜11。由于在绝缘介质11中不含有通道孔，当在高地址线20b上加读电压时，在低地址线30a上不能测到读电流。这对应于状态‘0’。As shown in FIG. 2B, the '0' memory cell 1ba includes anupper address line 20b, a layer ofROM film 3b and alower address line 30a. TheROM film 3b includes an insulatingdielectric film 11 . Since there is no via hole in theinsulating medium 11, when a read voltage is applied to theupper address line 20b, no read current can be measured on thelower address line 30a. This corresponds to state '0'.

除二进制外，3D-MPROM也可以采用N(N为正整数且N＞2)进制，即3D-MPROM元具有N种状态，处于不同状态的存储元具有不同的伏-安特性。每个N进制3D-MPROM元可以存储b位信息。这里，b＝log₂(N)；b可以是整数，也可以是非整数。中国专利申请“N进制掩膜编程存储器”(专利申请号：200610100860.8)描述了多种N进制3D-MPROM，包括结形状型N进制3D-MPROM和结特性型N进制3D-MPROM。In addition to binary, 3D-MPROM can also use N (N is a positive integer and N>2) system, that is, 3D-MPROM elements have N states, and memory elements in different states have different V-A characteristics. Each N-ary 3D-MPROM element can store b-bit information. Here, b=log₂ (N); b can be an integer or a non-integer. Chinese patent application "N-ary mask programming memory" (patent application number: 200610100860.8) describes a variety of N-ary 3D-MPROMs, including junction-shaped N-ary 3D-MPROMs and junction-characteristic N-ary 3D-MPROMs .

在结形状型N进制3D-MPROM中，不同状态的存储元具有不同的结构，如不同的结形状。如图2C所示，一个结形状型存储元1ca含有一条高地址线20c、一层ROM膜3c和一条低地址线30a。ROM膜3c含有一层绝缘介质11、一个部分通道孔18’和一层准导通膜5。与图2A相比，部分通道孔18’只能将高地址线20c和准导通膜5部分耦合。相应地，存储元1ca与存储元1aa具有不同的伏-安特性。In the junction-shaped N-ary 3D-MPROM, memory cells in different states have different structures, such as different junction shapes. As shown in FIG. 2C, a junction type memory cell 1ca includes anupper address line 20c, a ROM film 3c and alower address line 30a. The ROM film 3c contains a layer ofinsulating medium 11, a partial channel hole 18' and a layer of quasi-conductingfilm 5. Compared with FIG. 2A, part of the via hole 18' can only partially couple theupper address line 20c with the quasi-conductingfilm 5. Correspondingly, the storage cell 1ca and the storage cell 1aa have different voltage-current characteristics.

在结特性型N进制3D-MPROM中，不同状态的存储元具有不同的结特性，如不同的掺杂浓度。如图2D所示，一个结特性型存储元1da含有一条高地址线20d、一层ROM膜3d和一条低地址线30a。ROM膜3d与存储元1aa中的ROM膜3a(图2A)具有类似的结构，它们均含有p-i-n二极管。但是，ROM膜3d的二极管5’与ROM膜3a的二极管5具有不同的掺杂浓度。这可以通过光刻和离子注入来实现。相应地，存储元1da与存储元1aa具有不同的伏-安特性。In the junction-type N-ary 3D-MPROM, memory elements in different states have different junction characteristics, such as different doping concentrations. As shown in FIG. 2D, a junction characteristic type memory cell 1da includes anupper address line 20d, aROM film 3d and alower address line 30a. TheROM film 3d has a similar structure to theROM film 3a (FIG. 2A) in the memory cell 1aa, both of which contain p-i-n diodes. However, the diode 5' of theROM film 3d has a different doping concentration from thediode 5 of theROM film 3a. This can be achieved by photolithography and ion implantation. Correspondingly, the storage cell 1da and the storage cell 1aa have different voltage-current characteristics.

本分明进一步改进了上述专利申请的实施方法，以便在更大的范围(如～4.5V或更大)内调节存储元的伏-安曲线，从而实现多位元(如4位元)。在本说明书中，b位元(b-bit-per-cell)是指每个存储元能存储b位信息，如4位元存储器中每个存储元能存储4位信息。相应地，本分明提出一种多位元三维掩膜编程存储器(large bit-per-cell 3D-MPROM，简称为3D-MPROM_B)。The present invention further improves the implementation method of the above-mentioned patent application so as to adjust the voltage-ampere curve of the storage element in a larger range (such as ~4.5V or greater), thereby realizing multi-bit (such as 4-bit). In this specification, b-bit-per-cell means that each storage cell can store b-bit information, for example, each storage cell in a 4-bit memory can store 4-bit information. Correspondingly, the present invention clearly proposes a multi-bit three-dimensional mask programming memory (large bit-per-cell 3D-MPROM, referred to as 3D-MPROM_B for short).

发明内容Contents of the invention

本发明的主要目的是提供一种具有超大容量的三维掩膜编程存储器。The main purpose of the present invention is to provide a three-dimensional mask programming memory with super large capacity.

本发明的另一目的是提供一种具有超低成本的三维掩膜编程存储器。Another object of the present invention is to provide a three-dimensional mask programmed memory with ultra-low cost.

本发明的另一目的是提供一种每个存储元可以存储多位(如4位或更多)信息的三维掩膜编程存储器。Another object of the present invention is to provide a three-dimensional mask programming memory in which each memory cell can store multiple bits (eg, 4 bits or more) of information.

根据这些以及别的目的，本发明提供一种多位元三维掩膜编程存储器(3D-MPROM_B)，其每个存储元能存储多位(如4位)信息。3D-MPROM_B通过在存储元中增加电阻膜和/或电阻元素来增大存储元伏-安曲线可调节的范围。相应地，3D-MPROM_B可以分为含有电阻膜的3D-MPROM_B(3D-MPROM_Bwith resistive layer，简称为3D-MPROM_RL)和含有电阻元素的3D-MPROM_B(3D-MPROM_B with resistive element，简称为3D-MPROM_RE)。According to these and other objects, the present invention provides a multi-bit three-dimensional mask programming memory (3D-MPROM_B ), each memory cell of which can store multi-bit (eg, 4-bit) information. 3D-MPROM_B increases the adjustable range of the voltage-ampere curve of the memory cell by adding a resistive film and/or a resistive element in the memory cell. Correspondingly, 3D-MPROM_B can be divided into 3D-MPROM_B with resistive layer (3D-MPROM_B with resistive layer, referred to as 3D-MPROM_RL for short) and 3D-MPROM_B with resistive elements (3D-MPROM_B with resistive layer element, referred to as 3D-MPROM_RE ).

本发明的3D-MPROM_B包括：一个含有晶体管的半导体衬底；多个叠置在衬底并与衬底耦合的掩膜编程存储层，每个存储层含有包括第一存储元和第二存储元的多个掩膜编程存储元，每个存储元含有准导通膜，该准导通膜在一个方向上的导电性好于另一方向，所述多个存储元具有N(N＞2)种状态，不同状态下的存储元具有不同的伏-安特性；所述第一存储元的阈值电压在所有状态中最小；所述第二存储元的阈值电压大于所述第一存储元，所述第二存储元比所述第一存储元至少多含有一层电阻膜。The 3D-MPROM_B of the present invention includes: a semiconductor substrate containing transistors; a plurality of mask programming storage layers stacked on the substrate and coupled with the substrate, each storage layer includes a first storage unit and a second storage A plurality of mask programming storage elements of the unit, each storage unit contains a quasi-conducting film, and the conductivity of the quasi-conducting film in one direction is better than that in the other direction, and the plurality of storage units have N (N>2 ) states, the memory cells in different states have different volt-ampere characteristics; the threshold voltage of the first memory cell is the smallest among all states; the threshold voltage of the second memory cell is greater than that of the first memory cell, The second memory cell contains at least one more layer of resistive film than the first memory cell.

本发明的3D-MPROM_B还包括：一个含有晶体管的半导体衬底；多个叠置在衬底并与衬底耦合的掩膜编程存储层，每个存储层含有包括第一存储元和第二存储元的多个掩膜编程存储元，每个存储元含有准导通膜，该准导通膜在一个方向上的导电性好于另一方向，所述多个存储元具有N(N＞2)种状态，不同状态下的存储元具有不同的伏-安特性；所述第一存储元的阈值电压在所有状态中最小；所述第二存储元的阈值电压大于所述第一存储元，所述第二存储元的准导通膜比所述第一存储元的准导通膜含有更高的电阻元素浓度。The 3D-MPROM_B of the present invention also includes: a semiconductor substrate containing transistors; a plurality of mask programming storage layers stacked on the substrate and coupled with the substrate, each storage layer contains a first storage element and a second storage element. A plurality of mask-programmed memory cells for memory cells, each memory cell containing a quasi-conductive film having better conductivity in one direction than the other, the plurality of memory cells having N (N> 2) Two states, the memory cells in different states have different volt-ampere characteristics; the threshold voltage of the first memory cell is the smallest among all states; the threshold voltage of the second memory cell is greater than that of the first memory cell , the quasi-conducting film of the second memory cell contains a higher resistance element concentration than the quasi-conducting film of the first memory cell.

附图说明Description of drawings

图1是表示一种3D-MPROM的断面图；Fig. 1 is a sectional view showing a kind of 3D-MPROM;

图2A-图2D是表示以往技术中‘1’3D-MPROM元、‘0’3D-MPROM元、结形状型N进制3D-MPROM元、结特性型N进制3D-MPROM元的断面图；Figures 2A-2D are cross-sectional views showing '1' 3D-MPROM elements, '0' 3D-MPROM elements, junction shape N-ary 3D-MPROM elements, and junction characteristic type N-ary 3D-MPROM elements in the prior art ;

图3表示一种4位元3D-MPROM_B(b＝4，N＝16)中16种状态的伏-安特性；Fig. 3 represents the volt-ampere characteristic of 16 kinds of states in a kind of 4-bit 3D-MPROM_B (b=4, N=16);

图4A-图4D是表示几种含有电阻膜3D-MPROM_B(3D-MPROM_RL)元的断面图；Fig. 4A-Fig. 4D are the sectional views showing several kinds of 3D-MPROM_B (3D-MPROM_RL ) elements containing resistive film;

图5比较基元、电阻膜和3D-MPROM_RL元的伏-安曲线；Figure 5 compares the volt-ampere curves of the element, the resistive film and the 3D-MPROM_RL element;

图6A-图6D是表示四种电阻膜的断面图；6A-FIG. 6D are cross-sectional views representing four kinds of resistive films;

图7是表示一种3D-MPROM_RL采用的电阻膜掩膜版的俯视图，以及在工艺流程中电阻膜图形和高低地址线图形的相对位置；Figure 7 is a top view of a resistive film mask used in 3D-MPROM_RL , and the relative positions of the resistive film pattern and the high and low address line patterns in the process flow;

图8A-图8C表示一种3D-MPROM_RL元的工艺流程。该图中的结构是沿图7中AA’线的断面图；8A-8C show a process flow of a 3D-MPROM_RL element. The structure in this figure is a sectional view along the AA' line in Fig. 7;

图9A-图9C是表示三种含有部分电阻膜3D-MPROM_B元的断面图；Fig. 9A-Fig. 9C are the sectional views showing three kinds of 3D-MPROM_B elements containing part of the resistive film;

图10是表示一种含有电阻元素3D-MPROM_B(3D-MPROM_RE)元的断面图；Fig. 10 is a sectional view showing a 3D-MPROM_B (3D-MPROM_RE ) element containing a resistance element;

图11比较硅二极管、SiO_x(x＜2)二极管和SiO₂膜的伏-安曲线；Fig. 11 compares the volt-ampere curve of silicon diode, SiO_x (x＜2) diode and SiO₂ film;

图12A和图12B表示3D-MPROM_RE元的一种工艺流程；12A and 12B represent a process flow of 3D-MPROM_RE element;

图13A-图13C是表示三种2位元3D-MPROM_B(b＝2，N＝4)的断面图；13A-FIG. 13C are sectional views showing three kinds of 2-bit 3D-MPROM_B (b=2, N=4);

图14A是表示一种2位元3D-MPROM_B的电路图；图14B是表示一种读操作时字线和位线电压的时序图；Fig. 14A is a circuit diagram showing a 2-bit 3D-MPROM_B ; Fig. 14B is a timing diagram showing a word line and a bit line voltage during a read operation;

图15A是表示一种4位元3D-MPROM_B(b＝4，N＝16)状态设置的表格；图15B是表示一种4位元3D-MPROM_B的断面图。FIG. 15A is a table showing a state setting of a 4-bit 3D-MPROM_B (b=4, N=16); FIG. 15B is a cross-sectional view showing a 4-bit 3D-MPROM_B.

除图15A以外，本说明书附图未按比例绘制。With the exception of Figure 15A, the drawings of this specification are not drawn to scale.

具体实施方式Detailed ways

本发明提供一种多位元三维掩膜编程存储器(3D-MPROM_B)，其每个存储元能存储多位(如4位)信息。图3是一种4位元3D-MPROM_B(b＝4，N＝16)中16种状态的伏-安曲线410-425。它们与状态‘0’-‘f’一一对应。注意该图的电流轴采用指数刻度。当流过存储元中的电流超过阈值电流(I_T)时，存储元导通，这时存储元上的电压为阈值电压(V_T)。例如，状态‘0’的阈值电压为V_T0；...；状态‘f’的阈值电压为V_Tf。本说明书采用以下规范：具有较小V_T的存储元被赋予较小的状态值，如具有最小V_T的存储元处于状态‘0’；具有第二小V_T的存储元处于状态‘1’；...。当然，采用其它规范也是可行的。The present invention provides a multi-bit three-dimensional mask programming memory (3D-MPROM_B ), each storage unit of which can store multi-bit (eg 4-bit) information. FIG. 3 is a volt-ampere curve 410-425 of 16 states in a 4-bit 3D-MPROM_B (b=4, N=16). They correspond to states '0'-'f' one by one. Note that the current axis of the graph is on an exponential scale. When the current flowing through the storage element exceeds the threshold current (_IT ), the storage element is turned on, and the voltage on the storage element is the threshold voltage (V_T ). For example, the threshold voltage of state '0' is V_T0 ; ...; the threshold voltage of state 'f' is V_Tf . This specification adopts the following specification: the storage element with the smaller V_T is assigned a smaller state value, such as the storage element with the smallest V_T is in state '0'; the storage element with the second smallest V_T is in state '1';…. Of course, it is also feasible to adopt other specifications.

为了容忍工艺变化和读出误差，相邻状态V_T的间隔ΔV_T一般需要～0.3V或更大，因此V_T窗口-即最大V_T(V_Tf)和最小V_T(V_T0)之差-一般需要～4.5V或更大。为了实现这么大的V_T窗口，本发明提出在存储元中增加电阻膜和/或电阻元素。相应地，3D-MPROMB可以分为含有电阻膜的3D-MPROM_B(3D-MPROM_RL)和含有电阻元素的3D-MPROM_B(3D-MPROM_RE)。To tolerate process variations and readout errors, the separation ΔV_T between adjacent states V_T generally needs to be ~0.3V or greater, so the V_T window—that is, the difference between the maximum V_T (V_Tf ) and the minimum V_T (V_T0 ) - Typically ~4.5V or greater is required. In order to realize such a large V_T window, the present invention proposes adding a resistive film and/or a resistive element in the storage element. Correspondingly, 3D-MPROMB can be divided into 3D-MPROM_B (3D-MPROM_RL ) containing a resistive film and 3D-MPROM_B (3D-MPROM_RE ) containing a resistive element.

3D-MPROM_RL的例子见图4A-图9C。其中，图4A-图4D描述了多种3D-MPROM_RL元。如图4A所示，该存储元是一个基元1za。基元1za在所有状态中具有最小的V_T-V_T0。它含有多层膜，包括高地址线20z、ROM膜3z和低地址线30a。这些膜一起被称为基膜。其中，地址线20z、30a含有导体材料，如高掺杂的多晶硅(poly Si)、钨(W)、钛钨合金(TiW)、氮化钛(TiN)、铜(Cu)等。ROM膜3z只含有准导通膜25。准导通膜25具有非线性电阻特性，它在一个方向上的导电性好于另一方向。准导通膜25一般采用二极管。这里，它是一个p-i-n二极管，并含有p膜22、i膜24和n膜26。有关准导通膜的细节可参考中国专利ZL98119572.5。Examples of 3D-MPROM_RL are shown in Figures 4A-9C. Among them, FIG. 4A-FIG. 4D describe various 3D-MPROM_RL elements. As shown in FIG. 4A, the storage element is a primitive 1za. Primitive 1za has the smallest V_T −V_T0 among all states. It contains a multi-layer film includingupper address line 20z,ROM film 3z andlower address line 30a. Together these membranes are called basement membranes. Wherein, theaddress lines 20z, 30a contain conductive materials, such as highly doped polysilicon (poly Si), tungsten (W), titanium-tungsten alloy (TiW), titanium nitride (TiN), copper (Cu) and the like. TheROM film 3z includes only thequasi-conducting film 25 . Thequasi-conducting film 25 has a non-linear resistance characteristic, and it conducts electricity better in one direction than in the other direction. Thequasi-conducting film 25 generally adopts a diode. Here, it is a pin diode, and includesp film 22 ,i film 24 andn film 26 . For details about the quasi-conducting film, please refer to Chinese patent ZL98119572.5.

图4B描述了第一种3D-MPROM_RL元1ea。它含有高地址线20e、ROM膜3e和低地址线30a。地址线20e、30a含有导体材料。ROM膜3e除了准导通膜25(包括p膜22、i膜24和n膜26)以外，还含有一层电阻膜23。在该实施例中，电阻膜23位于准导通膜25之上。在I_T时，电阻膜23的电阻最好接近或大于准导通膜25的电阻。由于基元1za除地址线20z、30a外只含有准导通膜25，因此电阻膜23的电阻最好接近或大于基元1za的电阻。Figure 4B depicts the first 3D-MPROM_RL element 1ea. It containsupper address line 20e,ROM film 3e andlower address line 30a.Address lines 20e, 30a contain conductive material. TheROM film 3e includes aresistive film 23 in addition to a quasi-conducting film 25 (includinga p film 22, ani film 24, and an n film 26). In this embodiment, theresistive film 23 is located on thequasi-conducting film 25 . At_IT , the resistance of theresistive film 23 is preferably close to or greater than that of thequasi-conducting film 25. Since the cell 1za only includes thequasi-conducting film 25 except for theaddress lines 20z and 30a, the resistance of theresistive film 23 is preferably close to or greater than that of the cell 1za.

图4C描述了第二种3D-MPROM_RL元1fa。它含有高地址线20f、ROM膜3f和低地址线30a。地址线20f、30a含有导体材料。ROM膜3f除了准导通膜25(包括p膜22、i膜24和n膜26)以外，还含有一层电阻膜23。在该实施例中，电阻膜23位于准导通膜25之中，即位于最高层的p膜22和中间的i膜24之间。类似地，在I_T时，电阻膜23的电阻最好接近或大于基元1za的电阻。FIG. 4C depicts the second 3D-MPROM_RL element 1fa. It contains upper address line 20f, ROM film 3f andlower address line 30a.Address lines 20f, 30a contain conductive material. The ROM film 3f includes aresistive film 23 in addition to the quasi-conducting film 25 (including thep film 22, thei film 24, and the n film 26). In this embodiment, theresistive film 23 is located in thequasi-conducting film 25 , that is, between the p-film 22 on the highest layer and the i-film 24 in the middle. Similarly, at_IT , the resistance of theresistive film 23 is preferably close to or greater than that of the cell 1za.

图4D描述了第三种3D-MPROM_RL元1ga。它含有高地址线20g、ROM膜3g和低地址线30a。地址线20g、30a含有导体材料。ROM膜3g除了准导通膜25(包括p膜22、i膜24和n膜26)以外，还含有一层电阻膜23。在该实施例中，电阻膜23位于准导通膜25之下。类似地，在I_T时，电阻膜23的电阻最好接近或大于基元1za的电阻。Figure 4D depicts the third 3D-MPROM_RL element 1ga. It contains anupper address line 20g, aROM film 3g and alower address line 30a. Theaddress lines 20g, 30a contain conductive material. TheROM film 3g includes aresistive film 23 in addition to the quasi-conducting film 25 (including thep film 22, thei film 24, and the n film 26). In this embodiment, theresistive film 23 is located under thequasi-conducting film 25 . Similarly, at_IT , the resistance of theresistive film 23 is preferably close to or greater than that of the cell 1za.

为了形成三维结构(即多个存储层能相互叠置)，在同一存储层上的3D-MPROM_RL元(1ea/1fa/1ga。这里，“/”表示“或”)和基元1za需要为上面的存储层提供一个良好的基础。也就是说，它们的高地址线(20e/20f/20g、20z)最好可以被平面化(如采用化学机械抛光法，即CMP方法)。这需要电阻膜23的厚度T_R满足以下要求：1)在图4C和图4D的实施例中，如果ROM膜(3f/3g、3z)还需要被平面化，T_R应该小于基元1za中准导通膜25最高层膜22的厚度T_U；2)在图4B-图4D的实施例中，如果ROM膜(3e/3f/3g、3z)不需要被平面化，则T_R应该小于基元1za中高地址线20z的厚度T_A。In order to form a three-dimensional structure (that is, multiple storage layers can be stacked on top of each other), the 3D-MPROM_RL element (1ea/1fa/1ga. Here, "/" means "or") and the primitive 1za on the same storage layer need to be The storage layer above provides a good foundation. That is to say, their high address lines (20e/20f/20g, 20z) can preferably be planarized (such as by chemical mechanical polishing, that is, CMP method). This requires the thickness_TR of theresistive film 23 to meet the following requirements: 1) in the embodiment of Fig. 4C and Fig. 4D, if the ROM film (3f/3g, 3z) also needs to be planarized,_TR should be smaller than that in the unit 1za The thickness T_U ofquasi-conducting film 25_uppermostlayer film 22; 2) in the embodiment of Fig. 4B-Fig. Thickness T_A ofupper address line 20z in cell 1za.

图5比较了基元1za、电阻膜23和3D-MPROM_RL元1ea的伏-安曲线。它们分别以430、431和432表示。由于在3D-MPROM_RL元1ea中，电阻膜23和准导通膜25串联在一起，因此3D-MPROM_RL元1ea的伏-安曲线432是由准导通膜25(也就是基元1za)的伏-安曲线430偏移而成，偏移量由电阻膜23的伏-安曲线431决定：在I_T时，3D-MPROM_RL元1ea的V_T是基元1za的V_T0与电阻膜23上的电压V_r之和，即V_T＝V_T0+V_r。FIG. 5 compares the voltage-ampere curves of the element 1za, theresistive film 23 and the 3D-MPROM_RL element 1ea. These are indicated at 430, 431 and 432, respectively. Since in the 3D-MPROM_RL element 1ea, theresistive film 23 and thequasi-conducting film 25 are connected in series, the voltage-ampere curve 432 of the 3D-MPROM_RL element 1ea is determined by the quasi-conducting film 25 (that is, the element 1za) TheV-A curve 430 of the 3D-MPROM RL is offset by theV-A curve 431 of the resistive film 23: at_IT , the V_T of the 3D-MPROM_RL element 1ea is equal to the V_T0 of the element 1za and the resistive film The sum of the voltages V_r on 23, that is, V_T =V_T0 +V_r .

图6A-图6D是四种电阻膜的断面图。其中，图6A中的电阻膜23只含有一层核心电阻膜502。该核心电阻膜502具有图5所示的指数型伏-安特性。它含有一层半导体膜，和/或一个薄的介质膜。半导体材料可以是硅(Si)、碳(C)、锗(Ge)、碳硅化合物(SiC)、锗硅化合物(SiGe)等；它最好具有非单晶结构，如无定形结构、微晶结构或多晶结构。半导体膜的一个例子是45nm的非定形硅，它可以将存储元V_T偏移～4.5V或更多。介质膜可以是氧化硅(SiO₂)、氮化硅(Si₃N₄)或其它保护性陶瓷材料(参见中国专利ZL98119257.2)。虽然介质膜传统上被认为是绝缘膜，但当其厚度很薄时，它具有指数型伏-安特性。因此，介质膜适合用于电阻膜。介质膜的例子包括5nm的氧化硅、或9nm的氮化硅，这些介质膜都可以将V_T偏移～4.5V或更多。6A-6D are cross-sectional views of four kinds of resistive films. Wherein, theresistive film 23 in FIG. 6A only includes a coreresistive film 502 . The coreresistive film 502 has an exponential volt-ampere characteristic as shown in FIG. 5 . It consists of a semiconductor film, and/or a thin dielectric film. The semiconductor material can be silicon (Si), carbon (C), germanium (Ge), carbon silicon compound (SiC), germanium silicon compound (SiGe), etc.; it preferably has a non-single crystal structure, such as amorphous structure, microcrystalline structure or polycrystalline structure. An example of a semiconductor film is 45nm amorphous silicon, which can shift memory cell_VT by ~4.5V or more. The dielectric film can be silicon oxide (SiO₂ ), silicon nitride (Si₃ N₄ ) or other protective ceramic materials (see Chinese patent ZL98119257.2). Although a dielectric film is traditionally considered an insulating film, it exhibits exponential volt-ampere characteristics when its thickness is very thin. Therefore, dielectric films are suitable for resistive films. Examples of dielectric films include 5nm silicon oxide, or 9nm silicon nitride, both of which can shift_VT by ~4.5V or more.

图6B-图6D描述了其它三种电阻膜23。在图6B中，核心电阻膜502上方含有一层隔离膜501；在图6C中，核心电阻膜502下方含有一层隔离膜503；在图6D中，核心电阻膜502上下方各含有一层隔离膜501、503。隔离膜为电阻膜23提供一个更好的界面，它还可以作为刻蚀停止膜。一般说来，隔离膜含有导体材料，如高掺杂的多晶硅(poly Si)、钨(W)、钛钨合金(TiW)、氮化钛(TiN)、铜(Cu)等。6B-6D describe other three kinds ofresistive films 23 . In FIG. 6B, a layer ofisolation film 501 is contained above thecore resistance film 502; in FIG. 6C, a layer ofisolation film 503 is contained below thecore resistance film 502; in FIG. Membrane 501,503. The isolation film provides a better interface to theresistive film 23, and it also acts as an etch stop film. Generally speaking, the isolation film contains conductive materials, such as highly doped polysilicon (poly Si), tungsten (W), titanium-tungsten alloy (TiW), titanium nitride (TiN), copper (Cu), etc.

图7是表示一种用于3D-MPROM_RL的电阻膜掩膜版的俯视图，以及在工艺流程中电阻膜图形7x、7y和高地址线图形20a、20b、20e及低地址线图形30a、30b的相对位置。相对于高地址线图形的特征尺寸1F，电阻膜图形的特征尺寸可以更大，为nF(n＞1，最好～2)。而且，相邻的电阻膜图形(如7ab、7bb)还可以合并在一起以形成一个电阻膜图形7y。因此，电阻膜掩膜版是一个nF掩膜版(n＞1，最好～2)。例如，20nm节点的3D-MPROM_RL可以采用40nm节点的电阻膜掩膜版。Fig. 7 is a top view showing a resistive film mask plate for 3D-MPROM_RL , andresistive film patterns 7x, 7y and highaddress line patterns 20a, 20b, 20e and lowaddress line patterns 30a, 30b in the process flow relative position. Compared with the characteristic dimension 1F of the high address line pattern, the characteristic dimension of the resistive film pattern can be larger, which is nF (n>1, preferably ~2). Moreover, adjacent resistive film patterns (such as 7ab, 7bb) can also be merged together to form a resistive film pattern 7y. Therefore, the resistive film mask is an nF mask (n>1, preferably ~2). For example, a 3D-MPROM_RL at a 20nm node can use a resistive film mask at a 40nm node.

图8A-图8C表示一种3D-MPROM_RL元1ea的工艺流程。它包括如下步骤：A)形成低地址线30a，然后淀积准导通膜25，并将其刻蚀成为多个柱体25(图8A)；B)淀积并平面化层内介质27。之后，淀积电阻膜23并利用图7中的电阻膜掩膜版进行图形转换，然后刻蚀电阻膜23。注意到电阻膜23的尺寸为nF(n＞1，最好～2)(图8B)；C)淀积高地址线膜20e(图8C)并将其刻蚀。该刻蚀步骤以层内介质27作为刻蚀停止膜，以清除部分电阻膜23。因此，在最后的存储元结构中，电阻膜23与高地址线20e自对准(图4B)。对于熟悉本专业的人士来说，图4C和图4D中的3D-MPROM_RL元1fa、1ga也可以采用类似步骤完成。8A-8C show a process flow of a 3D-MPROM_RL element 1ea. It includes the following steps: A) forming thelower address line 30a, then depositing aquasi-conducting film 25, and etching it into a plurality of pillars 25 (FIG. 8A); B) depositing and planarizing anintralayer dielectric 27. Afterwards,resistive film 23 is deposited and patterned using the resistive film mask shown in FIG. 7 , and thenresistive film 23 is etched. Note that the size of theresistive film 23 is nF (n>1, preferably ~2) (FIG. 8B); C) Deposit the highaddress line film 20e (FIG. 8C) and etch it. In this etching step, theintralayer dielectric 27 is used as an etching stop film to remove part of theresistive film 23 . Therefore, in the final memory cell structure, theresistive film 23 is self-aligned with theupper address line 20e (FIG. 4B). For those familiar with this field, the 3D-MPROM_RL elements 1fa and 1ga in Fig. 4C and Fig. 4D can also be completed by using similar steps.

根据以上对工艺流程的描述，电阻膜23的最后形状由电阻膜图形7x和高地址线图形20e的重叠部分决定。这个自对准的工艺流程对电阻膜图形的边缘精度要求较低。也就是说，20nm节点的3D-MPROM_RL不仅可以采用40nm节点的电阻膜掩膜版(图7)，而且该掩膜版还可以是一个非高精度的掩膜版。因此，3D-MPROM_RL的掩膜版成本能被极大地降低。最后，由于上述工艺流程对高地址线和电阻膜之间的对准精度要求较低，所以3D-MPROM_RL的光刻工艺成本也相对较低。According to the above description of the process flow, the final shape of theresistive film 23 is determined by the overlapping portion of theresistive film pattern 7x and the highaddress line pattern 20e. This self-aligned process has lower requirements on the edge precision of the resistive film pattern. In other words, the 3D-MPROM_RL at the 20nm node can not only use a resistive film mask at the 40nm node (Figure 7), but the mask can also be a non-high-precision mask. Therefore, the mask cost of 3D-MPROM_RL can be greatly reduced. Finally, since the above-mentioned process flow requires less alignment accuracy between the high address line and the resistive film, the photolithography process cost of 3D-MPROM_RL is also relatively low.

3D-MPROM_RL可以与结形状型N进制3D-MPROM(参见中国专利申请200610100860.8)结合，即通过改变电阻膜的形状来实现更多种的状态。相应地，本发明还提出一种含有部分电阻膜的3D-MPROM(3D-MPROM_B with partialresistive layer，简称为3D-MPROM_PRL)。图9A-图9C描述了三种3D-MPROM_PRL元。3D-MPROM_RL can be combined with junction-shaped N-ary 3D-MPROM (see Chinese patent application 200610100860.8), that is, more states can be realized by changing the shape of the resistive film. Correspondingly, the present invention also proposes a 3D-MPROM with a partial resistive layer (3D-MPROM_B with partial resistive layer, 3D-MPROM_PRL for short). Figures 9A-9C describe three 3D-MPROM_PRL elements.

如图9A所示，3D-MPROM_PRL元1ha含有高地址线20h、ROM膜3h和低地址线30a。其中，ROM膜3h含有阻挡介质膜29、部分电阻膜23’和准导通膜25。阻挡介质膜29和部分电阻膜23’位于准导通膜25上方。高地址线20h通过部分电阻膜23’仅与准导通膜25部分耦合。由于部分电阻膜23’与图4B中的电阻膜23具有不同形状-部分电阻膜23’比电阻膜23小，因此存储元1ha的电阻比图4B中存储元1ea的电阻大。具体说来，部分电阻膜23’和准导通膜25之间的接触面积21小于准导通膜25的截面积，而图4B中电阻膜23和准导通膜25之间的接触面积和准导通膜25的截面积接近。通过改变接触面21的宽度f，可以导致不同的电阻，从而形成更多种的状态。由于f由电阻膜图形决定，因此一个电阻膜掩膜版就可以将多位信息录入至每个存储元。类似地，在I_T时，部分电阻膜23’的电阻最好接近或大于基元1za的电阻。很明显，中国专利申请200610100860.8中的各种发明精神均可以应用至3D-MPROM_PRL。As shown in FIG. 9A, the 3D-MPROM_PRL cell 1ha contains anupper address line 20h, aROM film 3h and alower address line 30a. Among them, theROM film 3h includes a blockingdielectric film 29 , apartial resistance film 23 ′ and aquasi-conducting film 25 . The blockingdielectric film 29 and part of theresistive film 23 ′ are located above thequasi-conducting film 25 . Thehigh address line 20h is only partially coupled to thequasi-conducting film 25 through a part of the resistive film 23'. Since the partial resistive film 23' has a different shape than theresistive film 23 in FIG. 4B - the partial resistive film 23' is smaller than theresistive film 23, the resistance of the memory cell 1ha is greater than that of the memory cell 1ea in FIG. 4B. Specifically, thecontact area 21 between the partial resistance film 23' and thequasi-conducting film 25 is smaller than the cross-sectional area of thequasi-conducting film 25, while the contact area between theresistive film 23 and thequasi-conducting film 25 and The cross-sectional area of thequasi-conducting film 25 is close to . By changing the width f of thecontact surface 21 , different resistances can be caused, thereby forming more kinds of states. Since f is determined by the pattern of the resistive film, a resistive film mask can record multiple bits of information into each memory element. Similarly, at_IT , the resistance of the partial resistive film 23' is preferably close to or greater than the resistance of the element 1za. Apparently, various inventive spirits in Chinese patent application 200610100860.8 can be applied to 3D-MPROM_PRL .

图9B和图9C描述了另外两种3D-MPROM_PRL元1ia、1ja。它们类似于图9A中3D-MPROM_PRL元1ha。唯一的差别是其部分电阻膜23’的位置：在图9B中部分电阻膜23’位于准导通膜25中；在图9C中部分电阻膜23’位于准导通膜25下。类似地，通过改变f的数值，可以导致不同的电阻，从而形成更多种的状态。这样，一个电阻膜掩膜版就可以将多位信息录入至每个存储元。Figure 9B and Figure 9C describe two other 3D-MPROM_PRL elements 1ia, 1ja. They are similar to 3D-MPROM_PRL element 1ha in Fig. 9A. The only difference is the position of part of the resistive film 23': part of the resistive film 23' is located in thequasi-conducting film 25 in FIG. 9B; part of the resistive film 23' is located under thequasi-conducting film 25 in FIG. 9C. Similarly, by changing the value of f, different resistances can be caused, thus forming more kinds of states. In this way, a resistive film mask can record multiple bits of information into each memory cell.

在一个含有电阻元素的3D-MPROM_B(3D-MPROM_RE)中，3D-MPROM_RE元的准导通膜比基元的准导通膜含有更高的电阻元素浓度。图10-图12B描述了多种3D-MPROM_RE。如图10所示，3D-MPROM_RE元1ka含有高地址线20k、ROM膜3k和低地址线30a。其中，ROM膜3k含有准导通膜25’。与其左边的基元1za比较，3D-MPROM_RE元1ka的准导通膜25’与基元1za的准导通膜25具有类似结构，即均为p-i-n二极管。但是，准导通膜25’比准导通膜25含有更高的电阻元素浓度。在与基元1za中准导通膜25(如p-i-n二极管)的半导体材料(如硅)结合后，电阻元素(如氧、氮、碳等)能增大该半导体材料的电阻率，而且电阻元素的浓度增加导致电阻率增加。这与半导体材料中常用的掺杂元素(如硼、磷、砷)不同：这些掺杂元素降低半导体的电阻率，而且掺杂元素的浓度增加导致电阻率降低。In a 3D-MPROM_B (3D-MPROM_RE ) containing resistive elements, the quasi-conducting film of the 3D-MPROM_RE element contains a higher concentration of resistive elements than the quasi-conducting film of the elementary element. Figures 10-12B describe various 3D-MPROM_REs . As shown in FIG. 10, the 3D-MPROM_RE element 1ka includes anupper address line 20k, aROM film 3k, and alower address line 30a. Among them, theROM film 3k includes a quasi-conduction film 25'. Compared with the unit 1za on the left, thequasi-conducting film 25 ′ of the 3D-MPROM_RE unit 1ka has a similar structure to thequasi-conducting film 25 of the unit 1za, that is, both are pin diodes. However, thequasi-conducting film 25 ′ contains a higher resistance element concentration than thequasi-conducting film 25 . After combining with the semiconductor material (such as silicon) of the quasi-conducting film 25 (such as pin diode) in the unit 1za, the resistance element (such as oxygen, nitrogen, carbon, etc.) can increase the resistivity of the semiconductor material, and the resistance element An increase in the concentration leads to an increase in resistivity. This is different from the doping elements commonly used in semiconductor materials (such as boron, phosphorus, arsenic): these doping elements reduce the resistivity of the semiconductor, and the increase in the concentration of the doping elements leads to a decrease in the resistivity.

图11比较了硅二极管(即基元)、SiO_x(x＜2)二极管(即3D-MPROM_RE元)和SiO₂膜的伏-安曲线。它们分别以440、441和442表示。很明显，SiO_x(x＜2)二极管的伏-安曲线441应位于硅二极管伏-安曲线440和SiO₂膜伏-安曲线442之间。这是因为SiO₂是SiO_x(x＜2)的一种极端情况：当SiO_x(x＜2)中氧的含量高到一定程度时，SiO_x就变成了SiO₂。因此，SiO_x(x＜2)二极管的V_T应介于硅二极管的V_T0和SiO₂膜的V_Tx之间，即V_T0＜V_T＜V_Tx。由于V_Tx数值极大，3D-MPROM_RE元的V_T可以在极大范围内调节。与氧类似，氮也可以在极大范围内调节3D-MPROM_RE元的V_T。另外，碳也可以用来调节V_T。这是因为碳能与硅形成SiC_z(z＜1)。SiC_z作为一种半导体材料，其能带隙(bandgap)比硅宽。一般说来，二极管中半导体材料的能带隙越宽，该二极管的V_T越高。Figure 11 compares the volt-ampere curves of silicon diodes (ie primitives),_SiOx (x<2) diodes (ie 3D-MPROM_RE elements) and SiO₂ films. These are indicated at 440, 441 and 442, respectively. Obviously, theV-A curve 441 of the SiO_x (x<2) diode should lie between theV-A curve 440 of the silicon diode and theV-A curve 442 of the SiO₂ film. This is because SiO₂ is an extreme case of SiO_x (x<2): when the content of oxygen in SiO_x (x<2) is high enough, SiO_x becomes SiO₂ . Therefore, the V_T of the SiO_x (x<2) diode should be between the V_T0 of the silicon diode and the V_Tx of the SiO₂ film, that is, V_T0 <V_T <V_Tx . Due to the extremely large value of V_Tx , the V_T of the 3D-MPROM_RE element can be adjusted within a large range. Similar to oxygen, nitrogen can also regulate the V_T of 3D-MPROM_RE elements in an extremely large range. Alternatively, carbon can also be used to tune V_T . This is because carbon can form_SiCz (z<1) with silicon. As a semiconductor material, SiC_z has a wider bandgap than silicon. In general, the wider the bandgap of the semiconductor material in a diode, the higher the_VT of that diode.

图12A和图12B表示3D-MPROM_RE元1ka的一种工艺流程。首先形成低地址线30a和准导通膜25。然后通过一个电阻元素掩膜版在光刻胶28中形成开口28o。电阻元素掩膜版与电阻膜掩膜版类似，都是nF掩膜版(n＞1，最好～2)。这里，开口28o的宽度为nF(n＞1，最好～2)，比高地址线20k的宽度(～F)大。接着通过离子注入法在准导通膜25中注入电阻元素(如氧、氮、碳等)(图12A)。该离子注入步骤能增加开口28o下电阻元素的浓度。之后，清除光刻胶28并将准导通膜25刻蚀成柱体25’(图12B)。余下的步骤与基元1za类似(参见图8B和图8C)。与3D-MPROM_RL类似，20nm节点的3D-MPROM_RE不仅可以采用40nm节点的电阻元素掩膜版，而且该掩膜版还可以是一个非高精度的掩膜版。综上所述，3D-MPROM_B的信息录入成本远比大多数人想象的要低。12A and 12B show a process flow of 3D-MPROM_RE element 1ka. First, thelower address line 30a and thequasi-conduction film 25 are formed. Openings 28o are then formed in thephotoresist 28 through a resistive element mask. The resistive element mask is similar to the resistive film mask, both of which are nF masks (n>1, preferably ~2). Here, the width of the opening 28o is nF (n>1, preferably ~2), which is larger than the width (~F) of theupper address line 20k. Next, resistive elements (such as oxygen, nitrogen, carbon, etc.) are implanted into thequasi-conducting film 25 by ion implantation (FIG. 12A). This ion implantation step can increase the concentration of the resistive element under the opening 28o. Afterwards, thephotoresist 28 is removed and thequasi-conducting film 25 is etched into pillars 25' (FIG. 12B). The remaining steps are similar to primitive 1za (see Figure 8B and Figure 8C). Similar to 3D-MPROM_RL , 3D-MPROM_RE at 20nm node can not only use a resistive element mask at 40nm node, but the mask can also be a non-high-precision mask. To sum up, the information entry cost of 3D-MPROM_B is far lower than most people imagine.

3D-MPROM_RL(图4B-图4D、图9A-图9C)、3D-MPROM_RE(图10)可以和结形状型N进制3D-MPROM、结特性型N进制3D-MPROM(参见中国专利申请200610100860.8)结合起来，进一步提高每个存储元存储的信息量。图13A-图14B描述多种2位元3D-MPROM_B(b＝2，N＝4)；图15A和图15B描述一种4位元3D-MPROM_B(b＝4，N＝16)。3D-MPROM_RL (Figure 4B-Figure 4D, Figure 9A-Figure 9C), 3D-MPROM_RE (Figure 10) can be combined with junction shape type N-ary 3D-MPROM, junction characteristic type N-ary 3D-MPROM (see China Patent application 200610100860.8) combined to further increase the amount of information stored in each storage element. 13A-14B describe various 2-bit 3D-MPROM_B (b=2, N=4); FIG. 15A and FIG. 15B describe a 4-bit 3D-MPROM_B (b=4, N=16).

图13A-图13C描述三种2位元3D-MPROM_B。如图13A所示，该实施例结合了图4B中的3D-MPROM_RL和图10中的3D-MPROM_RE。这四个存储元1za、1ma、1na、1oa代表四种状态。基元1za不含任何电阻膜或电阻元素。存储元1ma的准导通膜25’至少含有一种电阻元素。存储元1na在准导通膜25上含有一层电阻膜23。存储元1oa含有电阻元素和电阻膜。另外，存储元1ma可以与基元1za具有不同的掺杂浓度。很明显，该实施例只需要2个掩膜版(即电阻膜掩膜版和电阻元素掩膜版)就能将2位信息录入至每个存储元。13A-13C describe three kinds of 2-bit 3D-MPROM_B . As shown in FIG. 13A , this embodiment combines the 3D-MPROM_RL in FIG. 4B and the 3D-MPROM_RE in FIG. 10 . These four storage elements 1za, 1ma, 1na, and 1oa represent four states. Element 1za does not contain any resistive film or resistive elements. The quasi-conducting film 25' of the memory cell 1ma contains at least one resistance element. The memory cell 1na includes aresistive film 23 on aquasi-conductive film 25 . The memory cell 1oa includes a resistive element and a resistive film. In addition, the memory cell 1ma may have a different doping concentration than the cell 1za. Obviously, in this embodiment, only two masks (namely, a resistive film mask and a resistive element mask) are needed to record 2-bit information into each storage element.

图13B表示第二种2位元3D-MPROM_B。它采用了图4B中3D-MPROM_RL的两种实施例。这四个存储元1za、1pa、1qa、1ra代表四种状态。例如，存储元1pa的电阻膜23a含有15nm非定形硅，存储元1qa的电阻膜23b含有30nm非定形硅，存储元1ra含有电阻膜23a和23b，即45nm非定形硅。又如，存储元1pa的电阻膜23a含有3nm氮化硅，存储元1qa的电阻膜23b含有6nm氮化硅，存储元1ra则含有9nm氮化形硅。类似地，该实施例只需要2个电阻膜掩膜版就能将2位信息录入至每个存储元。FIG. 13B shows the second type of 2-bit 3D-MPROM_B . It adopts two embodiments of 3D-MPROM_RL in Fig. 4B. These four storage elements 1za, 1pa, 1qa, and 1ra represent four states. For example, theresistive film 23a of memory cell 1pa contains 15nm amorphous silicon, theresistive film 23b of memory cell 1qa contains 30nm amorphous silicon, and the memory cell 1ra containsresistive films 23a and 23b, that is, 45nm amorphous silicon. For another example, theresistive film 23a of the memory cell 1pa contains 3nm silicon nitride, theresistive film 23b of the memory cell 1qa contains 6nm silicon nitride, and the memory cell 1ra contains 9nm silicon nitride. Similarly, this embodiment only needs 2 resistive film masks to record 2-bit information into each memory cell.

图13C表示第三种2位元3D-MPROM_B。它结合了图4B和图4D中3D-MPROM_RL的两种实施例。这四个存储元1za、1sa、1ta、1ua代表四种状态。存储元1sa的电阻膜23c位于准导通膜25上方，存储元1ta的电阻膜23d位于准导通膜25下方，存储元1ua含有两层电阻膜23c和23d，它们分别位于准导通膜25上方和下方。该实施例也只需要2个电阻膜掩膜版就能将2位信息录入至每个存储元。FIG. 13C shows the third type of 2-bit 3D-MPROM_B . It combines two embodiments of 3D-MPROM_RL in Fig. 4B and Fig. 4D. The four storage elements 1za, 1sa, 1ta, and 1ua represent four states. Theresistance film 23c of the storage element 1sa is located above thequasi-conducting film 25, theresistance film 23d of the storage element 1ta is located below thequasi-conducting film 25, and the storage element 1ua includes two layers ofresistance films 23c and 23d, which are respectively located on thequasi-conducting film 25. above and below. In this embodiment, only two resistive film masks are needed to record 2-bit information into each storage element.

在对3D-MPROM_B进行读操作时，需要提供一系列逐步增大的读电压信号。一旦读电压大到能在一存储元中产生读电流，则产生一输出信号，这时的读电压对应于该存储元所处的状态。图14A和图14B描述了一种2位元3D-MPROM_B的读电路和读操作。When performing a read operation on the 3D-MPROM_B , it is necessary to provide a series of gradually increasing read voltage signals. Once the read voltage is large enough to generate a read current in a memory element, an output signal is generated, and the read voltage at this time corresponds to the state of the memory element. 14A and 14B describe a read circuit and read operation of a 2-bit 3D-MPROM_B.

如图14A所示，该2位元3D-MPROM_B包括两部分：存储堆0和周边电路0K。存储堆0包括数据组30DT(包括数据元1ca-1cz、数据位线30a-30z)和哑元组32DY(包括哑元1c0-1c3、哑位线32a-32d)。数据元存储数据，而哑元为读操作提供参考信号。数据元和哑元都具有4种状态‘0’-‘3’。例如，数据元1ca和哑元1c1都处于状态‘1’。该图中括号里的数字表示存储元所处的状态。在该实施例中，处于相同状态的哑元和数据元具有相同结构并采用相同材料。这样哑元不会导致额外的生产成本，因此能降低3D-MPROM_B的成本。As shown in FIG. 14A, the 2-bit 3D-MPROM_B includes two parts:bank 0 and peripheral circuit OK.Stack 0 includes a data group 30DT (including data elements 1ca-1cz, data bitlines 30a-30z) and a dummy group 32DY (including dummy elements 1c0-1c3, anddummy bit lines 32a-32d). Data elements store data, while dummy elements provide reference signals for read operations. Both the data element and the dummy element have 4 states '0'-'3'. For example, data element 1ca and dummy element 1c1 are both in state '1'. The numbers in parentheses in the figure indicate the state of the storage element. In this embodiment, dummy elements and data elements in the same state have the same structure and use the same material. Such dummy elements will not cause additional production costs, thus reducing the cost of 3D-MPROM_B.

周边电路0K形成在衬底0s里，并通过接触通道孔与存储堆0耦合。它含有字线电压产生电路50、行译码器52、列译码器54、参考信号产生电路56、读出放大器58、数据缓冲器60和N进制-二进制转换器62等。字线电压产生电路50在不同读阶段产生不同的读电压。行译码器52根据行地址52A将该读电压送到相应的字线(如20c)。列译码器54根据列地址54A将相应的位线与读出放大器58的第一输入51耦合。参考信号产生电路56为读出放大器58产生参考电压53。它含有多个开关对(如56a’)，每个开关对含有一对共享栅信号(如56a)的晶体管。The peripheral circuit OK is formed in the substrate 0s, and is coupled with thememory stack 0 through a contact via hole. It contains word linevoltage generating circuit 50,row decoder 52,column decoder 54, referencesignal generating circuit 56,sense amplifier 58,data buffer 60 and n-ary-binary converter 62, etc. The word linevoltage generation circuit 50 generates different read voltages in different read phases. Therow decoder 52 sends the read voltage to the corresponding word line (such as 20c) according to therow address 52A.Column decoder 54 couples the corresponding bit line tofirst input 51 ofsense amplifier 58 according to column address 54A. Referencesignal generating circuit 56 generatesreference voltage 53 forsense amplifier 58 . It contains a plurality of switch pairs (such as 56a'), each switch pair contains a pair of transistors that share a gate signal (such as 56a).

图14B表示一种读操作时字线和位线电压的时序图。每个读操作需要含有N-1个读阶段。该实施例含有3个读阶段：T0-T2。在每个读阶段，在选中的字线(如20c)上加相应的读电压。根据存储元(1ca-1cz、1c0-1c3)所处的状态，不同存储元流过不同的读电流，这样与其耦合的位线上(30a-30z、32a-32d)的电压也以不同速率上升。当每个读阶段快结束时，数据组30DT中所有数据位线(30a-30z)上的电压被一一读出。如果位线(如30a)电压大于触发电压V_x，则输出55变高。同时，读出放大器58将相应位线(30a)在剩余读操作中设置为高电压V_H，这样能避免剩余读操作中的读电压损坏相应存储元(1ca)中的二极管。以下介绍各个读阶段的细节：Figure 14B shows a timing diagram of word line and bit line voltages during a read operation. Each read operation needs to contain N-1 read phases. This embodiment contains 3 read phases: T0-T2. In each read phase, a corresponding read voltage is applied to the selected word line (eg, 20c). According to the states of the memory cells (1ca-1cz, 1c0-1c3), different memory cells flow different read currents, so the voltages on the bit lines (30a-30z, 32a-32d) coupled with them also rise at different rates . Towards the end of each read phase, the voltages on all the data bit lines (30a-30z) in the data set 30DT are read out one by one. If the bit line (eg 30a) voltage is greater than the trigger voltage_Vx , theoutput 55 goes high. At the same time, thesense amplifier 58 sets the corresponding bit line (30a) to a high voltage_VH during the remaining read operations, which can prevent the read voltage from damaging the diode in the corresponding memory cell (1ca) during the remaining read operations. The details of each reading stage are introduced as follows:

A)在第一读阶段T0中，在字线20c上加第一读电压V_R0。这时，位线(30a-30z、32a-32d)电压根据存储元状态以不同速率上升。对于状态‘0’(如存储元1ca、1c0)来说，读电压V_R0产生一大读电流，因此位线(30a、32a)电压上升很快；对于状态‘1’(如存储元1cz、1c1)来说，读电压V_R0产生小读电流，因此位线(30z、32b)电压上升很慢；...。同时，参考信号产生电路56中仅栅信号56a被置高，开关对56a’闭合，这样哑位线32a、32b耦合在一起。因此，参考电压53是状态‘0’和状态‘1’位线电压的平均。当T0快结束时，读出放大器58将数据组30DT中所有数据位线(30a-30z)上的电压与参考电压53一一比较，输出55被送到数据缓冲器60。A) In the first read phase T0, a first read voltage V_R0 is applied to theword line 20c. At this time, the bit line (30a-30z, 32a-32d) voltage rises at different rates depending on the state of the memory cell. For state '0' (such as memory cell 1ca, 1c0), read voltage V_R0 produces a large read current, so the voltage of bit line (30a, 32a) rises very quickly; for state '1' (such as memory cell 1cz, 1c1), the read voltage V_R0 produces a small read current, so the voltage of the bit lines (30z, 32b) rises very slowly;  …. At the same time, only thegate signal 56a in the referencesignal generating circuit 56 is set high, and theswitch pair 56a' is closed, so that thedummy bit lines 32a and 32b are coupled together. Thus,reference voltage 53 is the average of the state '0' and state '1' bit line voltages. When T0 is about to end, thesense amplifier 58 compares the voltages on all data bit lines (30a-30z) in the data set 30DT with thereference voltage 53 one by one, and theoutput 55 is sent to thedata buffer 60.

B)在第二读阶段T1中，在字线20c上加第二读电压V_R1。对于状态‘0’(如存储元1ca、1c0)来说，位线(30a、32a)在T0时已被设置为V_H；对于状态‘1’(如存储元1cz、1c1)来说，读电压V_R1产生一大读电流，因此位线(30z、32b)电压上升很快；对于状态‘2’(如存储元1cb、1c2)来说，读电压V_R1产生小读电流，因此位线(30b、32c)电压上升很慢；...。同时，参考信号产生电路56中仅栅信号56b被置高，开关对56b’闭合，这样哑位线32b、32c耦合在一起。因此，参考电压53是状态‘1’和状态‘2’位线电压的平均。当T1快结束时，数据组30DT中所有数据位线(30a-30z)上的电压被一一读出，输出55被送到数据缓冲器60。B) In the second read phase T1, a second read voltage V_R1 is applied to theword line 20c. For state '0' (such as memory cells 1ca, 1c0), bit lines (30a, 32a) have been set to V_H at T0; for state '1' (such as memory cells 1cz, 1c1), read Voltage V_R1 produces a large read current, so the voltage of the bit lines (30z, 32b) rises quickly; for state '2' (such as memory cells 1cb, 1c2), the read voltage V_R1 produces a small read current, so the bit line (30b, 32c) The voltage rises very slowly;  …. At the same time, only thegate signal 56b in the referencesignal generating circuit 56 is set high, and theswitch pair 56b' is closed, so that thedummy bit lines 32b and 32c are coupled together. Thus, thereference voltage 53 is the average of the state '1' and state '2' bit line voltages. When T1 is about to end, the voltages on all the data bit lines (30a-30z) in the data set 30DT are read out one by one, and theoutput 55 is sent to thedata buffer 60.

C)在第三读阶段T2中，在字线20c上加第三读电压V_R2。对于状态‘0’和‘1’(如存储元1ca、1c0；1cz、1c1)来说，位线(30a、32a；30z、32b)在T0和T1时已被设置为V_H；对于状态‘2’(如存储元1cb、1c2)来说，读电压V_R2产生一大读电流，因此位线(30b、32c)电压上升很快；...。同时，参考信号产生电路56中仅栅信号56c被置高，开关对56c’闭合，这样哑位线32c、32d耦合在一起。因此，参考电压53是状态‘2’和状态‘3’位线电压的平均。当T2快结束时，数据组30DT中所有数据位线(30a-30z)上的电压被一一读出，输出55被送到数据缓冲器60。C) In the third read phase T2, a third read voltage V_R2 is applied to theword line 20c. For states '0' and '1' (eg memory cells 1ca, 1c0; 1cz, 1c1), bit lines (30a, 32a; 30z, 32b) have been set to_VH at T0 and T1; for states '2' (such as memory cells 1cb, 1c2), the read voltage V_R2 generates a large read current, so the voltage of the bit lines (30b, 32c) rises quickly;  …. At the same time, only thegate signal 56c in the referencesignal generating circuit 56 is set high, and theswitch pair 56c' is closed, so that thedummy bit lines 32c and 32d are coupled together. Thus,reference voltage 53 is the average of the state '2' and state '3' bit line voltages. When T2 is about to end, the voltages on all the data bit lines (30a-30z) in the data set 30DT are read out one by one, and theoutput 55 is sent to thedata buffer 60.

D)在读操作结束时，存储在数据缓冲器60中的数据被N进制-2进制转换器62转换成二进制数据。这样，存储在存储元1ca-1cz中的4进制数据被读出。D) At the end of the read operation, the data stored in thedata buffer 60 is converted into binary data by the n-ary-binary converter 62 . Thus, the 4-ary data stored in the memory cells 1ca-1cz are read out.

图15A和图15B描述一种4位元3D-MPROM_B。图15A中的表格列出了其16种状态的设置；图15B是其断面图。对于熟悉本专业的人士来说，图14A和图14B中的读电路和读操作都可以应用到4位元3D-MPROM_B中。15A and 15B describe a 4-bit 3D-MPROM_B . The table in Figure 15A lists the settings of its 16 states; Figure 15B is its cross-sectional view. For those familiar with this field, the read circuit and read operation in Fig. 14A and Fig. 14B can be applied to 4-bit 3D-MPROM_B.

如图15A所示，为了实现4位元，存储元可以在4维上变化：高电阻膜23x、中电阻膜23y、低电阻膜23z和电阻元素。表中的“是”表示采用电阻膜或电阻元素；“否”表示不采用。由于每维有两种选择(“是”和“否”)，该实施例共有16种状态。这4维可以通过4个掩膜版来实现，即高电阻膜掩膜版、中电阻膜掩膜版、低电阻膜掩膜版和电阻元素掩膜版。As shown in FIG. 15A, in order to realize 4 bits, memory cells can be varied in 4 dimensions:high resistance film 23x, medium resistance film 23y, low resistance film 23z and resistance elements. "Yes" in the table means to use resistive film or resistive element; "No" means not to use. Since there are two choices for each dimension ("Yes" and "No"), this embodiment has a total of 16 states. These 4 dimensions can be realized by 4 masks, namely high resistance film mask, medium resistance film mask, low resistance film mask and resistive element mask.

如图15B所示，该4位元3D-MPROM_B含有一个半导体衬底0s和一个3D-MPROM_B堆0。该半导体衬底0s含有多个晶体管0T(包括栅极0P)。这些晶体管0T及其互连层0I一起构成3D-MPROM_B堆0的周边电路0X。3D-MPROM_B堆0叠置在衬底0s上。在该实施例中，它含有4个存储层100-400：存储层100含有字线(80a-80h...)、位线(90d...)和存储元(1ad-1hd...)；存储层200叠置与存储层100之上，并含有字线(80a-80h...)、位线(90d^*...)和存储元(1ad^*...)；存储层300叠置与存储层200之上，并含有字线(80a’-80h’...)、位线(90d’...)和存储元(1a’d’-1h’d’...)；存储层400叠置与存储层300之上，并含有字线(80a’-80h’...)、位线(90d”...)和存储元(1a’d”...)。接触通道孔(如90dv)将存储层(如100)与衬底0s耦合。As shown in FIG. 15B, the 4-bit 3D-MPROM_B includes a semiconductor substrate 0s and a 3D-MPROM_B stack 0. The semiconductor substrate Os includes a plurality of transistors OT (including gates OP). These transistors 0T and their interconnection layer 0I together constitute the peripheral circuit 0X of the 3D-MPROM_B- stack 0. The 3D-MPROM_B stack 0 is stacked on the substrate 0s. In this embodiment it contains 4 memory layers 100-400:memory layer 100 contains word lines (80a-80h...), bit lines (90d...) and memory cells (1ad-1hd...) ; Thestorage layer 200 is stacked on thestorage layer 100, and contains word lines (80a-80h...), bit lines (90d^* ...) and storage elements (1ad^* ...); the storage layer 300 is stacked placed on thestorage layer 200, and contains word lines (80a'-80h'...), bit lines (90d'...) and memory cells (1a'd'-1h'd'...); The memory layer 400 is stacked on the memory layer 300 and includes word lines (80a'-80h'...), bit lines (90d"...) and memory cells (1a'd"...). Contact via holes (eg 90dv) couple the storage layer (eg 100) to the substrate 0s.

在存储层100、300中的存储元1ad-1hd、1a’d’-1h’d’分别代表状态‘0’-‘f’(参考图15A)。例如，存储元1ad代表状态‘0’，它是一个基元，即不含有任何电阻膜或电阻元素；存储元1bd代表状态‘1’，其二极管25’含有电阻元素；存储元1cd代表状态‘2’，它含有低电阻膜23z；存储元1ed代表状态‘4’，它含有中电阻膜23y；存储元1a’d’代表状态‘8’，它含有高电阻膜23x；存储元1h’d’代表状态‘f’，它含有高电阻膜23x、中电阻膜23y、低电阻膜23z和电阻元素；...。为简便计，存储层200、400中的存储元细节以及存储层200-400的接触通道孔没有画出。The storage cells 1ad-1hd, 1a'd'-1h'd' in the storage layers 100, 300 respectively represent states '0'-'f' (refer to FIG. 15A ). For example, storage unit 1ad represents state '0', which is a primitive, that is, does not contain any resistance film or resistance element; storage unit 1bd represents state '1', and its diode 25' contains resistance element; storage unit 1cd represents state' 2', it contains low-resistance film 23z; memory unit 1ed represents state '4', and it contains medium-resistance film 23y; memory unit 1a'd' represents state '8', and it contains high-resistance film 23x; memory unit 1h'd ' represents state 'f' which containshigh resistance film 23x, medium resistance film 23y, low resistance film 23z and resistance elements; . . . For simplicity, details of memory cells inmemory layers 200, 400 and contact via holes of memory layers 200-400 are not shown.

图15B中的实施例结合了多种改进的3D-MPROM，如混合层3D-MPROM(参见中国专利申请200610162698.2)和窄线宽3D-MPROM(参见中国专利申请200810183936.7)。混合层3D-MPROM中部分存储层(如100、200)共享地址线(80a-80h...)；其它存储层(如200、300)则不共享地址线，而由层间介质膜121隔开。窄线宽3D-MPROM中存储层地址线的特征尺寸小于衬底晶体管栅极的特征尺寸。进一步结合三维存储模块(参见中国专利申请200710194280.4)，一个采用20nm技术的x8x8x4 3D-MPROM模块可以存储～1TB信息。这里，x8x8x4是指该模块含有8个3D-MPROM_B芯片，每个3D-MPROM_B芯片含有8个存储层，每个存储元存储4位信息。The embodiment in FIG. 15B combines various improved 3D-MPROMs, such as mixed layer 3D-MPROM (see Chinese patent application 200610162698.2) and narrow linewidth 3D-MPROM (see Chinese patent application 200810183936.7). Some storage layers (such as 100, 200) in the hybrid layer 3D-MPROM share address lines (80a-80h...); other storage layers (such as 200, 300) do not share address lines, but are separated by interlayer dielectric films open. The characteristic size of the storage layer address line in the narrow line width 3D-MPROM is smaller than the characteristic size of the gate of the substrate transistor. Further combined with a three-dimensional memory module (see Chinese patent application 200710194280.4), a x8x8x4 3D-MPROM module using 20nm technology can store ~1TB of information. Here, x8x8x4 means that the module contains 8 3D-MPROM_B chips, each 3D-MPROM_B chip contains 8 storage layers, and eachstorage element stores 4 bits of information.

在图13A-图13C中，只需要2个掩膜版就能将2位信息录入至每个存储元，即实现2位元；在图15A和图15B中，只需要4个掩膜版就能将4位信息录入至每个存储元，即实现4位元。实际上，在3D-MPROM_B中，每个掩膜版能在存储元中多录入1位信息。譬如，5个掩膜版可以实现5位元，6个掩膜版可以实现6位元...。如果采用图9A-图9C中3D-MPROM_PRL，掩膜版的数目还可以进一步减少。这比在以往技术的二进制3D-MPROM中，每多录入1位信息就需要多叠置一个存储层来说，节省了很多生产成本。In Figure 13A-Figure 13C, only 2 masks are needed to record 2 bits of information into each storage element, that is, 2 bits are realized; in Figure 15A and Figure 15B, only 4 masks are needed 4 bits of information can be entered into each storage element, that is, 4 bits are realized. In fact, in 3D-MPROM_B , each mask can record 1 more bit of information in the storage element. For example, 5 masks can realize 5 bits, and 6 masks can realize 6 bits.  … If the 3D-MPROM_PRL shown in FIG. 9A-FIG. 9C is used, the number of masks can be further reduced. This saves a lot of production cost compared to the binary 3D-MPROM of the prior technology, which requires an additional storage layer to be stacked for every additional bit of information entered.

虽然以上说明书具体描述了本发明的一些实例，熟悉本专业的技术人员应该了解，在不远离本发明的精神和范围的前提下，可以对本发明的形式和细节进行改动，这并不妨碍它们应用本发明的精神。因此，除了根据附加的权利要求书的精神，本发明不应受到任何限制。Although the above description has specifically described some examples of the present invention, those skilled in the art should understand that the form and details of the present invention can be changed without departing from the spirit and scope of the present invention, which does not hinder their application. spirit of the invention. The invention, therefore, should not be restricted except in accordance with the spirit of the appended claims.

Claims (10)

1. multidigit unit three-dimensional masking film program storer is characterized in that containing:

One contains transistorized Semiconductor substrate (0s);

A plurality of masking film program accumulation layers (100-400) that are stacked in substrate and are coupled with substrate, each accumulation layer contains a plurality of masking film program storage elements that comprise first storage element (1za) and second storage element (1ea...), each storage element contains accurate conductive membrane (25), this accurate conductive membrane good conductivity in one direction is in other direction, described a plurality of storage element has N (N＞2) kind state, and the storage element under the different conditions has different volt-ampere characteristics;

The threshold voltage of described first storage element is minimum in all states; The threshold voltage of described second storage element is greater than described first storage element, and described second storage element at least than described first storage element more and contained one deck resistive film (23).

2. multidigit according to claim 1 unit three-dimensional masking film program storer, its feature also is: when threshold current, the resistance of described resistive film near or greater than the resistance of described first storage element.

3. the first three-dimensional masking film program storer of multidigit according to claim 1, its feature also is: described resistive film contains one deck semiconductor film or at least one layer dielectric at least.

4. the first three-dimensional masking film program storer of multidigit according to claim 1, its feature also is:

Described resistive film thickness is less than the thickness of the high address line of described first storage element; Or,

Described resistive film thickness is less than the thickness of top film in the accurate conductive membrane of described first storage element.

5. the first three-dimensional masking film program storer of multidigit according to claim 1, its feature also is:

Contain the 3rd storage element, the threshold voltage of described the 3rd storage element is greater than described first storage element, and described the 3rd storage element at least than described first storage element more and contained one deck resistive film;

The resistive film of described second storage element and described the 3rd storage element has difformity.

6. the first three-dimensional masking film program storer of multidigit according to claim 1, its feature also is:

Contain the 3rd storage element, the threshold voltage of described the 3rd storage element is greater than described first storage element, and described the 3rd storage element at least than described first storage element more and contained one deck resistive film;

Contain the 4th storage element, the threshold voltage of described the 4th storage element is greater than the described second and the 3rd storage element, and described the 4th storage element contains described second and the resistive film of the 3rd storage element.

7. multidigit unit three-dimensional masking film program storer is characterized in that containing:

One contains transistorized Semiconductor substrate (0s);

A plurality of masking film program accumulation layers (100-400) that are stacked in substrate and are coupled with substrate, each accumulation layer contains a plurality of masking film program storage elements that comprise first storage element (1za) and second storage element (1ka), each storage element contains accurate conductive membrane, this accurate conductive membrane good conductivity in one direction is in other direction, described a plurality of storage element has N (N＞2) kind state, and the storage element under the different conditions has different volt-ampere characteristics;

The threshold voltage of described first storage element is minimum in all states; The threshold voltage of described second storage element is greater than described first storage element, and the accurate conductive membrane (25 ') of described second storage element contains higher resistance concentration of element than the accurate conductive membrane (25) of described first storage element.

8. the first three-dimensional masking film program storer of multidigit according to claim 7, its feature also is: described resistance element can increase the resistivity of accurate conductive membrane semiconductor material in described first storage element.

9. the first three-dimensional masking film program storer of multidigit according to claim 7, its feature also is: described resistance element can increase the band gap of accurate conductive membrane semiconductor material in described first storage element.

10. the first three-dimensional masking film program storer of multidigit according to claim 7, its feature also is: contain the 3rd storage element, the threshold voltage of described the 3rd storage element is greater than described first storage element, and described the 3rd storage element at least than described first storage element more and contained one deck resistive film (23).

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