CN102214614B - chip package - Google Patents

Abstract

The invention discloses a chip packaging body, comprising: the chip is provided with a plurality of conductive pads and is arranged around the chip; and the sealing ring comprises a plurality of metal strips which are arranged in the space range surrounded by the two adjacent conducting pads, and each metal strip is not electrically connected with the two adjacent conducting pads at the same time.

Description

Chip packing-body

Technical field

The present invention relates to chip packing-body, particularly a kind of seal ring structure of chip packing-body.

Background technology

Industry has developed a kind of wafer-class encapsulation technology for the encapsulation of chip at present, after the wafer-class encapsulation body is completed, need to carry out cutting step between each chip, to separate each chip, in order to reduce the fracture extension that produces in the cutting step probability to the chip, between each chip, sealing ring need be set, to improve the reliability of chip packing-body.In addition, the area that sealing ring such as occupying volume are outer, the tube core sum on wafer may reduce.

Summary of the invention

The object of the present invention is to provide a kind of core packaging body, to address the above problem.

For reaching above-mentioned purpose, embodiments of the invention provide a kind of chip packing-body, comprising: chip, have a plurality of conductive pads, and be arranged at around chip; And sealing ring, comprise a plurality of metal strip things, be arranged in two spatial dimensions of enclosing in abutting connection with conductive pad, and each metal strip thing is not electrically connected with the conductive pad of two adjacency simultaneously.

For allow above-mentioned purpose of the present invention, feature, and advantage can become apparent, below coordinate accompanying drawing, be described in detail below:

Description of drawings

Fig. 1 is the vertical view according to the seal ring structure region of the chip packing-body of the embodiment of the present invention;

Fig. 2 A is the enlarged diagram at Fig. 1center line 3B place;

Fig. 2 B is the partial structurtes stereogram according to the seal ring structure of the embodiment of the present invention;

Fig. 3 A is the vertical view according to the seal ring structure of the embodiment of the present invention;

Fig. 3 B is the vertical view according to the seal ring structure of another embodiment of the present invention; And

Fig. 4 A-Fig. 4 F is the generalized section according to each processing step of the making chip packing-body of the embodiment of the present invention.

Description of reference numerals

30～chip;

36～connecting portion;

32～sealing ring;

34～conductive pad;

40,41,43,45,401-408～metal strip thing;

41a～external series gap;

45a～internal clearance;

The width of w～conductive pad;

The spacing of d～external series gap and internal clearance;

42～guide hole;

44～stress barricade;

341,342, the metal level of 343～conductive pad;

411,412, the metal level of 413～metal strip thing;

361,362, the metal level of 363～connecting portion;

100～wafer substrate;

The wafer substrates of 100 '～thinning;

102～conductive pad;

104～dielectric layer;

106～wall;

107～hole;

109～recess;

110～microlens array;

112 insulating barriers;

114～conductor layer;

116～protective layer;

118～conductive projection;

200～encapsulated layer;

C～Cutting Road;

Bending channel between S～two metal strip things.

Embodiment

Below with embodiment and coordinate accompanying drawing to describe the present invention in detail, in accompanying drawing or specification were described, similar or identical part was used identical figure number.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.Moreover in accompanying drawing, the part of each element will be it should be noted that the element that does not illustrate in figure or describe to describe explanation, be form known to a person of ordinary skill in the art in affiliated technical field.In addition, the ad hoc fashion that specific embodiment only uses for disclosing the present invention, it is not to limit the present invention.

The present invention makes the embodiment of image sensing element packaging body (image sensor package) as an illustration.Yet, scrutablely be, in the embodiment of chip packing-body of the present invention, it can be applicable to the various electronic components (electroniccomponents) that comprise active element or the integrated circuits such as passive component (active or passive elements), digital circuit or analogous circuit (digital or analog circuits), for example relates to photoelectric cell (opto electronic devices), MEMS (micro electro mechanical system) (Micro Electro Mechanical System; MEMS), microfluid system (micro fluidicsystems) or the physical sensors (PhysicalSensor) that utilizes the physical quantitys such as heat, light and pressure to change to measure.But choice for use wafer-class encapsulation (wafer scale package particularly; WSP) technique is to Image Sensor, light-emitting diode (light-emitting diodes; LEDs), the semiconductor chips such as solar cell (solarcells), radio-frequency (RF) component (RF circuits), accelerometer (accelerators), gyroscope (gyroscopes), little brake (micro actuators), surface acoustic wave element (surface acoustic wave devices), pressure sensor (process sensors) or ink gun (ink printer heads) encapsulate.

Wherein above-mentioned wafer-class encapsulation technique mainly refers to after wafer stage is completed encapsulation step, cut into again independently packaging body, yet, in a particular embodiment, the semiconductor chip redistribution that for example will separate is on bearing wafer, carry out again packaging technology, also can be referred to as wafer-class encapsulation technique.In addition, above-mentioned wafer-class encapsulation technique also is applicable to have by stacking (stack) mode arrangement the multi-disc wafer of integrated circuit, to form the chip packing-body of multilevel integration (multi-layer integrated circuit devices).

Fig. 1 is for showing the vertical view according to the sealing ring region of the chip packing-body of embodiments of the invention, around eachchip 30 by sealingring 32 around, be Cutting Road c between two sealing rings 32.Fig. 2 A is the amplification plan view at Fig. 1center line 3B place, finds out that by knowing in Fig. 2 A a plurality of conductive pads arrange around chip, and 32 of sealing rings comprise two in abutting connection with the metal strip thing 40 between conductive pad 34.In an embodiment, metal strip thing 40 integral body can be positioned at the spatial dimension of enclosing in abutting connection withconductive pad 34 by two, and therefore, the seal ring structure of the present embodiment can utilize the space betweenconductive pad 34 itself and two adjacent conductive pads to complete.In another embodiment, width assealing ring 32 is no more than two width in abutting connection withconductive pad 34, and the width between twoadjacent sealing rings 32 such as need are about 80 μ m, also 80 μ m only of required Cutting Road width c, with the wafer of 8 inches, therefore the tube core sum can increase.In addition, the design of the seal ring structure of the present embodiment can also be applicable to chip on board encapsulation (chip on board is called for short COB) and wafer-level package (chip scale package is called for short CSP) technique.

In an embodiment,conductive pad 34 can be for extending contact pad, and it utilizes the joint sheet on connectingportion 36 and chip to be electrically connected, and does not need retaining space that inner seal ring is set between extension contact pad and joint sheet, therefore can further dwindle the area of chip.

In an embodiment, the width w ofconductive pad 34 for example is about 50 μ m, and the width of metal strip thing 40 for example is about 10 μ m, therefore as shown in Fig. 2 A, 3metal strip things 41 parallel to each other, 43 and 45 can be set between conductive pad 34.In addition, in another embodiment, also can arrange more than 3 betweenconductive pad 34 or following metal strip thing, looking closely actual demand and decide.It should be noted that, eachmetal strip thing 41,43 and 45 two ends can be not simultaneously be electrically connected with adjacent twoconductive pads 34, that is has at least a gap, it is between the conductive pad at each metal strip thing and two ends, to avoid short circuit, wherein, at least one external series gap is positioned at the outside of two conductive pad enclosed spaces; And at least one internal clearance is positioned at the inboard of two conductive pad enclosed spaces.For example, compriseexternal series gap 41a between themetal strip thing 41 of chip exterior such as Cutting Road c andconductive pad 34, compriseinternal clearance 45a between themetal strip thing 45 ofchip 30 inside and conductive pad 34.In another embodiment,external series gap 41a andinternal clearance 45a can form bending channel, it is greater than the rectilineal interval d of thisexternal series gap 41a andinternal clearance 45a, that is, can the stress that cutting step produces must just can be entered along two metal strip things as the bending channel between 41,43 or 43,45 bymetal strip thing 41,43 and/or 45, avoid above-mentioned stress directly to pass internal clearance and form the crack that extends to chip internal from external series gap.

Then, see also Fig. 2 B, it shows the partial structurtes stereogram ofsealing ring 32, in this embodiment,conductive pad 34 has three-layer metal layer 341,342 and 343, and extends to fromconductive pad 34 connectingportion 36 that is electrically connected with joint sheet (not drawing) and also have three-layer metal layer 361,362 and 363.In this embodiment, conductive pad is electrically connected with three-layer metal layer and joint sheet, yet, in another embodiment, also can only utilize the layer of metal layer to be connected to joint sheet, themetal level 362 in the middle of for example utilizing is connected to joint sheet.In an embodiment, have a plurality ofguide holes 42 between the three-layer metal layer 341 of conductive pad 34,342 and 343, to be electrically connected each metal level, the position ofguide hole 42 does not limit, and the crack ofguide hole 42 all right stop portions, avoid it to extend to chip internal simultaneously.

In an embodiment, eachmetal strip thing 41,43 and 45 between twoconductive pads 34 also can have the three-layer metal layer, as shown in Fig. 2 B,metal strip thing 41 has three-layer metal layer 411,412 and 413, and have a plurality ofguide holes 42 between each metal level 411,412 and 413, to be electrically connected each metal level, the position ofguide hole 42 can arrange arbitrarily.In an embodiment, because the metal level of the metal level that can select conductive pad on technique and metal strip thing forms simultaneously, therefore, the number of plies of the number of plies of the metal level of conductive pad and the metal level of metal strip thing can be identical.It should be noted that, in an embodiment, have at least astress barricade 44 between themetal level 411 of metal strip thing 41,412 and 413, thisstress barricade 44 is except the structure of reinforcedseal ring 32 more, more can effectively stop the crack, avoid it to extend to chip internal.In another embodiment, at least has a stress barricade between eachmetal strip thing 41,43 and 45 metal level, that ismetal strip thing 41,43 and 45 all has the stress barricade separately, as shown in Fig. 2 B, gap between this stress barricade and conductive pad can arrange according to the described mode of above-mentioned Fig. 2 A, so that the stress that cutting step produces must enter along the extension passage between two stress barricades, avoid above-mentioned stress directly to pass internal clearance and form the crack that extends to chip internal from external series gap.

In the seal ring structure of the present embodiment, the set-up mode of the metal strip thing 40 betweenconductive pad 34 can have many kinds of kenels, and Fig. 2 A is depicted as wherein a kind of kenel.In addition, Fig. 3 A to Fig. 3 B shows other two kinds of kenels, see also Fig. 3 A, in an embodiment, have twometal strip things 401 and 403 parallel to each other betweenconductive pad 34,metal strip thing 401 is connected withconductive pad 34 with an end of being connected, the other end and keep the gap between conductive pad,metal strip thing 401 and 403 andconductive pad 34 between the gap be staggered, the stress that cutting step produces must be entered along the extension passage S between twometal strip things 401 and 403, can avoid the crack directly to extend to chip internal.

Then, see also Fig. 3 B, in this embodiment, have three metal strip things 405,407 and 408 betweenconductive pad 34,metal strip thing 405 and 407 wherein is located along the same line, its rectilinear direction of arranging is perpendicular toconductive pad 34, andmetal strip thing 405 is connected withconductive pad 34 with an end of being connected, and has the gap betweenmetal strip thing 405 and 407.408 of another metal strip things are arranged in parallel with 405,407, and the two ends ofmetal strip thing 408 all keep the gap with conductive pad 34.It should be noted that these gaps in Fig. 3 B also are staggered.

Although only enumerate the arrangement mode of several metal strip things in specification of the present invention, yet, be understandable that, metal strip thing between conductive pad can also have other kinds arrangement mode, as long as these metal strip things can not make and produce short circuit between conductive pad, and it is each other staggered arrangement and gets final product with gap or the gap between each metal strip thing between two conductive pads.

Fig. 4 A-Fig. 4 F is the generalized section of demonstration according to each processing step of the making chip packing-body of the embodiment of the present invention, and these profiles show the section along Fig. 2 A center line X-X ', and therefore it can not show metal strip thing 40 on the position of conductive pad 34.See also Fig. 4 A, at first, providesubstrate 100, it is for example semiconductor wafer, having a plurality of chip (not shown)s onsemiconductor wafer 100, is for example Image Sensor, and can havecorresponding microlens array 110 as image sensor surface on Image Sensor.Havingdielectric layer 104 in the substrate of semiconductor wafer, is for example silica, and each chip has corresponding conductive pad (conductive pad) 102, is arranged in thisdielectric layer 104.

Then, front withsemiconductor wafer 100, that is surface and encapsulatedlayer 200 with chip are bonding, encapsulated layer is as the bearing structure of encapsulation, and it can be for example glass, quartz (quartz), opal (opal), plastic cement or other any transparency carrier for the light turnover.It is worth mentioning that, also can optionally form filter (filter) and/or anti-reflecting layer (anti-reflective layer) on encapsulated layer.Wall (spacer) 106 can be set betweenencapsulated layer 200 andsemiconductor wafer 100, make and form gap (cavity) 107 betweensemiconductor wafer 100 andencapsulated layer 200,gap 107 be spaced apart thelayer 106 around.

Above-mentionedwall 106 can be epoxy resin (epoxy), welding resisting layer (solder mask) or other megohmite insulant that is fit to, the for example silicon oxide layer of inorganic material, silicon nitride layer, silicon oxynitride layer, metal oxide or its combination, or the polyimide resin (polyimide of organic high score material; PI), benzocyclobutene (butylcyclobutene; BCB), Parylene (parylene), naphthalene polymer (polynaphthalenes), fluorine carbide (fluorocarbons), acrylate (accrylates) etc., and thiswall 106 can be to utilize coating method, rotary coating (spin coating) for example, spraying (spraycoating) or pouring curtain coating cloth (curtain coating), or other depositional mode that is fit to, for example liquid deposition (liquid phase deposition), physical vapour deposition (PVD) (physical vapor deposition, PVD), chemical vapour deposition (CVD) (chemical vapor deposition, CVD), low-pressure chemical vapor deposition (lowpressure chemical vapor deposition, LPCVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD), rapid heat chemical vapour deposition (rapid thermal-CVD, RTCVD) or aumospheric pressure cvd (atmospheric pressurechemical vapor deposition, APCVD) mode forms, and pollutes or avoids aqueous vapor to invade with isolated environment.

In an embodiment, above-mentioned Image Sensor can be complementary metal oxide semiconductor element (CMOS) or charge coupled cell (charge-couple device; CCD).In addition, above-mentionedconductive pad 102 can be also to extend joint sheet (extension pad), and preferably can be by copper (copper; Cu), aluminium (aluminum; Al) or other suitable metal material made.

Then, see also Fig. 4 B, back side thinning semiconductor wafer fromsemiconductor wafer 100, become the semiconductor wafer 100 ' with predetermined thickness, this thinning technique can be etching (etching), milling (milling), grinding (grinding) or the modes such as (polishing) of grinding.Then, the back side with the semiconductor wafer 100 ' of indentation technique after thinning forms recess (notch) 109.After thisrecess 109 formed, semiconductor wafer 100 ' can be isolated out many semiconductor chips (chip)

See also Fig. 4 C, thedielectric layer 104 ofetching recess 109 bottoms is to the contact surface that exposes conductive pad 102.Then, see also Fig. 4 D, forminsulating barrier 112 with the lateral zones of coveringrecess 109 and the back side ofsemiconductor wafer 100 '.in an embodiment, above-mentionedinsulating barrier 112 can be epoxy resin, welding resisting layer or other megohmite insulant that is fit to, the silicon oxide layer of inorganic material for example, silicon nitride layer, silicon oxynitride layer, metal oxide or its combination, or the polyimide resin of organic high score material, benzocyclobutene, Parylene, the naphthalene polymer, the fluorine carbide, acrylate etc., and thisinsulating barrier 112 can utilize coating method, rotary coating for example, spraying or pouring curtain coating cloth, or other depositional mode that is fit to, for example liquid deposition, physical vapour deposition (PVD), chemical vapour deposition (CVD), low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, the mode of rapid heat chemical vapour deposition or aumospheric pressure cvd forms, with theconductor layer 114 of isolation of semiconductor wafer 100 ' with follow-up formation.

Then,form conductor layer 114 inrecess 109 and on the back side of semiconductor wafer 100 ', can be by being for example physical vaporous deposition (PVD) or sputtering method (sputtering), depositing to compliance is for example copper, aluminium, silver (silver; Ag), nickel (nickel; Ni) or the conductive layer of its alloy inrecess 109 and on the back side of semiconductor wafer 100 ', then by photoengraving carving technology patterned conductive layer, to form conductor layer 114.The Surface Contact ofconductor layer 114 andconductive pad 102 forms the L-type contact, and extends to the terminal contact (not drawing) on the semiconductor wafer 100 ' back side.

Then, see also Fig. 4 E, form protective layer (passivation) 116 onconductor layer 114, cover the back side and the recess of semiconductor wafer 100 ', protective layer is for example soldering-resistance layer (solder mask).Then, see also Fig. 4 F, form conductive projection (conductive bump) 118 and passprotective layer 116 and conductor layer 14 electric connections.In an embodiment; after forming above-mentionedprotective layer 116; thisprotective layer 116 of patterning; to form the opening of exposeportion conductor layer 114; then, the mode by plating or screen painting (screenprinting) fills in scolder (solder) in above-mentioned opening; and carrying out reflow (re-flow) technique, is for example theconductive projection 118 of soldered ball (solder ball) or weld pad (solder paste) to form.Then, cut apart the wafer-class encapsulation body of said chip along Cutting Road (scribe line), to separate each chip, complete chip packing-body of the present invention.

According to the manufacture method of the chip packing-body of the embodiment of the present invention,conductive pad 102 is not etched, andconductive pad 102 only exposes contact-making surface and contacts withconductor layer 114, to form the L-type contact.Therefore, the sealing ring that is comprised of the metal strip thing between conductive pad and conductive pad can not suffer damage in the manufacture process of chip packing-body, can reach the effect of sealing ring.

In sum, seal ring structure of the present invention comprises various embodiment.For example in an embodiment, it is the space that utilizes between conductive pad itself and two conductive pads.In another embodiment, the width of seal ring structure can not surpass the width of conductive pad.Or in another embodiment, sealing ring comprises a plurality of metal strip things, has at least one external series gap and an internal clearance between itself and two adjacent conductive pads, and the bending channel that both form can reduce stress.

Although the present invention has disclosed preferred embodiment as above; so it is not to limit the present invention, any person skilled in the art, without departing from the spirit and scope of the present invention; when can do a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.

Claims (14)

1. chip packing-body comprises:

Chip has a plurality of conductive pads, is arranged at around this chip; And

Sealing ring, it comprises a plurality of metal strip things, be arranged in two spatial dimensions of enclosing in abutting connection with conductive pad and be arranged on two in abutting connection with between conductive pad, and each metal strip thing is not electrically connected with the conductive pad of above-mentioned two adjacency simultaneously.

2. chip packing-body as claimed in claim 1, wherein, described conductive pad has width, and the described metal strip thing width that the is positioned at above-mentioned two adjacent conductive pads spatial dimension of enclosing, and described metal strip thing is arranged in parallel with each other.

3. chip packing-body as claimed in claim 1 or 2, wherein each this metal strip thing at least with one of above-mentioned two adjacent conductive pads gap that is separated by.

4. chip packing-body as claimed in claim 3, wherein, the outside, space that the width of above-mentioned two adjacent conductive pads encloses also comprises the external series gap between described metal strip thing and described conductive pad, and the inboard, space that the width of above-mentioned two adjacent conductive pads encloses also comprises the internal clearance between described metal strip thing and described conductive pad, formed extension passage is bending channel described a plurality of metal strip things from this external series gap to this internal clearance, and this bending channel is greater than the rectilineal interval of this external series gap and this internal clearance.

5. chip packing-body as claimed in claim 3, wherein said gap is Heterogeneous Permutation.

6. chip packing-body as claimed in claim 4, wherein this bending channel comprises along the space between two metal strip things as communicating passage.

7. chip packing-body as claimed in claim 6, wherein this conductive pad comprises the multiple layer metal layer.

8. chip packing-body as claimed in claim 7, comprise that also a plurality of guide holes are arranged between the described metal level of this conductive pad.

9. chip packing-body as claimed in claim 7, wherein this metal strip thing comprises the multiple layer metal layer.

10. chip packing-body as claimed in claim 9, the number of plies of the described metal level of this metal strip thing is identical with the number of plies of the described metal level of this conductive pad.

11. chip packing-body as claimed in claim 9 comprises that also at least one stress dams setting is between the described metal level of this metal strip thing.

12. chip packing-body as claimed in claim 9 wherein has the stress barricade between each metal level of each this metal strip thing.

13. chip packing-body as claimed in claim 3 also comprises:

Encapsulated layer is arranged on this chip, engages with the first surface of this chip;

Conductor layer is arranged in this chip on the second surface with respect to this first surface, extends to the Surface Contact with described conductive pad;

Protective layer is arranged on this conductor layer, has this conductor layer that opening exposes a part; And

Conductive projection is arranged on this opening, is electrically connected with this conductor layer.

14. a chip packing-body comprises:

Chip has a plurality of conductive pads, is arranged at around this chip, and described conductive pad has width; And

Sealing ring, comprise a plurality of metal strip things, be arranged in two spatial dimensions of enclosing in abutting connection with conductive pad and be arranged on two in abutting connection with between conductive pad, and the width of sealing ring is not more than the width of described conductive pad, and each this metal strip thing is not electrically connected with the conductive pad of above-mentioned two adjacency simultaneously; Also comprise the external series gap between described metal strip thing and described conductive pad outside the space that wherein width of above-mentioned two adjacent conductive pads encloses, and the inboard, space that the width of above-mentioned two adjacent conductive pads encloses also comprises the internal clearance between described metal strip thing and described conductive pad, formed extension passage is bending channel described a plurality of metal strip things from this external series gap to this internal clearance, and this bending channel is greater than the rectilineal interval of this external series gap and this internal clearance.

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