CN102129216B - Circuit arrangement and method for reclocking an input signal - Google Patents

Abstract

Translated fromChinese

实施例包括对输入信号重新计时的电路装置和方法。在一个实施例中，电路装置包括数据存储元件，该数据存储元件具有用来接收具有第一时钟速率的数字数据流的数据输入以及接收具有第二时钟速率的时钟信号的时钟输入。数据存储元件还包括逻辑，该逻辑基于时钟信号调整数字数据流中的跳变的边沿时间以产生具有在要求频率及其谐波下含频谱零点的功率谱的经调制输出信号而不会改变平均数据速率。

Embodiments include circuitry and methods for reclocking an input signal. In one embodiment, a circuit arrangement includes a data storage element having a data input for receiving a digital data stream at a first clock rate and a clock input for receiving a clock signal at a second clock rate. The data storage element also includes logic that adjusts the edge timing of transitions in the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at the desired frequency and its harmonics without changing the average data rate.

Description

Be used for the circuit arrangement of input signal reclocking and method

field

The disclosure generally relates to the circuit arrangement of input signal reclocking and method, and the mode from the radiation interference of interchip communication link of relating more specifically to reduce under particular radio-frequency frequency is to the circuit of input signal reclocking and method.

Background technology

Digital signal across the communication link transmission between circuit can give off spectrum energy under a plurality of rf frequencies, and this causes the interference that is sometimes called as electromagnetic interference (EMI) (EMI) with near analog receiver circuit.When this receiver circuit is tuned to particular radio-frequency (RF) channel, the frequency spectrum giving off can may cause the interference in RF channel, this disturbs as random noise or sparkle noise and occurs, these noises may damage the bit error rate of signal to noise ratio (S/N ratio) increase and RF channels associated.Therefore, need to control the spectrum energy of this radiation.

Summary of the invention

The edge time that the embodiment of the circuit arrangement disclosing is herein configured to change saltus step in input traffic be created in output power spectrum require frequency and harmonic wave place thereof have spectral null through modulated output signal.In addition, disclosed for generation of require frequency and harmonic wave place thereof in output power spectrum and there is the embodiment of the method through modulated output signal of spectral null.

accompanying drawing summary

Figure 1A is part block scheme and the partial logic figure that latchs digit data stream and the data of timing are offered to the traditional circuit device of digital I/O pin under a clock rate.

Figure 1B is the curve map of data output power spectrum at the digital I/O pin place of the device of traditional circuit shown in Figure 1A, the spectral null shown in figure under the clock frequency of integral multiple.

Fig. 2 A is the figure of an embodiment that comprises the circuit arrangement of the edge Circuit tuning that is configured to flow to digital data reclocking.

Fig. 2 B is that the data of describing circuit arrangement shown in Fig. 2 A are inputted, data are exported and the sequential chart of clock signal.

Fig. 2 C be illustrated in timing under the first clock rate data-signal the first output power spectrum and at the curve map that uses the second output power spectrum of the data-signal of circuit reclocking under second clock speed shown in Fig. 2 A.

Fig. 3 A illustrates ideal to draw high, drag down pulse and the unbalanced sequential chart of drawing high, drag down pulse.

Fig. 3 B illustrates for Fig. 3 A ideal signal at the figure that requires the spectral null under frequency and requiring the output power spectrum of the spread spectrum under frequency for the unbalanced signal of Fig. 3 A.

Fig. 4 comprises the figure being configured to the second embodiment of the circuit arrangement of the edge Circuit tuning of the data-signal reclocking of reception.

Fig. 5 is the sequential chart that the signal associated with the circuit arrangement of Fig. 4 is shown.

Fig. 6 comprises the figure being configured to the 3rd embodiment of the circuit arrangement of the edge Circuit tuning of the data-signal reclocking of reception.

Fig. 7 is the sequential chart that the signal associated with the circuit arrangement of Fig. 6 is shown.

Fig. 8 is the diagram that comprises the communicator of circuit arrangement, thereby this circuit arrangement has edge Circuit tuning to be used for digital signal reclocking to change selectively the edge sequential of digital signal.

Fig. 9 is the process flow diagram to the method for data-signal reclocking embodiment.

Figure 10 is the process flow diagram to the second embodiment of the method for data-signal reclocking.

describe in detail

Figure 1A is the block scheme that latchs theinput signal 103 of reception and the data of timing are offered to the traditional circuit device 100 of digital I/O pin 110 under a clock frequency.Circuit arrangement 100 comprises signal source 105 and the data storage elements of datainput trigger circuit 102 for example.

Signal source 105 can be data storage device, receiver circuit or other circuit that is configured to produce and provide digit data stream.Signal source 105 offersinput signal 103input 104 ofdata input trigger 102 fromclock source 106 receiveclock signals 109 and with the associated data transfer rate of the clock rate withclock signal 109.

Data input trigger 102 comprisesdata input 104, for receivinginput signal 103 from signal source 105.Data input trigger 102 also comprises that being coupled inclock source 106inputs 107 with the clock of receive clock signal 109.Datainput trigger circuit 102 also comprises the output that is coupled in digital I/O (I/O)pin 110 by data buffer 108.Data input trigger 102 is configured toresponse clock signal 109input signal 103 frominput 104 is moved to digital I/O pin 110 bydata buffer 108.

Numeral I/O pin 110 is bycommunication link 114, to be coupled in conductive lead wire or the solder joint ofdata circuit 112, and describedcommunication link 114 can be electrical lead, raised pad, trace or other conductive electrical communication path.In one embodiment,communication link 114 can comprise a plurality of conductive paths, for example Low Voltage Differential Signal (LVDS) link.

Data circuit 112 can comprise the digital circuit that is configured to process data signal, the signal for example being received by antenna 116 and/or from theinput signal 103 of signal source 105.In one example,data circuit 112 can comprise one or more processors, data storage medium, DLC (digital logic circuit), other circuit or be configured to process its combination in any of numerical data.In addition,data circuit 112 can comprise the one or more interfaces for conveying a message to user and selecting from user there audio reception, video and/or user, for example, by assembly such as loudspeaker, microphone, video camera, keyboard and the display of mobile communication equipment, display can be touch-sensitive formula.

In one embodiment, the rising edge of datainput trigger circuit 102response clock signals 109 moves to the logical value of theinput signal 103 atinput 104 places its output and makes it enter data buffer 108.Signal source 105 anddata trigger 102 be fromclock source 106 receiveclock signals 109, thus with the identical clock rate of the data withoffer data buffer 108 by datainput trigger circuit 102 toinput signal 103 timing.Mobile value is communicated by letter acrosscommunication link 114 with the clock rate ofclock signal 109 as output signal 111.

Output signal 111 oncommunication link 114 is included in the spectral null under clock frequency and harmonic wave thereof, and as used, fourier transform analysis confirms, this spectral null is mainly derived from output signal 111 with the switching of clock rate.Oncommunication link 114 communication output signal 111 in saltus step may give off electromagnetic interference (EMI), this electromagnetic interference (EMI) may affect be coupled in analog receiver circuit 118 near for example reception at antenna 116 places of circuit.This radiation interference (being represented by dotted line 120) may induce electric current at antenna 116, to the electric current (I receiving_rX) extra noise is provided.According to magnetic coupling equation below, this induced noise coupling may induce voltage in associated receiver circuit 18:

Vn=wMI_d(equation 1)

Inequation 1, the voltage of induction (Vn) is the mutual inductance (M) between digital signal frequency (w), antenna 116 andcommunication link 114 and the electric current (I that is associated with output signal 111_d) function.

Figure 1B is the curve map of the data output power spectrum of the output signal 111 described in Figure 1A.Output signal 111 is included under the clock frequency of integral multiple the spectral null 124,126 and 128 of (in clock frequency (1/T) or for example under 2/T, 3/T isochronon frequency harmonics).Due to the frequency zero 124,126,128 in the power spectrum of output signal 111, for example near the receiver circuit of analog receiver circuit 118 will experience very little interference in the rf frequency channel corresponding to clock frequency or clock frequency integral multiple.Yet, when near receiver circuit is tuned to other frequency, may require the position of controlling spectral null with corresponding with the rf frequency requiring.

Although the clock frequency ofadjustable clock signal 109 is with travel frequency zero point, yet the clock rate that changesclock signal 109 changes the data rate ofinput signal 103 equally.Whendata circuit 112 cannot be moved under the data rate of the clock frequency through regulating, this scheme may be useless.For example, be configured to operate under the situation of fixed frequency indata circuit 112, if data rate changes with the spectral null in mobile output signal 111, circuit arrangement 100 anddata circuit 112 possibly cannot proper communications.

Yet, as below with reference to as described in Fig. 2 A-10, for the data rate of optional frequency, can retrain the rising edge of (reclocking) digital output signal and negative edge and introduce spectral null and do not change mean data rate with the respectively requirement frequency place in output power spectrum.

Fig. 2 A is the block scheme of an embodiment of thecircuit arrangement 200 of theedge Circuit tuning 220 that comprises that configuration paired data stream reclocks.Circuit arrangement 200 comprises for example data storage elements of datainput trigger circuit 102, and comprises edge Circuit tuning 220.Datainput trigger circuit 102 receivesinput signal 103 anddigit data stream 209 is offered to the edgeCircuit tuning input 210 ofedge Circuit tuning 220 to be associated with the first clock rate ofclock signal 109.

Edge Circuit tuning 220 comprises that being coupled in edge Circuit tuning inputs the 210 reclocking flip-flop circuits 224 with received digital data stream 209.Edge Circuittuning 220 is also inputted 222 by clock and is coupled insecond clock source 228 to receive thesecond clock signal 229 with second clock speed, and this second clock speed can be different from the clock rate of clock signal 109.The saltus step edge time in reclocking flip-flop circuit 224 changedigit data streams 209, this offereddata circuit 112 through modulatedoutput signal 227 bytelecommunication circuit 114 and data buffer 226,108 to produce through modulated output signal 227.Data buffer 226 can be the data storage elements of flip-flop circuit and so on for example, anddata buffer 226 is bysecond clock signal 229 clocks and synchronously timing of reclocking trigger 224.Introducingdata buffer 226 does not become the problem incircuit arrangement 200 to guarantee metastable state, and otherwise this just may be subject to due to asynchronous clock signal 109,229 impact of some data instabilities.In some cases, for examplesecond clock signal 229 derivation self-clock signals 109 or while not needing data reliability, can savedata buffer 226.

Second clock source 228 can be local oscillator, phase-locked loop circuit or other circuit that is configured to provide second clock signal 229.In one embodiment,second clock source 229 can be the adjustable clock source that controlled circuit (example control circuit 422 as shown in Figure 4) is controlled.In certain embodiments,second clock source 228 can be included in edge Circuit tuning 220.In other embodiments, second clock source 228Ke edge Circuit tuning 220 outsides (as shown in the figure) or even in the outside ofcircuit arrangement 200.

Can controlsecond clock source 220 so that the selected clock period (T that has to be provided₂) thesecond clock signal 229 of clock rate so that interested rf frequency is corresponding to following equation:

F_rF=n/T₂(equation 2)

Inequation 2, for example variable (n) can be integer.Be otherwise noted that because zero point in frequency domain is very wide soequation 2 is not necessarily accurate, and ifequation 2 approximate some significant advantages that just can obtain just.Input traffic 103 first thefirst clock signal 107 based on having the first clock rate passes through 102 timing of data input trigger circuit to producedigit data stream 209, anddigit data stream 209 is used and had second clock speed (1/T by reclocking flip-flop circuit 224₂) 229 reclockings of second clock signal, under the multiple of the second clock frequency of this second clock speed in the power spectrum throughmodulated output signal 227, introduce spectral null and can not change the mean data rate ofdigit data stream 209.

Fig. 2 B is thedigit data stream 109 of describingcircuit 200 shown in Fig. 2 A,clock signal 109,second clock signal 229 and through the sequential chart 230 of modulated output signal 227.Thefirst clock signal 109 has clock period (T₁), andsecond clock signal 229 has clock period (T₂).

As shown in the figure, throughmodulated output signal 227, be the function in the cycle of second clock signal 229.Specifically, paramount from low saltus step at the rising edge of 240 respondingdigital data stream 209 andsecond clock signal 229 through modulated output signal 227.Atdigit data stream 209 from high saltus step to low, throughmodulated output signal 227 242 from high saltus step to low, this saltus step corresponding todigit data stream 209 saltus step after the next rising edge of second clock signal 229.Throughmodulated output signal 227 244 again paramount from low saltus step and 246 from high saltus step to low, these two saltus steps are corresponding to the value ofdigit data stream 209 whensecond clock signal 229 is paramount from low saltus step.Throughmodulated output signal 227, in 248 saltus steps again, this saltus step is corresponding to the value ofdigit data stream 209 and the rising edge ofsecond clock signal 229.

As shown in the figure, through the saltus step edge ofmodulated output signal 227 with respect to the edge translation in digit data stream 109.In addition through the interval, edge ofmodulated output signal 227, with respect to the rising edge indigit data stream 209 and the interval, edge between negative edge, be changed.Yet mean data rate does not change.Specifically, the mean data rate ofdigit data stream 209 is associated with thefirst clock signal 109, and this clock rate remains unchanged.Reclocking flip-flop circuit 224 flows 209 reclockings to digital data, with respect todigit data stream 209, changes the edge time but can not change mean data rate.

Regulate the frequency ofsecond clock signal 229 to change the edge time and to change the interval, edge in modulated output signal 227.Yet, the input data rate ofdigit data stream 209 can be independent of the selected clock frequency of (being asynchronous to)second clock signal 229, thereby can pull-in frequency zero point and can not change the mean data rate ofdigit data stream 209, because the data indigit data stream 209 continue to be associated with the identical speed rates (edge interval time have a small amount of movement) of thefirst clock signal 109.

Fig. 2 C is illustrated in the first output power spectrum of the output signal 111 of timing under the first clock frequency that is associated withclock signal 109 and the curve map that uses the output power spectrum of the change throughmodulated output signal 227 ofsecond clock signal 229 reclockings shown in Fig. 2 A.As described with reference to Figure 1B above, if data are communicated under the first clock frequency, the signal obtaining will be corresponding to clock frequency (1/T₁) 124,126 and 128 places of multiple comprise spectral null.

Yet, edge Circuit tuning 220 applysecond clock signal 229 with produce have change output power spectrum throughmodulated output signal 227, the output power spectrum of described change (is n/T at the frequency multiple of second clock signal 229₂) under there is spectral null 252,254,256 and 258.Can select the frequency ofsecond clock signal 229 so that it is corresponding to interested rf frequency (the rf frequency that, receiver circuit is tuned to).This clock frequency is selected to can be used to spectral null to be positioned under interested frequency, and this has reduced the radiation interference under this frequency and harmonic wave thereof.Becauseedge Circuit tuning 220 has changed edge time ofdigit data stream 209, what therefore obtain comprises spectral null but can not change the mean data rate ofdigit data stream 209 throughmodulated output signal 227.

In some cases, due to the difference of current path (drawing high current path with respect to dragging down current path) or due to the manufacturing variation of drawing high or dragging down between the field effect transistor (p channel fet and/or n channel fet) of driving circuit, numeral output rising and falling time may not be strict symmetrical.For the spectral null that usescircuit arrangement 200 requiring in the output power spectrum throughmodulated output signal 227 to provide under frequency, rising pulse should equal communication data signal anti-phase falling pulse so that positive pulse by the negative pulse of constant amplitude, offset.Yet, if inaccurately control rising edge and negative edge, think that drawing high and drag down pulse (as shown insequential chart 300 in Fig. 3 A) provides equal duration of pulse and equal pulse area, because two signals are not exclusively offset the spectral null in output power spectrum is is partly filled and led up.

In addition, being associated with the electric current of drawing high pulse can follow and different flow to ground current path than being associated with the circuit that drags down pulse.Under this class situation, even be subject to accurately controlling while making when transistor characteristic, also can affect because of different current flow path magnetic coupling, this produces in addition unbalanced pulse so that spectral null is part fills and leads up.

Fig. 3 A illustrates with respect to the ideal current 304 throughmodulated output signal 227 to compare the unbalancedsequential chart 300 of drawing high and drag down electric current 306.Ideal current 304 comprises respectively draws high and drags down pulse, forexample pulse 308 and 310, and these pulses are used for forming corresponding rising edge and the negative edge through modulated output signal 227.In one example.Drawing high current impulse is used for driving digital I/O pin 110 to form the rising edge through modulated output signal 227.Dragging down current impulse is used for driving digital I/O pin 110 to form the negative edge throughmodulated output signal 227.

In some digital circuits, the rising and falling time of numeral output may not be strict symmetrical.For example, the current path that is driven to low digital I/O pin may be different from the current path of driven paramount digital I/O pin.These differences can be reflected in the pulsion phase ratio of drawing high of forexample pulse 312 as in the various durations that drags down pulse of pulse 314.This different duration may be caused imbalance, uneven and then reduce or fill and lead up the spectral null in the power spectrum ofmodulated output signal 227.

Fig. 3 B is the figure for theoutput power spectrum 320 of the ideal current 304 shown in Fig. 3 A and out-of-balance current 306, and it illustrates and is requiring frequency (1/T from ideal current 304₂)spectral null 324 located, and being illustrated in the spread spectrum (filling and leading up) 326 requiring under frequency, this expansion is drawn high and is dragged downpulse 312 and 314 and caused by unbalanced.Thisfrequency expansion 326 is partly eliminatedspectral null 324, thereby at the frequency requiring and harmonic wave (n/T thereof₂) lower emittance, near the reception at the analog receiver circuit place energy of this radiation may disturb.In order to use, to draw high pulse and drag down pulse to offset, pulse should be symmetrical, yet this symmetry may be difficult to obtain.

Yet, can draw high pulse and offset and draw high pulse and drag down pulse and offset and drag down pulse with neighbouring with neighbouring, thus generation spectral null.In this embodiment, can ignore the asymmetry between rising pulse and falling pulse.In an object lesson, if the edge time of near positive pulse and near negative pulse be adjusted to respectively the rf frequency cycle (T2) that the integer of being separated by adds 1/2 times (i.e. (n+0.5) T₂), spectral null is introduced in the output power spectrum of modulated output signal, and this is with to draw high/drag down Pulse symmetry irrelevant, as below with reference to as described in Fig. 4.

Fig. 4 illustrates the block scheme of the second embodiment of thecircuit arrangement 400 that comprises theedge Circuit tuning 420 that is configured to signal 209 reclockings to digital data.Edge Circuittuning 420 is in such a way to the signal reclocking receiving, such as making to have nothing to do in drawing high and drag down symmetry between pulse in the mode that requires to introduce under frequency spectral null throughmodulated output signal 440.

Circuit arrangement 400 comprisesedge Circuit tuning 420, and thisedge Circuit tuning 420 comprises the edgeCircuit tuning input 210 in order to received digital data stream 209.Edge Circuit tuning 420 comprisesmultiplexer 402, and thismultiplexer 402 has the second clock of being coupled insource 228 and has clock rate (1/T to receive₂)second clock signal 229 thefirst input 403 and have byphase inverter 405 and be coupled insecond clock source 228 to receive thesecond input 404 of the anti-phase form of second clock signal 229.Multiplexer 402 also comprises that being coupled innode 412 selects theMUX selection input 408 ofsignal 409 and themultiplexer output 406 that the clock signal ofselection 407 is offered to theclock input 222 of reclocking flip-flop circuit 224 to receive MUX.

Reclocking flip-flop circuit 224 receiveddigital data streams 209 also receive selected clock signal 407 (besecond clock signal 229 or be the paraphase form of second clock signal).Reclocking flip-flop circuit 224 latchsdigit data stream 209 and will provide tonode 439 throughmodulated output signal 440 to be associated with the second clock speed of theclock signal 407 of selection.

Edge Circuit tuning 420 also comprises logical circuit, for example T-flip flop circuit 410, this T-flip flop circuit 410 have be coupled in the clock input ofnode 439, the data that are coupled in the output ofnode 412 and are coupled innode 412 byphase inverter 411 are inputted.Edge Circuit tuning 420 also comprisesdata buffer 226, and thisdata buffer 226 comprises and is coupled in the input ofnode 439 and the output that is coupled incommunication link 114 bydata buffer 108 and digital I/O pin 110.As described with reference to Fig. 2 A above,data buffer 226 can be the same flip-flop circuit that receives theclock signal 407 of selecting.

Second clock source 228 is coupled incontrol circuit 422, and thiscontrol circuit 422 is configured to control the clock rate of second clock signal 229.In a concrete example,control circuit 422 regulatesecond clock sources 228 with produce have with near clock frequency (1/T corresponding to the interested rf frequency of analog receiver circuit₂)second clock signal 229.

In one example, inmultiplexer input 403, receive from thesecond clock signal 229 insecond clock source 228 and inmultiplexer input 404, receive the anti-phase form of second clock signals.The MUX ofmultiplexer 402 based on receiving fromnode 412 selectssignal 409 that the anti-phase form ofsecond clock signal 229 or second clock signal is offered tomultiplexer output 406 as theclock signal 407 of selecting.

The rising edge of theclock signal 407 of reclocking flip-flop circuit 224 based on selecting moves tonode 439 bydigit data stream 209 from edgeCircuit tuning input 210, and this rising edge can selectsignal 409 to represent rising edge or the negative edge ofsecond clock signal 229 according to MUX.

Node 439 places are provided forcommunication link 114 throughmodulated output signal 440 bydata buffer 226,data buffer 108 and digital I/O pin 110.The saltus step inmodulation output stream 440 atnode 439 places makes T-flip flop circuit 410 change atnode 439 value that MUX selects signal 409.Specifically, whenever reclocking flip-flop circuit 224 innode 439 output the rising edge throughmodulated output signal 440, T-flip flop circuit 410 changes its output atnode 412, thereby change multiplexer, selects the MUX ininput 408select signal 409 and change selected clock signal 407.Inclock input 222, receive theclock signal 407 selected inmultiplexers output 406 with to flip-flop circuit 224 reclockings, change saltus step edge time indigit data stream 209 with produce have require to exist under frequency and harmonic wave thereof spectral null power spectrum throughmodulated output signal 440.

In one embodiment, a number adds clock period (i.e. (n+1/2) T of thesecond clock signal 229 of 1/2 times so that adjacent rising edge is separated by the edge time of capable of regulating rising edge and negative edge₂).The negative edge identical interval that can be separated by.In this case, the controlleddevice 420 of second clock signal that clock is inputted 403 places controls to make it have approximate frequency (1/T₂), as shown in equation 3:

$f_{\mathrm{RF}}=\frac{1}{n{T}_2}$(equation 3)

By these saltus steps in the digit data stream with respect to receiving, move the edge interval time of the saltus step inmodulated output signal 440, near the pulse counteracting of drawing high available is drawn high pulse and is dragged down pulse with near the pulse counteracting that drags down, and no longer needs thus to draw high and drag down the symmetry between current impulse.In one example, under the situation throughmodulated output signal 440 and sinusoidal signal convolution, can translation through the saltus step edge ofmodulated output signal 440 so that first draw high pulse corresponding to the positive part of sinusoidal signal and make the adjacent pulse of drawing high move to the negative part corresponding to sinusoidal signal.Therefore, rising edge by translation to offset the energy from adjacent rising edge, and negative edge by translation to offset the energy from adjacent negative edge, this allows irrelevantly to draw high/drag down Pulse symmetry and insert spectral null.

Fig. 5 illustrates thesequential chart 500 of the signal that is associated with Fig. 4 circuit arrangement 400.Sequential chart 500 comprises thedigit data stream 209 with first clock rate corresponding with clock signal 109.Sequential chart 500 also comprises thesecond clock signal 229 with second clock speed.Sequential chart 500 also comprises throughmodulated output signal 440, MUX to be selectedsignal 409 and draws high/drag down electric current (I_d) 512.

When MUX selects signal 409 indication negative edges to select 514, whendigit data stream 209 is high, electric current (I is drawn high in output_d)pulse 520 rises along with the negative edge ofsecond clock signal 229, whendigit data stream 209 is low, drag downcurrent impulse 526 and decline along with the negative edge of second clock signal 229.When MUX selects signal 409 indication rising edges to select 516, electric current (I is drawn high in output_d)pulse 522 and output drags downpulse 528 saltus step along with the rising edge of second clock signal 229.Therefore, interval, edge (cycle) translation one integer between risingedge 520 and 522 adds second clock signal period (i.e. (N+1/2) T of 1/2 times₂).Equally, also identical cycle of translation edge interval time between rising pulse 522,524 and between falling pulse 526,528.Fractional part (0.5 * T₂) be associated with the rising edge ofsecond clock signal 229 in the given clock period and the mistiming between negative edge.Therefore, through the rising edge of modulatedoutput signal 440 and the edge time of negative edge, change and be subject to the constraint ofsecond clock signal 229, thereby spectral null is arranged under the frequency and harmonic wave thereof that output power spectrum requires.In addition, thecontrol signal 109 that is had the first clock rate due to data rate controls and the edge time is subject todigit data stream 209 and 229 constraints of second clock signal, therefore can introduce the edge time to change and do not change mean data rate.

In practice,clock source 229 nearly may not have 50% dutycycle and this can cause hydraulic performancedecline.Clock source 229 may be on chip the suitable distance of route, and clock buffer may make the dutycycle of signal decline.In order to address this problem, shown in capable of regulating Fig. 4, be configured to run on the new clock input under the dual-rate of speed shown in Fig. 4.This embodiment is illustrated in Fig. 6.Fig. 6 is the block scheme of the 3rd embodiment ofcircuit arrangement 600, and thiscircuit arrangement 600 comprises the edge Circuit tuning 620 being configured to input signal 103 reclockings.Edge Circuit tuning 620 comprises the first trigger (DFF1) 602, in order to received digital data stream (D0) 209 and receive associated withsecond clock signal 229 through modulation clock signal 601 from node 640.In one example, through modulation clock signal 601, are the 50% duty cycle clock signals nearly of deriving fromsecond clock signal 229.

The first trigger (DFF1) 602 latchsdigit data stream 209 to produce data stream (D1) 606 according to the rising edge through modulation clock signal 601.Edge Circuit tuning 620 further comprises the second trigger (DFF2) 604, is used for based on inputting 605 streams of the negative edge latch data through modulation clock signal 601 (D1) that receive by inverted phase clock to produce first through modulated data stream (D2) 608.

In addition, edge Circuit tuning 620 comprises the 3rd trigger (DFF3) 612, is used for by inverted phase clock, inputting the 611 negative edge received digital data streams (D0) 209 through modulation clock signal 601 that receive to produce data stream (D3) 616.Edge Circuit tuning 620 also comprises that the 4th trigger (DFF4) 614 is with rising edge latch data stream (D3) 616 based on through modulation clock signal 601, thereby produces second through modulated data stream (D4) 618.

In addition, edge Circuit tuning 620 comprises logic AND door (with door) 621, and this ANDdoor 621 has reception first and inputs, receives second through the 2nd AND input of modulated data stream (D4) 618 and ANDout (AND goes out) signal 624 is provided to the AND output of the clock input of the 5th trigger (DFF5) 622 through an AND of modulated data stream (D2) 608.The 5th trigger (DFF5) 622 comprises byphase inverter 628 and is coupled in the output ofnode 626 and comprises the input that is coupled in node 626.Therefore, logic ANDdoor 621 is arranged in bistable state configuration, and this configuration is suitable for changing its output along with each new rising edge ofANDout signal 624.

Edge Circuit tuning 620 also comprisesmultiplexer 630, and thismultiplexer 630 comprises for receiving first the first multiplexer input through modulated data stream (D2) 608 and inputting through the second multiplexer of modulated data stream (D4) 618 for receivingsecond.Multiplexer 630 also comprises that being coupled innode 626 selects the multiplexer ofsignal 632 select to input and comprise by one or more buffers of forexample data buffer 108 multiplexer that offers digital I/O pin 110 through modulated output signal 642 is exported to receiveMUX.Multiplexer 630 response MUXselect signals 632 to export selectively the first and second one 608 in modulated data stream or 618 as through modulated output signal 642.Because selecting the value ofsignal 632, MUX responds the first and second saltus steps through modulated data stream 608,632 (being the saltus step in ANDout signal) and saltus step, therefore multiplexer 630 is repeatedly switched by logic ANDdoor 621 when data jump, changes the edge time of data output signal thus by controllingmultiplexer 630 outputs first or second through modulateddata stream 608 or 618.

Edge Circuit tuning 620 also comprise the 6th trigger (DFF6) 634, the six triggers (DFF6) 634 comprise byphase inverter 638 be coupled innode 640 input, be coupled insecond clock source 228 to receive theclock input 636 ofsecond clock signal 229 and the output that is coupled in node 640.In one embodiment, the 6th trigger (DFF6) 634 is with the rf frequency (1/2T of second clock signal 229₂) produce modulated clock signal 601 and come timing to enter data in the first, second, third and the 4th trigger 602,604,612 and 614 to produce spectral null with require frequency and harmonic wave place thereof in the output power spectrum through modulatedoutput signal 624, and do not need onsecond clock signal 229 50% dutycycle.

In one example, the first trigger (DFF1) 602 at the first side of the second clock signal atnode 640 places for example, along the rising edge of time clock () the mobiledigit data stream 209 from edge Circuit tuning input 210.The 3rd trigger (DFF3) 612 Second Edges at second clock signal for example, read thedigit data stream 209 from edgeCircuit tuning input 210 along (negative edge of time clock).By the rising and falling edges through modulation clock signal 601, latch time deviation thatdigit data stream 209 produces and cause in preset time arbitrarily o'clock poorly at the data phase at the first and the 3rd trigger 602,612 places, this phase differential is equal to the clock period (T of second clock signal 229₂).

The second trigger (DFF2) 604 is at the negative edge reading data flow (D1) 606 through modulation clock signal 601, and the 4th trigger (DFF4) 614 is at the rising edge through modulation clock signal 601 (being the rising edge of next clock pulse) reading data flow (D3) 616.Therefore, through modulated data stream (D2) 608, appear at the negative edge that reads the same time clock ofdigit data stream 209 from edge Circuit tuning input 210.On the contrary, modulated data-signal (D4) 618 appears at the rising edge of next clock pulse.

Logic ANDdoor 621 changes its output based on the first and second values through modulated data stream (D2) 608, (D4) 618.Whenever ANDout signal 624 from low to high, the just outputs at switchingnode 626 places repeatedly of the 5th trigger (DFF5) 622, thus change the value that the MUX that offersmultiplexer 630 selects signal 632.MUXselect signal 632control multiplexers 630 outputs first through modulated data stream (D2) 608 or second through modulated data stream (D4) 618.

Therefore through the saltus step edge time in modulated output signal 642, be, to be determined by first and second saltus steps in modulated data stream 608,618 through modulation clock signal 601 input by logic ANDdoor 621 of deriving from second clock signal 229.By changing the edge time, can introduce spectral null and can not change the mean data rate with respect todigit data stream 209 speed at require rf frequency and the harmonic wave place thereof of the output power spectrum through modulated output signal 642.

Fig. 7 illustrates thesequential chart 700 of the signal of thecircuit arrangement 600 that is associated with Fig. 6.Sequential chart 700 comprisesinput signal 103 and the first clock signal 109.Sequential chart 700 also comprises through modulation clock signal 601, data-signal (D1) 606, data-signal (D3) 616, first through modulated data stream (D2) 608 and second through modulated data stream (D4) 618.In addition,sequential chart 700 comprises thatANDout signal 624, MUX are selectedsignal 632 and through modulated output signal 642.

When the first and second one in modulated data stream 608,618 are height and another one saltus step when paramount,ANDout signal 624 is paramount from end saltus step.In addition, when first and second, through modulated data stream 608,618, be when high, first or second throughmodulation signal 608 or 618 from high saltus step when low, 624 saltus steps of ANDout signal are to low.

Multiplexer selects signal 632 in each rising edge saltus step of ANDout signal 624.Therefore, multiplexer is selected signal 632 saltus step in modulated data stream 608,618 and changing based on first and second.Multiplexer 630 response multiplexers select signals 632 with selectively in 722 outputs first through modulated data stream (D2) 608,726 outputs second through modulated data stream (D4) 618 and again in 732 outputs first through modulated data stream (D2) 608.Through modulated output signal 642, follow the tracks of first through modulated data stream (D2) 608, until multiplexer selects signal 642 in 724 saltus step positions, now through modulated output signal 642, follow the tracks of second through modulated data stream (D4) 618.Through modulated output signal 642, continue to follow the tracks of second through modulated data stream (D4) 618,728 by second through modulated data stream (D4) 618 saltus steps to logic high, and by multiplexer, select signal 632 repeatedly to switch in saltus step 730, to follow first through modulated data stream (D2) 608 subsequently.After saltus step 730, ANDout signal 624 is in 734 saltus steps, and switching multiplexing device is selected signal 632 so that multiplexer exports second through modulated data stream (D4) 618 repeatedly.Yet, due to second through modulated data stream (D4) 618 in first through the identical logic high of modulated data stream (D2) 608, therefore through modulated output signal 642, remain on logic high.

The saltus step edge time in modulated output signal 642 changed with respect to the saltus step edge time in input signal 103.As previously mentioned, the change edge time can require to produce spectral null under frequency in the output power spectrum through modulated output signal 642.This spectral null has reduced near receiver circuit in the radiation interference requiring under frequency and harmonic wave thereof.

Fig. 8 is the block scheme of an embodiment ofcommunicator 800, and thiscommunicator 800 comprises and being configured to digital signal reclocking to change selectively the edge Circuit tuning 830 of the edge time ofdigital signal.Communicator 800 can be configured to receive RF signal and the data that are associated with received RF signal are conveyed to mobile phone, personal digital assistant, media player (audio frequency, video etc.) or other electronic equipment such as near the circuit ofdata circuit 112.

Communicator 800 comprises theantenna 802 that is coupled indata circuit 112 by signal processing circuit 804.Signal processing circuit 804 compriseslow noise amplifier 808, and thislow noise amplifier 808 comprises the first input that is coupled inantenna 802 and the second input that is coupled in electrical grounding 810.Low noise amplifier 808 has the output that is coupled infrequency mixer 814,frequency mixer 814 fromlocal oscillator 816 receive clock signals and by the analog radio-frequency signal receiving with clock signal mixing with generation homophase (I) and quadrature (Q) basebandsignal.Frequency mixer 814 offersprogrammable gain amplifier 822 by I and Q baseband signal, andprogrammable gain amplifier 822 regulates selectively the gain of I and Q baseband signal and I and Q baseband signal through regulating are offered to I and Q analog to digital converter (ADC) 824,826.ADC 824,826 converts I and Q baseband signal to digital signal, and this digital signal is provided for digital signal processor (DSP) 828.

DSP 828 can be configured to process and/or compression I and Q baseband signal.In mobile phone application, forexample DSP 828 can be configured to compressed voice sound signal and sends and receiving digital signals.In the audio system of for example radio receiver circuit or television receiver, can provide high-fidelity equilibrium and/or the processing audio/vision signal to sound signal with DSP 828.DSP 828 is coupled ingeneral output circuit 840 andcontrol interface 842 to pass on data to other circuit and to receive data from other circuit, and forexample control circuit 422.

In addition,DSP 828 offers edge Circuit tuning 830 by treated I and Q baseband signal, and this edge Circuit tuning 830 can comprise two edge Circuit tunings in parallel, for example the edge Circuit tuning shown in Fig. 2 A, 4 and 6 220,420 and 620.For example, edge Circuit tuning 830 can comprise two duplicate circuits of the edge Circuit tuning 620 of the Fig. 6 that uses 831 timing of second clock source, so that one of them edge Circuit tuning is exported right output (Rout) signal, another exports left output (Lout) signal.

The clock signal of edge Circuit tuning 830 based on fromsecond clock source 831 changes the edge time of I and Q baseband signal selectively.Althoughsecond clock source 831 is illustrated as in edge Circuit tuning 830 outsides, yet in certain embodiments,second clock source 831 can be included in edge Circuit tuning 830.Edge Circuit tuning is adjusted the edge time of treated I and Q baseband signal and bydata buffer 832 and 836 and by the right side, left digital I/O (I/O)pin 834 and 838 and stride across the right side, left output (communication link 114) signal through adjustment is offered to data circuit 112.In certain embodiments,second clock source 831 can be coupled inlocal oscillator 816.

By using edge Circuit tuning 830 to adjust selectively the edge time of the saltus step in treated I, Q baseband signal, can todata circuit 112, pass on digital signal and can under for the interested rf frequency ofantenna 802, not produce radiation interference across communication link 114.Specifically, acrosscommunication link 114, be transferred to the rf frequency (1/T that the Rout ofdata circuit 112 and the output power spectrum of Lout baseband signal are requiring₂) under there is frequency zero.As previously mentioned,second clock source 831 can provide the second clock signal with the clock rate different from the clock rate of digit data stream, and this clock rate is selected under rf frequency interested and harmonic wave thereof spectral null is introduced through modulated output signal.Response second clock signal, edge Circuit tuning 830 can change the saltus step edge time in treated I and Q baseband signal selectively, for example, as integer, add the clock period (T of the second clock signal of 1/2 multiple₂) function, as previously mentioned.

Signal processing circuit 804 comprises theadjustable frequency circuit 818 that is coupled inreceiver clock pin 820, and thisreceiver clock pin 820 can be accessed to adjust by for example control circuit ofcontrol circuit 422 clock rate of local oscillator 816.The clock rate of capable of regulatinglocal oscillator 816 is to change the intermediate frequency of I and Q baseband signal.

In addition,signal processing circuit 804 comprisespin 836, andcontrol circuit 422 can be communicated by letter withcontrol interface 842 by this pin836.By control interface 842, forexample control circuit 422 can change the second clock speed insecond clock source 831, adjusts the frequency zero being produced by edge Circuit tuning 830 in Rout and Lout signal.

In one embodiment, bycontrol interface 842 andgeneral output circuit 840 control signal bypin 836 sending and receivings, be in the data rate that under interested rf frequency, non-radiating goes out to disturb.Yet, in the alternate embodiment of high-speed transfer that control signal is provided bypin 836,control interface 842 andgeneral output circuit 840, can comprise for example edge Circuit tuning of edge Circuit tuning 830 and so on.

In operation, edge Circuit tuning 830 changes the saltus step edge time in modulated data signal that sends todata circuit 112 oncommunication link 114 selectively, introduces spectral null to reduce the radiation interference under rf frequency interested at each in the output power frequency spectrum of modulated data signal.The clock frequency that controlcircuit 422 is configured to changesecond clock 831 is to change the frequency of spectral null appearance.

Fig. 9 is the process flow diagram 900 of the embodiment of the method during to input signal restatement by changing selectively the edge time.902, receive the numerical data with the mean data rate corresponding with the first clock rate.In one example, can be from being coupled in the signal source received digital data stream of first clock with the first clock rate, so that digit data stream has the data rate corresponding with the first clock rate.

Advance to 904, from thering is the time base source receive clock signal of second clock speed.Second clock signal can have the clock period (T with the first clock signal₁) different clock period (T₂).Can select second clock speed (1/T₂) so that its frequencies of interest corresponding near receiver circuit.

Proceed to 906, the edge time of adjusting the saltus step in digit data stream based on this clock signal does not change mean data rate at the power spectrum that requires to comprise spectral null under frequency (and harmonic wave) through modulated output signal to produce to have.In one example, can for example, by digital signal streams be latching in data storage elements (data trigger circuit) and adjusts the edge time with second clock speed.In another example, can selectively digit data stream be latching in data storage elements by the paraphase version according to clock signal or clock signal,

In another embodiment, the saltus step in modulated output signal can be used to produce control signal.In some cases, in these embodiments, can be by making one's options and come adjusting edge along the time as the clock input of data storage elements between clock signal and clock signal paraphase version based on this control signal.

In other cases, can produce control signal with saltus step.In one example, can digit data stream be for example latching to, in data storage elements (flip-flop circuit) to produce first and numerical data be latching in the second data storage elements and through modulation signal, adjust the edge time to produce second through modulation signal the rising edge based on clock signal by the negative edge based on clock signal.Can produce through modulated output signal by offering output through modulation signal or second through modulation signal by first selectively based on control signal.In another example, can through modulated data stream, adjust the edge time by export selectively first or second based on control signal.

Figure 10 is the process flow diagram 1000 to the method for data-signal reclocking embodiment.1002, the selected edge that uses clock signal to digital data during flowmeter to produce reclocking data stream.In one example, clock signal can be offered to for example clock input of the data storage elements of data trigger circuit, described data trigger circuit is at the rising edge Mobile data of clock signal.

Advance to 1004, the saltus step in the data stream based on through reclocking and produce control signal.For example, referring to Fig. 4, reclocking data stream is offered to digital I/O pin 110 and offer the clock input of the logical circuit that is for example configured between two states data trigger of repeatedly switching and so on.The output of logical circuit can be used as control signal to control multiplexer selectively the one in the paraphase version of clock signal or clock signal is offered to data storage elements to flow to digital data reclocking.

Advance to 1006, based on control signal, select the edge (for example rising edge or negative edge) of clock signal to change selectively the edge time in the data-signal of reclocking, thus produce have require to contain frequency (and harmonic wave) under spectral null power spectrum through modulated output signal.The frequency requiring can be corresponding to near the interested rf frequency of rf frequency receiver circuit.The clock signal period that can adjacent rising edge translation one integer through modulated output signal be added with respect to the adjacent rising edge in digit data stream in one embodiment, to 1/2 multiple.In an example, change selectively the edge time and do not change the mean data rate associated with the digit data stream receiving.

In another embodiment, clock signal has the clock frequency corresponding with requiring frequency.In addition, clock signal has the clock rate different from the clock rate of digit data stream.In another embodiment, by selectively the paraphase version of clock signal or clock signal being put on to the clock input of reclocking flip-flop circuit, select the edge of clock signal, thereby change the edge time.In another embodiment, by according to selecting signal to export selectively the edge that one in the first reclocking data stream (rising edge based on clock signal) or the second reclocking data stream (negative edge based on clock signal) is selected clock signal.

Can make many additional modifications and variation and not depart from spirit and scope of the present disclosure technology that herein institute record and describe and structure.For example, thesecond clock source 228 shown in Fig. 2 a, Fig. 4 and Fig. 6 can be derived from the first clock source 106.In addition,, with reference to thecircuit arrangement 804 shown in Fig. 8, the one or both in clock source (local oscillator 816 and second clock 831) can be positioned at circuit arrangement outside.

In addition, referring to the method for describing in Fig. 9 and Figure 10, before being to be understood that the square frame that can provide in the drawings according to application-specific, afterwards or between carry out other processing, transmission or tuning step.In addition, described technology can be used for measurement mechanism, communicator, or the digital signal control any circuit of electromagnetic interference (EMI) (EMI) radiation of communicating by letter.Therefore, the present invention it should be clearly understood that as only by the scope definition of claims and equivalent thereof.

Claims (11)

Translated fromChinese

1.一种对输入信号重新计时的方法，所述方法包括：1. A method of reclocking an input signal, the method comprising:在边沿调整电路的重新计时触发器电路的输入处接收具有对应于第一时钟速率的平均数据速率的数字数据流，所述第一时钟速率与第一时钟源关联；receiving a digital data stream having an average data rate corresponding to a first clock rate at an input of a reclocking flip-flop circuit of the edge adjustment circuit, the first clock rate being associated with the first clock source;从第二时钟源接收具有第二时钟速率的第二时钟信号；以及receiving a second clock signal having a second clock rate from a second clock source; and有选择地提供所述第二时钟信号和所述第二时钟信号倒相版本的其中选中一者到所述重新计时触发器电路的时钟输入，以重新计时所述数字数据流，从而基于所述第二时钟信号和所述第二时钟信号倒相版本的其中所述选中一者中的跳变边沿来调整所述数字数据流中的跳变的边沿时间，所述重新计时触发器电路被配置为响应于所述选中一者中的跳变边沿而产生经调制输出信号，selectively providing a selected one of the second clock signal and an inverted version of the second clock signal to a clock input of the reclocking flip-flop circuit to reclock the digital data stream based on the A transition edge in said selected one of a second clock signal and an inverted version of said second clock signal to adjust an edge time of a transition in said digital data stream, said reclocking flip-flop circuit being configured for generating a modulated output signal in response to a transition edge in said selected one,其中所述经调制输出信号具有在要求频率及其谐波下包含频谱零点的功率谱而不改变所述平均数据速率，从而降低对附近接收机电路的辐射干扰，所述要求频率包括附近接收机电路的射频频率。wherein said modulated output signal has a power spectrum containing spectral nulls at a desired frequency and its harmonics without changing said average data rate, thereby reducing radiated interference to nearby receiver circuits, said desired frequency including nearby receivers RF frequency of the circuit.2.如权利要求1所述的方法，其特征在于，调整跳变的边沿时间包括基于所述第二时钟信号的边沿以所述第二时钟速率将所述数字数据流锁存至数据存储元件中。2. The method of claim 1 , wherein adjusting transition edge times comprises latching the digital data stream to a data storage element at the second clock rate based on an edge of the second clock signal middle.3.如权利要求1所述的方法，其特征在于，调整跳变的边沿时间包括：3. The method according to claim 1, wherein adjusting the edge time of the transition comprises:将所述第二时钟信号和所述倒相版本提供给多路复用器的第一和第二输入，所述多路复用器包括选择输入且包括输出，该输出耦合到所述重新计时触发器电路的所述时钟输入；以及providing the second clock signal and the inverted version to first and second inputs of a multiplexer including a select input and including an output coupled to the reclocked said clock input to a flip-flop circuit; and在所述选择输入处接收多路复用器选择信号；以及receiving a multiplexer select signal at the select input; and有选择地提供所述第二时钟信号和所述第二时钟信号的所述倒相版本的其中一者到所述多路复用器的所述输出，作为选中时钟信号。One of the second clock signal and the inverted version of the second clock signal is selectively provided to the output of the multiplexer as a selected clock signal.4.如权利要求1所述的方法，其特征在于，所述第二时钟速率大于所述第一时钟速率。4. The method of claim 1, wherein the second clock rate is greater than the first clock rate.5.如权利要求1所述的方法，其特征在于，所述方法还包括基于所述经调制输出信号中的跳变使用触发器来改变多路复用器选择信号，所述触发器具有时钟输入，该时钟输入被配置为接收经调制的输出信号、数据输入、和经过反相器耦合到所述数据输入的数据输出，所述触发器配置为翻转输出信号以产生所述多路复用器选择信号。5. The method of claim 1, further comprising using a flip-flop to change a multiplexer select signal based on a transition in the modulated output signal, the flip-flop having a clock input, the clock input configured to receive a modulated output signal, a data input, and a data output coupled to the data input via an inverter, the flip-flop configured to invert the output signal to produce the multiplexed selector signal.6.一种对输入信号重新计时的方法，所述方法包括：在边沿调整电路的重新计时触发器电路的输入处接收具有对应于第一时钟速率的平均数据速率的数字数据流，所述第一时钟速率与第一时钟源关联；6. A method of reclocking an input signal, the method comprising: receiving at an input of a reclocking flip-flop circuit of an edge adjustment circuit a digital data stream having an average data rate corresponding to a first clock rate, the first a clock rate associated with the first clock source;从第二时钟源接收具有第二时钟速率的第二时钟信号；receiving a second clock signal having a second clock rate from a second clock source;基于从所述第二时钟信号获得的经调制时钟信号的下降沿将和所述数字数据流相关的第一数据流锁存至第一输出以产生第一经调制信号；latching a first data stream associated with said digital data stream to a first output based on a falling edge of a modulated clock signal derived from said second clock signal to generate a first modulated signal;基于所述经调制时钟信号的上升沿将和所述数字数据流相关的第二数据流锁存至第二输出以产生第二经调制信号；以及latching a second data stream associated with the digital data stream to a second output based on a rising edge of the modulated clock signal to generate a second modulated signal; and有选择地将所述第一经调制信号和所述第二经调制信号中的一者提供给输出以产生经调制输出信号，selectively providing one of the first modulated signal and the second modulated signal to an output to generate a modulated output signal,其中所述经调制输出信号具有在要求频率及其谐波下包含频谱零点的功率谱而不改变所述平均数据速率，从而降低对附近接收机电路的辐射干扰，所述要求频率包括附近接收机电路的射频频率。wherein said modulated output signal has a power spectrum containing spectral nulls at a desired frequency and its harmonics without changing said average data rate, thereby reducing radiated interference to nearby receiver circuits, said desired frequency including nearby receivers RF frequency of the circuit.7.一种对输入信号重新计时的电路装置，所述电路装置包括：7. A circuit arrangement for reclocking an input signal, said circuit arrangement comprising:接收具有第一时钟速率的数字数据流的输入，所述第一时钟速率对应于来自第一时钟源的第一时钟信号；receiving an input of a digital data stream having a first clock rate corresponding to a first clock signal from a first clock source;时钟输入，用于从第二时钟源接收具有第二时钟速率的第二时钟信号；a clock input for receiving a second clock signal having a second clock rate from a second clock source;控制电路，耦合至所述第二时钟源并配置成控制所述第二时钟速率以对应于要求频率，以及a control circuit coupled to the second clock source and configured to control the second clock rate to correspond to a desired frequency, and边沿调整电路，所述边沿调整电路配置成使用所述第二时钟信号和所述第二时钟信号倒相版本的其中选中一者中的跳变边沿对所述数字数据流重新计时，所述边沿调整电路包括：an edge adjustment circuit configured to reclock the stream of digital data using a transition edge in a selected one of the second clock signal and an inverted version of the second clock signal, the edge The adjustment circuit consists of:多路复用器，其被配置为有选择地将所述第二时钟信号和所述倒相版本的其中所述选中一者提供给所述多路复用器的输出；以及a multiplexer configured to selectively provide the selected one of the second clock signal and the inverted version to an output of the multiplexer; and重新计时触发器电路，其包括用于接收所述数字数据流的输入，和耦合到所述多路复用器的输出的时钟输入，所述重新计时触发器电路还包括输出，所述重新计时触发器电路被配置为有选择地改变所述数字数据流中的跳变的边沿时间，从而响应于所述第二时钟信号和所述倒相信号的其中所述选中一者中的跳变边沿产生具有在所述要求频率及其谐波下含频谱零点的功率谱的经调制输出信号以降低对附近接收机电路的辐射干扰，所述要求频率包括附近接收机电路的射频频率。a re-clocking flip-flop circuit comprising an input for receiving said digital data stream, and a clock input coupled to the output of said multiplexer, said re-clocking flip-flop circuit further comprising an output, said re-clocking flip-flop circuitry configured to selectively vary the edge timing of transitions in the digital data stream in response to transition edges in the selected one of the second clock signal and the inverted signal A modulated output signal having a power spectrum including spectral nulls at the desired frequency and harmonics thereof is generated to reduce radiated interference to nearby receiver circuits, the desired frequency including radio frequencies of nearby receiver circuits.8.如权利要求7所述的电路装置，其特征在于，还包括第一触发器，其包括用于接收输入信号的第一输入、用于接收第一时钟信号的第一时钟输入、以及耦合于所述输入并配置成提供所述数字数据流的第一输出。8. The circuit arrangement of claim 7, further comprising a first flip-flop comprising a first input for receiving an input signal, a first clock input for receiving a first clock signal, and coupled at the input and configured to provide a first output of the digital data stream.9.如权利要求7所述的电路装置，其特征在于，所述边沿调整电路包括：9. The circuit device according to claim 7, wherein the edge adjustment circuit comprises:逻辑电路，所述逻辑电路配置成基于所述数字数据流中的跳变而产生所述控制信号；logic circuitry configured to generate the control signal based on transitions in the digital data stream;所述多路复用器包括接收所述第二时钟信号的第一输入、接收所述第二时钟信号的倒相版本的第二输入、以及接收所述控制信号的选择输入，所述多路复用器还包括输出，且被配置为响应于所述控制信号将所述第二时钟信号和所述第二时钟信号的倒相版本中的一者提供给所述输出；以及The multiplexer includes a first input receiving the second clock signal, a second input receiving an inverted version of the second clock signal, and a select input receiving the control signal, the multiplexer the multiplexer also includes an output and is configured to provide one of the second clock signal and an inverted version of the second clock signal to the output in response to the control signal; and触发器，包括时钟输入、输入、以及输出，所述时钟输入耦合到所述重新计时触发器的输出，所述输出通过反相器耦合到所述输入且耦合到所述多路复用器的所述选择输入，所述触发器配置成基于所述经调制输出信号中的跳变来产生所述控制信号。a flip-flop including a clock input, an input, and an output, the clock input being coupled to the output of the reclocking flip-flop, the output being coupled to the input through an inverter and to the multiplexer The select input, the flip-flop is configured to generate the control signal based on a transition in the modulated output signal.10.如权利要求7所述的电路装置，其特征在于，所述边沿调整电路产生所述经调制输出信号而相对于所述数字数据流不改变平均数据速率。10. The circuit device of claim 7, wherein the edge adjustment circuit generates the modulated output signal without changing an average data rate relative to the digital data stream.11.一种对输入信号重新计时的电路装置，所述电路装置包括：11. A circuit arrangement for reclocking an input signal, said circuit arrangement comprising:接收具有对应于第一时钟速率的平均数据速率的数字数据流的输入，所述第一时钟速率对应于来自第一时钟源的第一时钟信号；以及receiving an input of a digital data stream having an average data rate corresponding to a first clock rate corresponding to a first clock signal from a first clock source; and边沿调整电路，包括：Edge adjustment circuit, including:时钟输入，用于从第二时钟源接收具有第二时钟速率的第二时钟信号；a clock input for receiving a second clock signal having a second clock rate from a second clock source;第一数据存储元件，所述第一数据存储元件配置成根据从所述第二时钟信号获得的经调制时钟信号的下降沿锁存和所述数字数据流有关的第一数据流以产生第一经调制数据流；A first data storage element configured to latch a first data stream associated with said digital data stream in response to a falling edge of a modulated clock signal derived from said second clock signal to produce a first modulated data stream;第二数据存储元件，所述第二数据存储元件配置成根据所述经调制时钟信号的上升沿锁存和所述数字数据流有关的第二数据流以产生第二经调制数据流；a second data storage element configured to latch a second data stream associated with said digital data stream in response to a rising edge of said modulated clock signal to generate a second modulated data stream;逻辑电路，所述逻辑电路配置成基于所述第一和第二经调制数据流产生控制信号；以及logic circuitry configured to generate a control signal based on the first and second modulated data streams; and多路复用器，所述多路复用器包括：耦合于所述第一数据存储元件以接收所述第一经调制数据流的第一输入；耦合于所述第二数据存储元件以接收所述第二经调制数据流的第二输入；以及配置成接收所述控制信号的选择输入，所述多路复用器响应于所述控制信号有选择地将所述第一和所述第二经调制数据流中的一者提供给输出作为经调制输出信号，a multiplexer comprising: a first input coupled to the first data storage element to receive the first modulated data stream; coupled to the second data storage element to receive a second input for the second modulated data stream; and a select input configured to receive the control signal in response to which the multiplexer selectively combines the first and the second one of the two modulated data streams is provided to the output as a modulated output signal,其中所述经调制输出信号具有在要求频率及其谐波下包含频谱零点的功率谱而不改变所述平均数据速率，从而降低对附近接收机电路的辐射干扰，所述要求频率包括附近接收机电路的射频频率。wherein said modulated output signal has a power spectrum containing spectral nulls at a desired frequency and its harmonics without changing said average data rate, thereby reducing radiated interference to nearby receiver circuits, said desired frequency including nearby receivers RF frequency of the circuit.

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