CN102122527B - Memory circuit and method of controlling memory circuit - Google Patents

Abstract

A memory circuit includes a first memory array having a first terminal coupled to a first supply voltage and a second terminal coupled to a second supply voltage less than the first supply voltage, a second memory array having a third terminal and a fourth terminal, and a switch module coupled to the second terminal, the third terminal, the first supply voltage and the second supply voltage. When the memory circuit operates in a non-operation mode, the switch module electrically connects the second terminal to the third terminal, electrically isolates the second terminal from the second supply voltage, and electrically isolates the third terminal from the first supply voltage.

Description

Translated fromChinese

存储器电路以及控制存储器电路的方法Memory circuit and method of controlling memory circuit

技术领域technical field

本发明是有关于一种存储器电路，尤指一种可以降低漏电流的存储器电路以及控制存储器电路的方法。The invention relates to a memory circuit, in particular to a memory circuit capable of reducing leakage current and a method for controlling the memory circuit.

背景技术Background technique

请参考图1，图1为已知静态随机存取存储器(Static Random AccessMemory，SRAM)单元100的示意图。如图1所示，SRAM单元100包含有六个晶体管N1～N4以及P1～P2，而SRAM单元100可以通过切换字组线WL、位线BL以及互补位线

电压电平来进行数据存取，此外，因为本领域技术人员应了解SRAM单元100存取的操作，因此相关细节在此不予赘述。Please refer to FIG. 1 , which is a schematic diagram of a known static random access memory (Static Random Access Memory, SRAM) unit 100 . As shown in FIG. 1, the SRAM unit 100 includes six transistors N1-N4 and P1-P2, and the SRAM unit 100 can switch word line WL, bit line BL and complementary bit line

Data access is performed at a voltage level. In addition, because those skilled in the art should understand the operation of accessing the SRAM cell 100 , relevant details are not repeated here.

参考图1，当SRAM单元100位于非运作模式时(亦即晶体管N3、N4为非导通状态)，则节点A、B的电压电平会因为漏电流而改变，进而影响到之后读取SRAM单元100时数据的正确性。举例来说，假设目前SRAM单元100位于非运作模式，且节点A、B的电压电平分别为VDD、VSS，则节点A与电压源VSS之间会形成两个漏电流通路，亦即晶体管N1所形成的次临界漏电流(sub-threshold leakage current)以及晶体管N2所形成的栅极漏电流(gateleakage current)；类似地，节点B与电压源VDD之间亦会形成两个漏电流通路，亦即晶体管P2所形成的次临界漏电流以及晶体管P1所形成的栅极漏电流。随着制程技术进入深次微米(deep sub-micron)，此等漏电流将呈指数型剧增，甚至成为集成电路的主要功率消耗的来源。Referring to FIG. 1, when the SRAM unit 100 is in the non-operation mode (that is, the transistors N3 and N4 are in a non-conductive state), the voltage levels of the nodes A and B will change due to the leakage current, which will affect the subsequent reading of the SRAM. Correctness of the data at unit 100. For example, assuming that the SRAM cell 100 is currently in the non-operation mode, and the voltage levels of the nodes A and B are VDD and VSS respectively, two leakage current paths will be formed between the node A and the voltage source VSS, that is, the transistor N1 The formed sub-threshold leakage current (sub-threshold leakage current) and the gate leakage current (gate leakage current) formed by the transistor N2; similarly, two leakage current paths are also formed between the node B and the voltage source VDD, also That is, the subthreshold leakage current formed by transistor P2 and the gate leakage current formed by transistor P1. As the process technology enters deep sub-micron, the leakage current will increase exponentially, and even become the main power consumption source of integrated circuits.

为了解决上述SRAM单元100的漏电流问题，美国专利US7,110,317揭露了一种可以减少SRAM漏电流的技术，如图2所示的美国专利US7,110,317中的SRAM单元501，其晶体管P1、P2是经由偏压电路510(包含晶体管511～513)连接至电压源VDD，且晶体管N1、N2是经由偏压电路520(包含晶体管521～523)连接至电压源VSS。在SRAM单元501位于非运作模式时，其SRAM单元501所连接到的电压源分别为(VDD-Vth)以及(VSS+Vth)(其中Vth为晶体管512～513、522～523的临界电压)，因为节点A、B与电压源之间的电压差降低了，因此可以确实减少漏电流。然而，因为晶体管的临界电压Vth会因为制程、电压、温度(PVT)变异而有所变动，因此，会影响到SRAM单元501于非运作模式时所连接到的电压源(VDD-Vth)以及(VSS+Vth)的电平，并有可能会造成SRAM单元501中数据的遗失。In order to solve the leakage current problem of the above-mentioned SRAM unit 100, U.S. Patent No. 7,110,317 discloses a technology that can reduce the leakage current of SRAM, as shown in FIG. The transistors N1 and N2 are connected to the voltage source VSS through the bias circuit 520 (including transistors 521 - 523 ). When theSRAM unit 501 is in the non-operating mode, the voltage sources connected to theSRAM unit 501 are respectively (VDD-Vth) and (VSS+Vth) (wherein Vth is the threshold voltage of the transistors 512-513, 522-523), Since the voltage difference between the nodes A, B and the voltage source is reduced, the leakage current can indeed be reduced. However, because the threshold voltage Vth of the transistor will vary due to process, voltage, temperature (PVT) variations, it will affect the voltage source (VDD-Vth) and ( VSS+Vth), and may cause data loss inSRAM unit 501.

此外，美国专利US5,581,500亦揭露了一种可以减少漏电流的技术，如图3所示的美国专利US5,581,500的SRAM单元10，其包含一(VSS+Δ)产生器30，当SRAM单元10位于非运作模式时，图3所示的节点A的电压为(VSS+Δ)，因此反向器12、14中储存高电位数据的节点与节点A的电压差会降低，因此可以有效减少漏电流。然而，采用美国专利US5,581,500技术的SRAM阵列会具有很高的制造成本(SRAM阵列中每一列都需要有一个(VSS+Δ)产生器30)，而且(VSS+Δ)产生器30本身亦会有漏电流的现象。In addition, U.S. Patent No. 5,581,500 also discloses a technology that can reduce leakage current. TheSRAM unit 10 of U.S. Patent No. 5,581,500 shown in FIG. When 10 is in the non-operating mode, the voltage of node A shown in FIG. 3 is (VSS+Δ), so the voltage difference between the nodes storing high-potential data ininverters 12 and 14 and node A will decrease, so it can effectively reduce leakage current. However, the SRAM array adopting the technology of U.S. Patent No. 5,581,500 will have a very high manufacturing cost (each column in the SRAM array needs to have a (VSS+Δ) generator 30), and the (VSS+Δ)generator 30 itself is also There will be leakage current.

发明内容Contents of the invention

因此，本发明的目的之一在于提供一种存储器电路以及控制存储器电路的方法，其可以有效降低漏电流且对制程、电压、温度(PVT)变异具有较高的容许量，以解决上述的问题。Therefore, one of the objects of the present invention is to provide a memory circuit and a method for controlling the memory circuit, which can effectively reduce the leakage current and have a higher tolerance for process, voltage, temperature (PVT) variation, so as to solve the above problems .

依据本发明的一实施例，一种存储器电路包含有一第一存储器阵列、一第二存储器阵列以及一开关模块，其中该第一存储器阵列具有一第一端点以及一第二端点，该第二存储器阵列具有一第三端点以及一第四端点，该第一端点耦接于一第一供应电压，该第四端点耦接于小于该第一供应电压的一第二供应电压，该开关模块耦接于该第二端点、该第三端点、该第一供应电压以及该第二供应电压。当该存储器电路操作于一非运作模式时，该开关模块将该第二端点电性连接至该第三端点，且将该第二端点电性阻绝于该第二供应电压，以及将该第三端点电性阻绝于该第一供应电压。According to an embodiment of the present invention, a memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first terminal and a second terminal, and the second The memory array has a third terminal and a fourth terminal, the first terminal is coupled to a first supply voltage, the fourth terminal is coupled to a second supply voltage lower than the first supply voltage, the switch module coupled to the second terminal, the third terminal, the first supply voltage and the second supply voltage. When the memory circuit operates in a non-operating mode, the switch module electrically connects the second terminal to the third terminal, and electrically isolates the second terminal from the second supply voltage, and the third terminal The terminal is electrically isolated from the first supply voltage.

依据本发明的另一实施例，其揭露一种控制一存储器电路的方法，其中该存储器电路包含有一第一存储器阵列以及一第二存储器阵列，该第一存储器阵列具有一第一端点以及一第二端点，该第二存储器阵列具有一第三端点以及一第四端点，该第一端点耦接于一第一供应电压，该第四端点耦接于小于该第一供应电压的一第二供应电压，该方法包含有：当该存储器电路操作于一非运作模式时：将该第二端点电性连接至该第三端点；将该第二端点电性阻绝于该第二供应电压；以及将该第三端点电性阻绝于该第一供应电压。According to another embodiment of the present invention, it discloses a method of controlling a memory circuit, wherein the memory circuit includes a first memory array and a second memory array, the first memory array has a first terminal and a The second terminal, the second memory array has a third terminal and a fourth terminal, the first terminal is coupled to a first supply voltage, and the fourth terminal is coupled to a first supply voltage lower than the first supply voltage two supply voltages, the method comprising: when the memory circuit operates in a non-operating mode: electrically connecting the second terminal to the third terminal; electrically isolating the second terminal from the second supply voltage; and electrically isolating the third terminal from the first supply voltage.

附图说明Description of drawings

图1为已知SRAM单元的示意图。FIG. 1 is a schematic diagram of a known SRAM cell.

图2所示为美国专利US7,110,317中的SRAM单元。Figure 2 shows the SRAM cell in US Patent No. 7,110,317.

图3所示为美国专利US5,581,500中的SRAM单元。Figure 3 shows the SRAM cell in US Patent No. 5,581,500.

图4为依据本发明一实施例的存储器电路的示意图。FIG. 4 is a schematic diagram of a memory circuit according to an embodiment of the invention.

图5为控制信号GP、GN、PI、PB以及端点N2、N3的电压电平VVN、VVP于运作模式以及非运作模式下的示意图。5 is a schematic diagram of the control signals GP, GN, PI, PB and the voltage levels VVN, VVP of the terminals N2, N3 in the operation mode and the non-operation mode.

图6为依据本发明的一实施例的控制存储器电路的方法的流程图。FIG. 6 is a flowchart of a method for controlling a memory circuit according to an embodiment of the invention.

图7为当图4所示的存储器电路操作于非运作模式时的等效电路图。FIG. 7 is an equivalent circuit diagram when the memory circuit shown in FIG. 4 operates in a non-operating mode.

图8为依据本发明另一实施例的存储器电路的示意图。FIG. 8 is a schematic diagram of a memory circuit according to another embodiment of the invention.

图9为依据本发明另一实施例的存储器电路的示意图。FIG. 9 is a schematic diagram of a memory circuit according to another embodiment of the invention.

图10为当存储器电路包含有n个存储器阵列，且存储器电路操作于非运作模式时的等效电路图。FIG. 10 is an equivalent circuit diagram when the memory circuit includes n memory arrays and the memory circuit operates in a non-operating mode.

[主要元件标号说明][Description of main component labels]

  100、501、10100, 501, 10  SRAM单元SRAM cell  N1～N4、P1～P2、511～513、521～523、16、18N1～N4, P1～P2, 511～513, 521～523, 16, 18  晶体管Transistor  WLWL  字组线word line  BLBL  位线bit line  

  

  互补位线Complementary bit line  510、520510, 520  偏压电路Bias circuit  3030  (VSS+Δ)产生器(VSS+Δ)generator  12、1412, 14  反向器Inverter  400、800、900400, 800, 900  存储器电路memory circuit  410、420、810、820、910、920、1000_1～1000_n410, 420, 810, 820, 910, 920, 1000_1～1000_n  存储器阵列memory array  430430  开关模块switch module  SW1、SW2、SW3SW1, SW2,SW3  开关 switch  930930  电压比较器voltage comparator

具体实施方式Detailed ways

请参考图4，图4为依据本发明一实施例的存储器电路400的示意图。如图4所示，存储器电路400包含有存储器阵列410、420、以及一开关模块430，其中存储器阵列410具有一第一端点N1、一第二端点N2，存储器阵列420具有一第三端点N3、一第四端点N4，开关模块430包含有三个开关SW1、SW2、SW3。此外，端点N1耦接于供应电压Vcc、端点N4耦接于供应电压GND、开关SW1耦接于端点N2与供应电压GND之间、开关SW2耦接于端点N2与端点N3之间、且开关SW3耦接于端点N3与供应电压Vcc之间。此外，于本实施例中，存储器阵列410、420为SRAM阵列，亦即存储器阵列410、420分别包含有多个SRAM单元，其中存储器阵列410、420中的SRAM单元与图1所示的SRAM单元类似，所差异的地方仅在于：存储器阵列410中SRAM单元的晶体管N1、N2是连接于端点N2，而非直接连接至供应电压；存储器阵列420中SRAM单元的晶体管P1、P2是连接于端点N3，而非直接连接至供应电压。Please refer to FIG. 4 , which is a schematic diagram of amemory circuit 400 according to an embodiment of the present invention. As shown in FIG. 4, thememory circuit 400 includesmemory arrays 410, 420, and aswitch module 430, wherein thememory array 410 has a first terminal N1 and a second terminal N2, and thememory array 420 has a third terminal N3 , a fourth terminal N4, theswitch module 430 includes three switches SW1, SW2, SW3. In addition, the terminal N1 is coupled to the supply voltage Vcc, the terminal N4 is coupled to the supply voltage GND, the switch SW1 is coupled between the terminal N2 and the supply voltage GND, the switch SW2 is coupled between the terminal N2 and the terminal N3, and the switch SW3 It is coupled between the terminal N3 and the supply voltage Vcc. In addition, in this embodiment, thememory arrays 410, 420 are SRAM arrays, that is, thememory arrays 410, 420 respectively include a plurality of SRAM cells, wherein the SRAM cells in thememory arrays 410, 420 are the same as the SRAM cells shown in FIG. Similarly, the only difference is: the transistors N1 and N2 of the SRAM cells in thememory array 410 are connected to the terminal N2 instead of being directly connected to the supply voltage; the transistors P1 and P2 of the SRAM cells in thememory array 420 are connected to the terminal N3 , rather than connecting directly to the supply voltage.

此外，在图4所示的实施例中，开关SW1、SW2、SW3为互补金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，CMOS)传输门，且开关SW1、SW3是由控制信号GP、GN来控制其导通状态，开关SW2是由控制信号PI、PB来控制其导通状态。In addition, in the embodiment shown in FIG. 4, the switches SW1, SW2, and SW3 are complementary metal-oxide-semiconductor (Complementary Metal-Oxide-Semiconductor, CMOS) transmission gates, and the switches SW1, SW3 are controlled by control signals GP, GN. To control its conduction state, the switch SW2 is controlled by the control signals PI and PB.

请同时参考图4、图5以及图6，图5为控制信号GP、GN、PI、PB以及端点N2、N3的电压电平VVN、VVP于运作模式以及非运作模式下的示意图，图6为依据本发明的一实施例的控制存储器电路400的方法的流程图。请注意，若是有实质上相同的结果，本发明的控制存储器电路400的方法的流程并不以图6所示的执行顺序为限。参考图4～6，流程叙述如下：Please refer to FIG. 4, FIG. 5 and FIG. 6 at the same time. FIG. 5 is a schematic diagram of the control signals GP, GN, PI, PB and the voltage levels VVN and VVP of the terminals N2 and N3 in the operation mode and the non-operation mode. FIG. 6 is A flowchart of a method for controlling thememory circuit 400 according to an embodiment of the present invention. Please note that the flow of the method for controlling thememory circuit 400 of the present invention is not limited to the execution sequence shown in FIG. 6 if substantially the same result is obtained. Referring to Figures 4 to 6, the process is described as follows:

首先，假设目前存储器电路400是操作于一运作模式，亦即存储器电路400目前正在被读取或是写入数据，则于步骤600中，一控制信号产生器(未绘示)产生控制信号GP、GN、PI、PB以控制开关SW1、SW2、SW3的导通状态，其中控制信号GP、PI为低电压电平且控制信号GN、PB为高电压电平，因此，此时开关SW1、SW3为导通状态且开关SW2为非导通状态，且端点N2的电压电平VVN为低电压电平(GND)，且端点N3的电压电平VVP为高电压电平(Vcc)。First, assuming that thememory circuit 400 is currently operating in an operation mode, that is, thememory circuit 400 is currently being read or written, then instep 600, a control signal generator (not shown) generates the control signal GP , GN, PI, PB to control the conduction state of the switches SW1, SW2, SW3, wherein the control signals GP, PI are low voltage levels and the control signals GN, PB are high voltage levels, therefore, at this time, the switches SW1, SW3 is in the conduction state and the switch SW2 is in the non-conduction state, and the voltage level VVN of the terminal N2 is a low voltage level (GND), and the voltage level VVP of the terminal N3 is a high voltage level (Vcc).

接着，于步骤602，存储器电路400由运作模式切换至非运作模式中的待机模式(亦即，图5所示的时间点t₁)，此时，控制信号GP、GN会分别切换至高电压电平以及低电压电平，以将开关SW1、SW3关闭(亦即将端点N2电性隔绝于供应电压GND，且将端点N3电性隔绝于供应电压Vcc)。Next, instep 602, thememory circuit 400 is switched from the operation mode to the standby mode in the non-operation mode (that is, the time point t₁ shown in FIG. level and a low voltage level to close the switches SW1 and SW3 (that is, to electrically isolate the terminal N2 from the supply voltage GND, and to electrically isolate the terminal N3 from the supply voltage Vcc).

接着，于步骤604中，在图5所示的时间点t₂，控制信号PI、PB会分别切换至高电压电平以及低电压电平，以将开关SW2导通(亦即将端点N2电性连接于端点N3)。在开关SW2导通之后，端点N2、N3的电压电平逐渐变成0.5*Vcc，而此时，图4所示的存储器电路400的等效电路可以如图7所示，存储器阵列410、420的跨压分别为0.5*Vcc，亦即存储器阵列410、420中每一个SRAM单元的轨对轨电压(rail-to-rail voltage)为0.5*Vcc，因此，可以确实降低SRAM单元的漏电流。Next, instep 604, at the time point_t2 shown in FIG. at endpoint N3). After the switch SW2 is turned on, the voltage levels of the terminals N2 and N3 gradually become 0.5*Vcc. At this time, the equivalent circuit of thememory circuit 400 shown in FIG. 4 can be shown in FIG. The cross-voltage of each SRAM cell is 0.5*Vcc, that is, the rail-to-rail voltage (rail-to-rail voltage) of each SRAM cell in thememory arrays 410, 420 is 0.5*Vcc, therefore, the leakage current of the SRAM cell can be reduced indeed.

在步骤606中，存储器电路400准备由非运作模式切换至运作模式时，控制信号PI、PB会先分别切换至低电压电平以及高电压电平，以将开关SW2关闭，之后控制信号GP、GN再分别切换至低电压电平以及高电压电平，以将开关SW1、SW3导通以进入唤醒模式(如图5所示的时间点t₃)。在进入唤醒模式之后的一段时间，端点N2的电压电平VVN会回到低电压电平(GND)，且端点N 3的电压电平VVP会回到高电压电平(Vcc)，此时存储器电路400进入运作模式(如图5所示的时间点t₄)。Instep 606, when thememory circuit 400 is ready to switch from the non-operation mode to the operation mode, the control signals PI and PB will be switched to a low voltage level and a high voltage level respectively to close the switch SW2, and then the control signals GP, GN is then switched to a low voltage level and a high voltage level respectively to turn on the switches SW1 and SW3 to enter the wake-up mode (time point t₃ shown in FIG. 5 ). After entering the wake-up mode for a period of time, the voltage level VVN of the terminal N2 will return to the low voltage level (GND), and the voltage level VVP of the terminal N3 will return to the high voltage level (Vcc), at this time the memory Thecircuit 400 enters the operation mode (time point t₄ as shown in FIG. 5 ).

此外，为了降低本体效应(body effect)，于图8所示本发明的另一实施例中，图8所示的存储器电路800与图4所示的存储器电路400类似，其差异只在于存储器电路800中MOS元件的N型井与P型井的连接方式。如图8所示，存储器阵列810中每个MOS元件的N型井是连接至供应电压Vcc、P型井则连接至端点N2；存储器阵列820中每个MOS元件的N型井是连接至端点N3、P型井则连接至供应电压GND；开关SW1的P型井连接至供应电压GND、N型井连接至端点N3；开关SW3的N型井连接至供应电压Vcc、P型井连接至端点N2。In addition, in order to reduce the body effect, in another embodiment of the present invention shown in FIG. 8, thememory circuit 800 shown in FIG. 8 is similar to thememory circuit 400 shown in FIG. 4, and the only difference is that the memory circuit The connection mode between the N-type well and the P-type well of the MOS element in 800. As shown in Figure 8, the N-type well of each MOS element in thememory array 810 is connected to the supply voltage Vcc, and the P-type well is connected to the terminal N2; the N-type well of each MOS element in thememory array 820 is connected to the terminal N3 and the P-type well are connected to the supply voltage GND; the P-type well of the switch SW1 is connected to the supply voltage GND, and the N-type well is connected to the terminal N3; the N-type well of the switch SW3 is connected to the supply voltage Vcc, and the P-type well is connected to the terminal N2.

此外，在图4所示的实施例中，开关SW1、SW2、SW3为CMOS传输门，然而，于本发明的其它实施例中，开关SW1、SW2、SW3可以用其它具有类似功能的半导体元件来实作，这些设计上的变化均应隶属于本发明的范畴。In addition, in the embodiment shown in FIG. 4, the switches SW1, SW2, and SW3 are CMOS transmission gates. However, in other embodiments of the present invention, the switches SW1, SW2, and SW3 can be implemented by other semiconductor elements with similar functions. In practice, these design changes should fall within the scope of the present invention.

此外，在图4～6所示的实施例中，当存储器电路400由运作模式切换为非运作模式时，开关SW1、SW3要先关闭(图5所示的时间点t₁)，之后过一段时间等到端点N2、N3的电压电平VVN、VVP比较接近的时候(因为端点N3的电压电平VVP会因为漏电流而逐渐下降、以及端点N2的电压电平VVN会因为漏电流而逐渐上升)才将开关SW2导通(图6所示的时间点t₂)，如此一来可以避免过射现象(overshoot/undershoot)或是有电流尖峰(current spike)发生而影响到存储器阵列410、420中的数据。至于如何决定将开关SW2导通的时间点t₂，大致上可以有以下两种方式：一、在开关SW1、SW3关闭后的一固定时间，将开关SW2导通，亦即图5所示的时间点t₁、t₂之间的差距为一固定值；二、使用一检测电路来检测端点N2、N3中至少一端点的电压电平来判断何时将开关SW2导通，以下图9所示的实施例将说明使用检测电路来判断何时将开关SW2导通。In addition, in the embodiments shown in FIGS. 4-6, when thememory circuit 400 is switched from the operation mode to the non-operation mode, the switches SW1 and SW3 should be closed first (time point t₁ shown in FIG. Wait until the voltage levels VVN and VVP of the terminals N2 and N3 are relatively close (because the voltage level VVP of the terminal N3 will gradually decrease due to the leakage current, and the voltage level VVN of the terminal N2 will gradually increase due to the leakage current) The switch SW2 is turned on (time point t₂ shown in FIG. 6 ), so as to prevent overshoot/undershoot or current spikes from affecting thememory arrays 410 and 420 The data. As for how to determine the time point_t2 for turning on the switch SW2, there are generally two ways as follows: 1. Turn on the switch SW2 for a fixed time after the switches SW1 and SW3 are turned off, that is, as shown in Fig. 5 The difference between the time points_t1 and_t2 is a fixed value; 2. Use a detection circuit to detect the voltage level of at least one of the terminals N2 and N3 to determine when to turn on the switch SW2, as shown in Figure 9 below The illustrated embodiment will illustrate the use of a detection circuit to determine when to turn on switch SW2.

请参考图9，图9为依据本发明另一实施例的存储器电路900的示意图。如图9所示，存储器电路900包含有存储器阵列910、920、一检测电路(于本实施例中，是以一电压比较器930为例)、以及三个开关SW1、SW2、SW3，其中存储器阵列910具有一第一端点N1、一第二端点N2，存储器阵列920具有一第三端点N3、一第四端点N4。此外，端点N1耦接于供应电压Vcc、端点N4耦接于供应电压GND、开关SW1耦接于端点N2与供应电压GND之间、开关SW2耦接于端点N2与端点N3之间、且开关SW3耦接于端点N3与供应电压Vcc之间。Please refer to FIG. 9 , which is a schematic diagram of amemory circuit 900 according to another embodiment of the present invention. As shown in Figure 9, thememory circuit 900 includesmemory arrays 910, 920, a detection circuit (in this embodiment, avoltage comparator 930 is taken as an example), and three switches SW1, SW2, SW3, wherein the memory Thearray 910 has a first terminal N1 and a second terminal N2, and thememory array 920 has a third terminal N3 and a fourth terminal N4. In addition, the terminal N1 is coupled to the supply voltage Vcc, the terminal N4 is coupled to the supply voltage GND, the switch SW1 is coupled between the terminal N2 and the supply voltage GND, the switch SW2 is coupled between the terminal N2 and the terminal N3, and the switch SW3 It is coupled between the terminal N3 and the supply voltage Vcc.

存储器电路900与图4所示的存储器电路400的架构类似，所差异的地方仅在于存储器电路900中用来控制开关SW2的控制信号PI、PB是由电压比较器930比较端点N2、N3的电压电平VVN、VVP而产生。详细来说，当电压电平VVP大于电压电平VVN时，电压比较器930所产生的控制信号PI、PB分别为低电压电平以及高电压电平，亦即开关SW2为非导通状态；而当电压电平VVP小于电压电平VVN时，电压比较器930所产生的控制信号PI、PB分别为高电压电平以及低电压电平，亦即开关SW2为导通状态。The structure of thememory circuit 900 is similar to that of thememory circuit 400 shown in FIG. Level VVN, VVP generated. In detail, when the voltage level VVP is greater than the voltage level VVN, the control signals PI and PB generated by thevoltage comparator 930 are at a low voltage level and a high voltage level respectively, that is, the switch SW2 is in a non-conductive state; And when the voltage level VVP is lower than the voltage level VVN, the control signals PI and PB generated by thevoltage comparator 930 are at a high voltage level and a low voltage level respectively, that is, the switch SW2 is turned on.

此外，虽然于上述图4、8、9所示的实施例中，存储器电路仅具有两个存储器阵列，然而，于本发明的其它实施例中，存储器电路可以包含有多个存储器阵列，只要存储器电路操作在一非运作模式时，其等效电路可以如图10所示的n个迭接存储器阵列(存储器阵列1000_1～1000_n)，使得每个存储器阵列的跨压为(1/n)Vcc，这些设计上的变化均应隶属于本发明的范畴。In addition, although in the above-mentioned embodiments shown in FIGS. When the circuit operates in a non-operating mode, its equivalent circuit can be n consecutive memory arrays (memory arrays 1000_1-1000_n) as shown in FIG. 10 , so that the cross voltage of each memory array is (1/n)Vcc, These design changes should all belong to the category of the present invention.

简要归纳本发明，于本发明的存储器电路以及控制存储器电路的方法中，当存储器电路操作于非运作模式时，两个存储器阵列为形成一个堆栈架构，而使得每一个存储器阵列的跨压只有当存储器电路操作于运作模式时的一半，如此一来，便可以有效地降低存储器阵列中每一个存储器单元于非运作模式时的漏电流。此外，本发明的存储器电路具有简单的架构，且对制程、电压、温度(PVT)变异具有较高的容许量。To briefly summarize the present invention, in the memory circuit and the method for controlling the memory circuit of the present invention, when the memory circuit operates in the non-operating mode, the two memory arrays form a stack structure, so that the cross voltage of each memory array is only when The operation of the memory circuit is half of the operating mode, so that the leakage current of each memory cell in the memory array in the non-operating mode can be effectively reduced. In addition, the memory circuit of the present invention has a simple structure and has high tolerance to process, voltage, temperature (PVT) variation.

以上所述仅为本发明的较佳实施例，凡依本发明权利要求范围所做的均等变化与修饰，皆应属本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (11)

Translated fromChinese

1.一种存储器电路，包含有：1. A memory circuit comprising:一第一静态随机存取存储器阵列，其具有一第一端点以及一第二端点，其中该第一端点耦接于一第一供应电压；A first static random access memory array, which has a first terminal and a second terminal, wherein the first terminal is coupled to a first supply voltage;一第二静态随机存取存储器阵列，其具有一第三端点以及一第四端点，其中该第四端点耦接于小于该第一供应电压的一第二供应电压；以及A second SRAM array having a third terminal and a fourth terminal, wherein the fourth terminal is coupled to a second supply voltage less than the first supply voltage; and一开关模块，耦接于该第一静态随机存取存储器阵列的该第二端点、该第二静态随机存取存储器阵列的该第三端点、该第一供应电压以及该第二供应电压；a switch module, coupled to the second terminal of the first SRAM array, the third terminal of the second SRAM array, the first supply voltage, and the second supply voltage;其中当该存储器电路操作于一非运作模式时，该开关模块将该第二端点电性连接至该第三端点，且将该第二端点电性阻绝于该第二供应电压，以及将该第三端点电性阻绝于该第一供应电压；以及当该存储器电路操作于一运作模式时，该开关模块将该第二端点电性阻绝于该第三端点，且将该第二端点电性连接至该第二供应电压，以及将该第三端点电性连接至该第一供应电压；Wherein when the memory circuit operates in a non-operating mode, the switch module electrically connects the second terminal to the third terminal, and electrically isolates the second terminal from the second supply voltage, and the first terminal is electrically isolated from the second supply voltage. Three terminals are electrically isolated from the first supply voltage; and when the memory circuit operates in an operation mode, the switch module electrically isolates the second terminal from the third terminal and electrically connects the second terminal to the second supply voltage, and electrically connect the third terminal to the first supply voltage;其中该开关模块包含有：The switch module includes:一第一开关，耦接于该第二端点与该第二供应电压之间；a first switch, coupled between the second terminal and the second supply voltage;一第二开关，耦接于该第二端点与该第三端点之间；以及a second switch, coupled between the second terminal and the third terminal; and一第三开关，耦接于该第三端点与该第一供应电压之间；a third switch, coupled between the third terminal and the first supply voltage;其中当该存储器电路自该运作模式切换至该非运作模式时，该第一开关以及该第三开关由导通状态切换至非导通状态，以及该第二开关由非导通状态切换至导通状态，其中该第二开关由非导通状态切换至导通状态的切换时间点晚于该第一开关以及该第三开关由导通状态切换至非导通状态的切换时间点。Wherein when the memory circuit is switched from the operation mode to the non-operation mode, the first switch and the third switch are switched from the conduction state to the non-conduction state, and the second switch is switched from the non-conduction state to the conduction state. The switching time point of the second switch from the non-conducting state to the conducting state is later than the switching time point of the first switch and the third switch from the conducting state to the non-conducting state.2.根据权利要求1所述的存储器电路，其中当该存储器电路自该非运作模式切换至该运作模式时，该第一开关以及该第三开关由非导通状态切换至导通状态，以及该第二开关由导通状态切换至非导通状态，其中该第二开关由导通状态切换至非导通状态的切换时间点早于该第一开关以及该第三开关由非导通状态切换至导通状态的切换时间点。2. The memory circuit according to claim 1, wherein when the memory circuit is switched from the non-operation mode to the operation mode, the first switch and the third switch are switched from a non-conductive state to a conductive state, and The second switch is switched from the conduction state to the non-conduction state, wherein the switching time point of the second switch from the conduction state to the non-conduction state is earlier than that of the first switch and the third switch from the non-conduction state The switching time point for switching to the on state.3.根据权利要求1所述的存储器电路，还包含有：3. The memory circuit according to claim 1, further comprising:一检测电路，耦接于该第二端点、第三端点以及该第二开关，用来依据该第二端点与该第三端点中至少一端点的电压电平，以产生一控制信号来控制该第二开关的导通状态。A detection circuit, coupled to the second terminal, the third terminal and the second switch, is used to generate a control signal to control the voltage level of at least one of the second terminal and the third terminal The conduction state of the second switch.4.根据权利要求3所述的存储器电路，其中该检测电路比较该第二端点与第三端点的电压电平来产生该控制信号。4. The memory circuit according to claim 3, wherein the detection circuit compares the voltage levels of the second terminal and the third terminal to generate the control signal.5.根据权利要求4所述的存储器电路，其中当该检测电路检测到该第二端点的电压电平大于该第三端点的电压电平时，该检测电路产生该控制信号以将该第二开关由非导通状态切换至导通状态。5. The memory circuit according to claim 4, wherein when the detection circuit detects that the voltage level of the second terminal is greater than the voltage level of the third terminal, the detection circuit generates the control signal to switch the second switch from a non-conductive state to a conductive state.6.根据权利要求1所述的存储器电路，其中该第一开关以及该第三开关为互补金属氧化物半导体传输门，且该第一开关的N型井连接至该第三端点，且该第三开关的P型井连接至该第二端点。6. The memory circuit according to claim 1, wherein the first switch and the third switch are CMOS transmission gates, and the N-type well of the first switch is connected to the third terminal, and the first switch The P-well of the three switches is connected to the second terminal.7.一种控制一存储器电路的方法，该存储器电路包含有一第一静态随机存取存储器阵列以及一第二静态随机存取存储器阵列，该第一静态随机存取存储器阵列具有一第一端点以及一第二端点，该第二静态随机存取存储器阵列具有一第三端点以及一第四端点，该第一端点耦接于一第一供应电压，该第四端点耦接于小于该第一供应电压的一第二供应电压，该方法包含有：7. A method of controlling a memory circuit comprising a first SRAM array and a second SRAM array, the first SRAM array having a first endpoint and a second terminal, the second static random access memory array has a third terminal and a fourth terminal, the first terminal is coupled to a first supply voltage, the fourth terminal is coupled to a voltage smaller than the first A second supply voltage of a supply voltage, the method comprising:当该存储器电路操作于一非运作模式时：When the memory circuit operates in a non-operational mode:将该第二端点电性连接至该第三端点；electrically connecting the second terminal to the third terminal;将该第二端点电性阻绝于该第二供应电压；以及electrically isolating the second terminal from the second supply voltage; and将该第三端点电性阻绝于该第一供应电压；electrically isolating the third terminal from the first supply voltage;当该存储器电路操作于一运作模式时：When the memory circuit operates in an operation mode:将该第二端点电性阻绝于该第三端点；electrically isolating the second terminal from the third terminal;将该第二端点电性连接至该第二供应电压；以及electrically connecting the second terminal to the second supply voltage; and将该第三端点电性连接至该第一供应电压；以及electrically connecting the third terminal to the first supply voltage; and当该存储器电路自该运作模式切换至该非运作模式时，将该第二端点电性连接于该第三端点的时间点是晚于该第二端点由电性阻绝至该第二供应电压，以及将该第二端点电性连接于该第三端点的时间点亦晚于该第三端点电性阻绝至该第一供应电压的时间点。When the memory circuit switches from the operation mode to the non-operation mode, the time point at which the second terminal is electrically connected to the third terminal is later than the second terminal is electrically blocked to the second supply voltage, And the time point at which the second terminal is electrically connected to the third terminal is also later than the time point at which the third terminal is electrically isolated from the first supply voltage.8.根据权利要求7所述的方法，还包含有：8. The method of claim 7, further comprising:当该存储器电路自该非运作模式切换至该运作模式时，将该第二端点电性阻绝于该第三端点的时间点是早于该第二端点由电性连接至该第二供应电压的时间点，以及将该第二端点电性阻绝于该第三端点的时间点亦早于该第三端点电性连接至该第一供应电压的时间点。When the memory circuit switches from the non-operating mode to the operating mode, the time point at which the second terminal is electrically isolated from the third terminal is earlier than when the second terminal is electrically connected to the second supply voltage The time point and the time point at which the second terminal is electrically isolated from the third terminal are also earlier than the time point at which the third terminal is electrically connected to the first supply voltage.9.根据权利要求7所述的方法，还包含有：9. The method of claim 7, further comprising:依据该第二端点与该第三端点中至少一端点的电压电平，以产生一控制信号来控制该第二端点电性连接或是电性阻绝于该第三端点。According to the voltage level of at least one of the second terminal and the third terminal, a control signal is generated to control the second terminal to be electrically connected to or electrically isolated from the third terminal.10.根据权利要求9所述的方法，其中依据该第二端点与该第三端点中至少一端点的电压电平以产生该控制信号的步骤包含有：10. The method according to claim 9, wherein the step of generating the control signal according to the voltage level of at least one of the second terminal and the third terminal comprises:比较该第二端点与第三端点的电压电平来产生该控制信号。The control signal is generated by comparing the voltage levels of the second terminal and the third terminal.11.根据权利要求10所述的方法，其中当该第二端点的电压电平大于该第三端点的电压电平时，产生该控制信号以控制该第二端点电性连接于该第三端点。11. The method according to claim 10, wherein when the voltage level of the second terminal is higher than the voltage level of the third terminal, the control signal is generated to control the second terminal to be electrically connected to the third terminal.

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