CN102110689A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofDownload PDFInfo
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- CN102110689A CN102110689ACN2009102441309ACN200910244130ACN102110689ACN 102110689 ACN102110689 ACN 102110689ACN 2009102441309 ACN2009102441309 ACN 2009102441309ACN 200910244130 ACN200910244130 ACN 200910244130ACN 102110689 ACN102110689 ACN 102110689A
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Abstract
Translated fromChinese
Description
Technical field
The present invention relates generally to a kind of semiconductor device and manufacture method thereof, specifically, relate to a kind of high-k gate dielectric/metal gate device and manufacture method thereof based on the grid alternative techniques.
Background technology
Along with development of semiconductor, have more high-performance and the bigger component density of more powerful integrated circuit requirement, and between each parts, element or size, size and the space of each element self needs also further to dwindle.22 nanometers and following technology lsi core The Application of Technology have become the inexorable trend of integrated circuit development, also are one of problems of competitively researching and developing of main in the world semiconductor company and research organization.With " high-k gate dielectric/metal gate " technology is that the cmos device grid engineering research of core is a most representative core process in 22 nanometers and the following technology, and associated material, technology and structural research are in carrying out widely.At present, research at high-k gate dielectric/metal gate technique can probably be divided into both direction, grid technique and grid alternative techniques promptly, before the source that is formed on of the grid of preceding grid technique, drain electrode generate, then after source, drain electrode generated, grid did not need to bear very high annealing temperature in this technology in the formation of the grid of grid alternative techniques.
For MOS device with high k/ metal-gate structures, the physics of high-k gate dielectric and electrology characteristic directly have influence on the performance of device, as equivalent oxide thickness (EOT, Equivalent OxideThickness) and threshold voltage optimization etc., and when carrying out high-k gate dielectric and the integrated research of metal gate process, fermi level pinning effect and interface dipole problem have occurred, these problems all directly have influence on the threshold voltage adjustments of device.Therefore, how to optimize high-k gate dielectric and with the metal gate integrated technique, and effectively control threshold voltage and become a key issue that improves the device overall performance.At present, at high-k gate dielectric in the grid alternative techniques and metal gate research, common way is with a kind of high-k gate dielectric material and different kinds of metals grid at nmos area territory and PMOS area deposition, to reach the purpose that reduces EOT and control device threshold voltage, for example the 45nm grid alternative techniques of Intel Company and 32nm grid alternative techniques.But the problem of bringing thus is that identical high-k gate dielectric can produce different influences, the electronic carrier mobility in the nmos device of especially can degenerating with holoe carrier to the electronic carrier in the nmos device PMOS device.
Therefore, the needs proposition is a kind of can to reduce the EOT of device and the threshold voltage of effective control device, and the semiconductor device of the electronic carrier mobility of the nmos device of can not degenerating.
Summary of the invention
In view of the above problems, the invention provides a kind of semiconductor device, described device comprises: have the Semiconductor substrate in nmos area territory and PMOS zone, wherein said nmos area territory and described PMOS zone are isolated mutually by isolated area; Be formed at that the first grid on the described nmos area territory is piled up and second grid that are formed on the described PMOS zone pile up; Wherein, the described first grid is piled up and is comprised: first boundary layer; The first high-k gate dielectric layer on described first boundary layer; First metal gate layers on the described first high-k gate dielectric layer; Described second grid pile up and comprise: the second contact surface layer; The second high-k gate dielectric layer on described second contact surface layer; Second metal gate layers on the described second high-k gate dielectric layer; The wherein said first and second high-k gate dielectric layers adopt the oxide material that contains n type metal to form, and the dielectric constant of the oxide of described n type metal is higher than SiO2, and comprise rare earth and class thulium in the formation material of the described first high-k gate dielectric layer, comprise other reactive metal elements except that rare earth and class thulium in the formation material of the described second high-k gate dielectric layer.The thickness of the described first and second high-k gate dielectric layers is about 1 to 10 nanometer, is preferably about 1 to 5 nanometer, and optimum is about 1 to 3 nanometer.Select unit usually to form the group of described first high-k gate dielectric layer column element under comprising: La2O3, HfLaOx, HfLaONx, HfLaSiOx, Y2O3And Sc2O3, and their combination.Select unit usually to form the group of described second high-k gate dielectric layer column element under comprising: Al2O3, HfAlOx, MgO2, TiO2, HfTiOx, HfSiTiOxAnd HfMgOx, and their combination.
The present invention also provides a kind of method of making described semiconductor device, and described method comprises: the Semiconductor substrate with nmos area territory and PMOS zone is provided, and wherein said nmos area territory and described PMOS zone are isolated mutually by isolated area; On described Semiconductor substrate, formation belongs to first boundary layer in nmos area territory, false grid and side wall thereof, formation belongs to the second contact surface layer in PMOS zone, false grid and side wall thereof, and in described Semiconductor substrate, form respectively and belong to the source area and the drain region in nmos area territory and PMOS zone, and cover source area, drain region and the nmos area territory in described NMOS and PMOS zone and the isolated area in PMOS zone forms inner layer dielectric layer; Remove the false grid in described nmos area territory and PMOS zone, to form first opening and second opening; In described first opening, form the first high-k gate dielectric layer that covers described first boundary layer, and in described second opening, form to cover the second high-k gate dielectric layer of described second contact surface layer, the wherein said first and second high-k gate dielectric layers adopt the oxide material that contains n type metal to form, and the dielectric constant of the oxide of described n type metal is higher than SiO2, and comprise rare earth and class thulium in the formation material of the described first high-k gate dielectric layer, comprise other reactive metal elements except that rare earth and class thulium in the formation material of the described second high-k gate dielectric layer; On the first high-k gate dielectric layer, form first metal gate layers, on the second high-k gate dielectric layer, form second metal gate layers; Described device is processed, and the first grid belong to the nmos area territory is piled up and second grid that belong to the PMOS zone pile up to form respectively.The thickness of the described first and second high-k gate dielectric layers is about 1 to 10 nanometer, is preferably about 1 to 5 nanometer, and optimum is about 1 to 3 nanometer.
By adopting the device of grid alternative techniques preparation, described device is respectively at the high-k gate dielectric material of nmos device zone and PMOS device area introducing different materials, so not only reduced the EOT value of nmos device and PMOS device respectively, effectively control the threshold voltage of nmos device and PMOS device, also reduced the degeneration of nmos device electronic carrier mobility.
Description of drawings
Fig. 1 shows the structural representation of semiconductor device according to an embodiment of the invention;
Fig. 2 shows the flow chart of the manufacture method of semiconductor device according to an embodiment of the invention;
Fig. 3-13 shows the schematic diagram of each fabrication stage of semiconductor device according to an embodiment of the invention.
Embodiment
The present invention relates generally to a kind of semiconductor device and manufacture method thereof, specifically, relate in particular to a kind of high-k gate dielectric/metal gate device and manufacture method thereof of the interface optimization based on the grid alternative techniques.Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.
With reference to figure 1, Fig. 1 shows the structural representation according to the semiconductor device of the embodiment of the invention.As shown in Figure 1, described device comprises: have theSemiconductor substrate 200 innmos area territory 201 andPMOS zone 202, wherein saidnmos area territory 201 is isolated byisolated area 208 mutually with describedPMOS zone 202; Be formed at the first grid on the describednmos area territory 201 pile up 300 and second grid that are formed on the describedPMOS zone 202 pile up 400; Wherein, the described first grid is piled up 300 and is comprised:first boundary layer 210; The first high-k gatedielectric layer 222 on describedfirst boundary layer 210; Firstmetal gate layers 226 on the described first high-k gatedielectric layer 222; Described second grid pile up 400 and comprise: secondcontact surface layer 210; The second high-k gatedielectric layer 224 on described secondcontact surface layer 210; Secondmetal gate layers 228 on the described second high-k gatedielectric layer 224; The wherein said first and second high-k gate dielectric layers adopt the oxide material that contains n type metal to form, and the dielectric constant of the oxide of described n type metal is higher than SiO2, and comprise rare earth and class thulium in the formation material of the described first high-k gate dielectric layer, comprise other reactive metal elements except that rare earth and class thulium in the formation material of the described second high-k gate dielectric layer.Wherein said first metal gate layers and second metal gate layers are same material.
Describe manufacturing and the realization of described embodiment in detail below with reference to Fig. 2, Fig. 2 shows the flow chart according to the manufacture method of the semiconductor device of the embodiment of the invention.
Then, in step 102, extremely shown in Figure 7 as Fig. 3, on describedSemiconductor substrate 200, formation belongs tofirst boundary layer 210 innmos area territory 201,false grid 212 andside wall 214 thereof, formation belongs to the secondcontact surface layer 210 in PMOS zone,false grid 212 andside wall 214 thereof, and in describedSemiconductor substrate 200, form the source belong tonmos area territory 201 respectively, the source indrain region 204 andPMOS zone 202,drain region 206, and cover the source in describednmos area territory 201, the source in drainregion 204 andPMOS zone 202, theisolated area 208 in drainregion 206 andnmos area territory 201 andPMOS zone 202 forms inner layerdielectric layer 216.
Specifically,deposition interface layer 210 onSemiconductor substrate 200 at first, as shown in Figure 3.Describedboundary layer 210 can be SiONx, the thickness of describedboundary layer 210 is about 0.3 to 3 nanometer, is preferably about 0.3 to 1 nanometer, optimum is about 0.3 to 0.7 nanometer.On describedboundary layer 210, depositfalse grid 212 then, as shown in Figure 4.Describedfalse grid 212 can be amorphous silicon or polysilicon.In one embodiment,false grid 212 comprise amorphous silicon.Then utilize graphical describedboundary layer 210 of dry method or wet etching technique and describedfalse grid 212, belong tofirst boundary layer 210 and thefalse grid 212 innmos area territory 201 and secondcontact surface layer 210 and thefalse grid 212 that belong toPMOS zone 202 respectively thereby form, as shown in Figure 5.The thickness of describedfalse grid 212 is about 20 to 200 nanometers, is preferably about 20 to 70 nanometers, and optimum is 20 to 50 nanometers.
Then, cover describedfalse grid 212 sidewalls and form side wall 214.Side wall 214 can be by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low K dielectrics material and combination thereof, and/or other suitable materialsform.Side wall 214 can have sandwichconstruction.Side wall 214 can form by the method that comprises the dielectric substance that atomic deposition method, plasma reinforced chemical meteorology deposition or additive method deposition are suitable.In one embodiment,side wall 214 is a three-decker, and forming the first side wall layer 214-1 successively by deposition, etching is Si3N4, the second side wall layer 214-2 is SiO2With the 3rd side wall layer 214-3 be Si3N4, as shown in Figure 6.This only is as example, is not limited to this.In order to simplify description, in description after this, comprise that the three-decker side wall of the described first side wall layer 214-1, the second side wall layer 214-2, the 3rd side wall layer 214-3 all is described asside wall 214.
Source/drain region 204,206 can be by the transistor arrangement according to expectation, injects p type or n type alloy or impurity and forms to thesubstrate 200 innmos area territory 201 andPMOS zone 202, as shown in Figure 6.Source/drain region 204,206 can be by comprising that photoetching, ion inject, spread and/or the method for other appropriate process forms.
As shown in Figure 7, deposition forms inner layer dielectric layer (ILD) 216 on thesubstrate 200 between theside wall 214 in theside wall 214 in describednmos area territory 201 and PMOS zone 202.Described inner layer dielectric layer (ILD) 216 can be but be not limited to for example unadulterated silica (SiO2), the silica (as Pyrex, boron-phosphorosilicate glass etc.) and the silicon nitride (Si that mix3N4).Described inner layerdielectric layer 216 for example can use, and chemical vapor deposition (CVD), physical vapor deposition (PVD), ald (ALD) and/or other suitable methods such as technology form.Described inner layer dielectric layer can have sandwich construction.In one embodiment, the thickness range of inner layerdielectric layer 216 is about 20 to 90 nanometers.To described interlayerdielectric layer 216 and describedside wall 214 planarization to expose the upper surface of describedfalse grid 212.
Then, in step 103, as shown in Figure 8,false grid 212 are removed in this step, to form first opening 218 and second opening 220.False grid 212 can use wet etching and/or dry ecthing to remove.In one embodiment, wet etching process comprises Tetramethylammonium hydroxide (TMAH), KOH or other suitable etch agent solutions.
Then, in step 104, as shown in Figure 9, in describedfirst opening 218, form the first high-k gatedielectric layer 222 that covers described first boundary layer 210.Cover described device and deposit the first high-k gatedielectric layer 222, as HfLaOxOn the first high-k gatedielectric layer 222 innmos area territory 201, form mask protection layer (not shown) then; then carrying out the first high-k gatedielectric layer 222 that photoetching will belong toPMOS zone 202 etches away; again the mask protection layer on the first high k gatedielectric layer 222 innmos area territory 201 is etched away; and stop on the first high k gatedielectric layer 222; thereby form the first high-k gatedielectric layer 222 that belongs to the nmos area territory, as shown in Figure 9.The thickness of the described first high-k gatedielectric layer 222 is about 1 to 10 nanometer, is preferably about 1 to 5 nanometer, and optimum is 1 to 3 nanometer.The deposition of the described first high-k gate dielectric layer can adopt sputter, PLD, MOCVD, ALD, PEALD or other suitable methods.Comprise the element that can regulate the nmos device threshold voltage in the formation material of the described first high-k gatedielectric layer 222, as rare earth and class thuliums such as La, Y, Sc, Gd, described metal oxide is that n type metal oxide and dielectric constant are higher than SiO2Dielectric constant, the described first high-k gatedielectric layer 222 can be by selecting one or more to form in the material that comprises these elements: La2O3, HfLaONx, HfLaSiOx, Y2O3And Sc2O3Deng.Owing to comprise the element that can form the interface dipole in the first high-k gatedielectric layer 222 withfirst boundary layer 210 below it, can effectively regulate the threshold voltage of nmos device, in addition, owing to do not had in the nmos device district can to improve the mobility of nmos device to a certain extent owing to spread elements such as the Al that causes the channel carrier mobil-ity degradation or Ti.
Then, in step 105, as shown in figure 10, in describedsecond opening 220, form the second high-k gatedielectric layer 224 that covers described second contact surface layer 210.Cover described device and deposit the second high-k gatedielectric layer 224, as HfAlOxOn the second high-k gatedielectric layer 224 on thePMOS zone 202, form mask protection layer (not shown) then; carrying out photoetching then etches away the second high-k gatedielectric layer 224 on the first high-k gatedielectric layer 222 innmos area territory 201; again the mask protection layer on the second high k gatedielectric layer 224 inPMOS zone 202 is etched away; and stop on the second high k gatedielectric layer 224; thereby form the second high-k gatedielectric layer 224 that belongs toPMOS zone 202, as shown in figure 10.The thickness of the described second high-k gatedielectric layer 224 is about 1 to 10 nanometer, is preferably about 1 to 5 nanometer, and optimum is 1 to 3 nanometer.The deposition of the described second high-k gate dielectric material layer can adopt sputter, PLD, MOCVD, ALD, PEALD or other suitable methods.The described second highK medium layer 224 comprises the element that can regulate the PMOS device threshold voltage, and as non-rare earth and class thulium reactive metal elements in addition such as Al, Mg, Ti, described metal oxide is that n type metal oxide and dielectric constant all are higher than SiO2Dielectric constant, the described second highK medium layer 224 can be by selecting one or more to form in the material that comprises these elements: Al2O3, HfAlOx, MgO2, TiO2, HfTiOx, HfSiTiOxAnd HfMgOxDeng.Owing to comprise the element that can form the interface dipole in the second highK medium layer 224, can effectively regulate the threshold voltage of PMOS device with the secondcontact surface layer 210 below it.
After this, can further process described device according to making needs.To shown in Figure 12, on the first high-k gatedielectric layer 222 and the second high-k gatedielectric layer 224, form firstmetal gate layers 226 and secondmetal gate layers 228 as Figure 11 respectively.Described firstmetal gate layers 226 and secondmetal gate layers 228 are one or more layers structure, the employing same material forms, the work function of the material of described first and second metal gate layers is generally work function value between silicon ribbon, can select one or more elements to deposit from the group that comprises following column element: TiN, TaN, MoN, HfN, HfC, TaC, TiC, MoC, TiAlN, TaAlN, HfAlN, HfTbN, TaTbN, TaErN, TaYbN, TaSiN, TaHfN, TiHfN, HfSiN, MoSiN, MoAlN, RuTax, NiTax, polysilicon and metal silicide, and their combination.In one embodiment, described firstmetal gate layers 226 and described secondmetal gate layers 228 are double-layer structure.Sedimentary facies metal material together on the first high-k gatedielectric layer 222 and the second high-k gatedielectric layer 224 as TiN, forms the first metal layer 226-1 that belongs tonmos area territory 201 and the second metal level 228-1 that belongs toPMOS zone 202, as shown in figure 11.Then, as shown in figure 12, on described second metal level 228-1 and the first metal layer 226-1, deposit low resistive metal, as TiAl, described low resistive metal fills up described first opening 218 and second opening 220 and covers inner layerdielectric layer 216, the first low resistance metal layer 226-2 and the second low resistance metal layer 228-2 that belongs toPMOS zone 202 that belong tonmos area territory 201 with formation, as shown in figure 12, thereby form firstmetal gate layers 226 that comprises the first metal layer 226-1 and the first low resistance metal layer 226-2, and secondmetal gate layers 228 that comprises the second metal level 228-1 and the second low resistance metal layer 228-2, this only is as example, be not limited to this, firstmetal gate layers 226 and secondmetal gate layers 228 can also be the sandwich constructions that comprises other metal materials.The deposition of described firstmetal gate layers 226 and secondmetal gate layers 228 can adopt sputter, PLD, MOCVD, ALD, PEALD or other suitable methods.
At last, as shown in figure 13, the grid that formnmos area territory 201 devices pile up 300 and the grid of PMOS zone device pile up 400.Grid pile up 300 and grid pile up 400 formation and can carry out cmp and etching is finished previous layer laminate.And then formed semiconductor device according to the embodiment of the invention.
The present invention is in grid alternative techniques (Replacement gate or Gate last) preparation CMOS transistor process, introduce different high-k gate dielectric materials in the nmos device zone with the PMOS device area respectively, form first high-k gate dielectric layer that belongs to the nmos area territory and the second high-k gate dielectric layer that belongs to the PMOS zone respectively, wherein comprise the element that to regulate the nmos device threshold voltage in the first high-k gate dielectric layer, as La, Y, Sc, Gd etc.; Comprise the element that to regulate the PMOS device threshold voltage in the second high-k gate dielectric layer, as Al, Mg, Ti etc.At the first and second high-k gate dielectric layers, different gate dielectric materials and the boundary layer below it are as SiO2Form different interface dipoles, described interface dipole can apply internal electric field between high-k gate dielectric layer and boundary layer, respectively to the threshold voltage generation effect of NMOS and PMOS device, and different gate dielectric materials is with the different influence of interface generation of metal gate layers on it, as change Fermi level bundle nail position etc., play the effect of effective adjusting nmos device and PMOS device threshold voltage.In addition, these can cause the material of the element of channel carrier mobil-ity degradation owing to diffusion owing to do not have employing to comprise Al or Ti etc. in the nmos device district, thereby have also improved the mobility of nmos device to a certain extent.As can be seen, this structure has not only reduced the EOT value of nmos device and PMOS device respectively, has effectively controlled the threshold voltage of nmos device and PMOS device, has also reduced the degeneration of nmos device electronic carrier mobility.
First and second metal gate layers use identical materials to form simultaneously, have simplified the manufacturing process flow of device.
Though describe in detail about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and claims, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, claims of the present invention are intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (12)
1. semiconductor device comprises:
Semiconductor substrate with nmos area territory and PMOS zone, wherein said nmos area territory and described PMOS zone are isolated mutually by isolated area;
Be formed at that the first grid on the described nmos area territory is piled up and second grid that are formed on the described PMOS zone pile up;
Wherein, the described first grid is piled up and is comprised: first boundary layer; The first high-k gate dielectric layer on described first boundary layer; First metal gate layers on the described first high-k gate dielectric layer;
Described second grid pile up and comprise: the second contact surface layer; The second high-k gate dielectric layer on described second contact surface layer; Second metal gate layers on the described second high-k gate dielectric layer;
The wherein said first and second high-k gate dielectric layers adopt the oxide material that contains n type metal to form, and the dielectric constant of the oxide of described n type metal is higher than SiO2
2. device according to claim 1, the wherein said first high-k gate dielectric layer comprises rare earth and class thulium, selects unit usually to form the group of described first high-k gate dielectric layer column element under comprising: La2O3, HfLaOx, HfLaONx, HfLaSiOx, Y2O3And Sc2O3, and their combination.
3. device according to claim 1, the wherein said second high-k gate dielectric layer comprises other reactive metal elements except that rare earth and class thulium, selects unit usually to form the group of described second high-k gate dielectric layer column element under comprising: Al2O3, HfAlOx, MgO2, TiO2, HfTiOx, HfSiTiOxAnd HfMgOx, and their combination.
4. device according to claim 1, the thickness of the wherein said first and second high-k gate dielectric layers are about 1 to 10 nanometer, are preferably about 1 to 5 nanometer, and optimum is about 1 to 3 nanometer.
5. device according to claim 1, wherein said first metal gate layers and second metal gate layers have identical materials.
6. device according to claim 5 selects unit usually to form the group of wherein said first and second metal gate layers column element under comprising: TiN, TaN, MoN, HfN, HfC, TaC, TiC, MoC, TiAlN, TaAlN, HfAlN, HfTbN, TaTbN, TaErN, TaYbN, TaSiN, TaHfN, TiHfN, HfSiN, MoSiN, MoAlN, RuTax, NiTax, polysilicon and metal silicide, and their combination.
7. method of making semiconductor device, described method comprises:
Semiconductor substrate with nmos area territory and PMOS zone is provided, and wherein said nmos area territory and described PMOS zone are isolated mutually by isolated area;
On described Semiconductor substrate, formation belongs to first boundary layer in nmos area territory, false grid and side wall thereof, formation belongs to the second contact surface layer in PMOS zone, false grid and side wall thereof, and in described Semiconductor substrate, form respectively and belong to the source area and the drain region in nmos area territory and PMOS zone, and cover source area, drain region and the nmos area territory in described NMOS and PMOS zone and the isolated area in PMOS zone forms inner layer dielectric layer;
Remove the false grid in described nmos area territory and PMOS zone, to form first opening and second opening;
In described first opening, form the first high-k gate dielectric layer that covers described first boundary layer, and in described second opening, form to cover the second high-k gate dielectric layer of described second contact surface layer, the wherein said first and second high-k gate dielectric layers adopt the oxide material that contains n type metal to form, and the dielectric constant of the oxide of described n type metal is higher than SiO2
On the described first high-k gate dielectric layer, form first metal gate layers, on the second high-k gate dielectric layer, form second metal gate layers;
Described device is processed, and the first grid belong to the nmos area territory is piled up and second grid that belong to the PMOS zone pile up to form respectively.
8. method according to claim 7, the wherein said first high-k gate dielectric layer comprises rare earth and class thulium, selects unit usually to form the group of described first high-k gate dielectric layer column element under comprising: La2O3, HfLaOx, HfLaONx, HfLaSiOx, Y2O3And Sc2O3, and their combination.
9. method according to claim 7, the wherein said second high-k gate dielectric layer comprises other reactive metal elements except that rare earth and class thulium, selects unit usually to form the group of described second high-k gate dielectric layer column element under comprising: Al2O3, HfAlOx, MgO2, TiO2, HfTiOx, HfSiTiOxAnd HfMgOx, and their combination.
10. method according to claim 7, the thickness of the wherein said first and second high-k gate dielectric layers are about 1 to 10 nanometer, are preferably about 1 to 5 nanometer, and optimum is about 1 to 3 nanometer.
11. method according to claim 7, wherein said first metal gate layers have and the second metal gate layers identical materials.
12. method according to claim 11, select unit usually to form the group of wherein said first and second metal gate layers column element under comprising: TiN, TaN, MoN, HfN, HfC, TaC, TiC, MoC, TiAlN, TaAlN, HfAlN, HfTbN, TaTbN, TaErN, TaYbN, TaSiN, TaHfN, TiHfN, HfSiN, MoSiN, MoAlN, RuTax, NiTax, polysilicon and metal silicide, and their combination.
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| CN103165440A (en)* | 2011-12-09 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of high-dielectric-constant metal grid electrode semiconductor device |
| CN106898545A (en)* | 2012-05-24 | 2017-06-27 | 三星电子株式会社 | Semiconductor device |
| US10840374B2 (en) | 2012-05-24 | 2020-11-17 | Samsung Electronics Co., Ltd. | Semiconductor devices with shaped portions of elevated source/drain regions |
| CN106898545B (en)* | 2012-05-24 | 2020-02-18 | 三星电子株式会社 | semiconductor device |
| US9899270B2 (en) | 2012-11-30 | 2018-02-20 | Institute of Microelectronics, Chinese Academy of Sciences | Methods for manufacturing semiconductor devices |
| CN103855006A (en)* | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN103855012A (en)* | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of N-type MOSFET |
| CN103854983A (en)* | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of P-type MOSFET |
| WO2014082332A1 (en)* | 2012-11-30 | 2014-06-05 | 中国科学院微电子研究所 | Manufacturing method of semiconductor device |
| CN104008974A (en)* | 2013-02-26 | 2014-08-27 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN104347507A (en)* | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device formation method |
| CN109560080A (en)* | 2017-09-25 | 2019-04-02 | 三星电子株式会社 | Semiconductor devices |
| CN114447115A (en)* | 2020-10-30 | 2022-05-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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