CN102110479A - Semiconductor memory apparatus including data compression test circuit - Google Patents

Abstract

The present invention provides a semiconductor memory apparatus having stacked first and second chips, the semiconductor memory apparatus includes: a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode; a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode; and a final data determination unit configured to generate a final test to signal in response to the first and second chip test signals in the test mode.

Description

The semiconductor storage that comprises the data compressing and testing circuit

The cross reference of related application

The application number that the application requires to submit to Korean Patent office on Dec 28th, 2009 is the right of priority of the korean patent application of 10-2009-0131780, and its full content is incorporated herein by reference.

Technical field

Each embodiment of the present disclosure relates generally to semiconductor storage, more specifically, relates to the semiconductor storage that comprises the data compressing and testing circuit.

Background technology

Semiconductor storage has a large amount of storage unit and can store high capacity data.In order to improve the reliability of semiconductor storage, carry out test usually and confirm whether inefficacy has taken place in the storage unit, and implement to repair to replace the storage unit that lost efficacy with the storage unit that provides separately.Yet,, can not test described storage unit one by one and confirm whether inefficacy has taken place because semiconductor storage has aforesaid a large amount of storage unit.Therefore, the method for testing that needs a kind of normal running of the storage unit that can in short time period, confirm semiconductor storage.

Fig. 1 is the figure that schematically illustrates the structure of conventional semiconductor memory storage.Referring to Fig. 1, the data compression that semiconductor storage will be exported from memory bank BANK0 to BANK3 via the data input/output line, and by determining side by side the data of being compressed come whether to have taken place in the test storage unit inefficacy.This is known as the data compressing and testing to semiconductor storage.Particularly, the first, the 3rd and the 5th data were stored in situation among the first memory bank BANK0 with high level data under, test circuit was data with the first, the 3rd and the 5th data compression.At this moment, if three data all have high level, then output has for example definite signal of high level, and can think that data are normal output.If any one in three data has different level, then output has for example low level definite signal, and can think that data are not normal output.

Fig. 1 illustrates by test is carried out in the data compression of the first memory bank BANK0.In Fig. 1, be stored in 16 Bit datas among the first memory bank BANK0 of bottom memory district LDQ by data compression unit 11 compressions of test circuit 10, and be loaded into global lines GIO_00＜0 to GIO_03＜0 on.Test circuit 10 order unit 12 really determines to be loaded into global lines GIO_00＜0〉to GIO_03＜0 on data whether all have identical level.Similarly, be stored in 16 Bit datas among the first memory bank BANK0 of top memory district UDQ by data compression unit 21 compressions of test circuit 20, and be loaded into global lines GIO_04＜0 to GIO_07＜0 on.Test circuit 20 order unit 22 really determines to be loaded into global lines GIO_04＜0〉to GIO_07＜0 on data whether all have identical level.

Therefore, be used to compress and the quantity of global lines of data of testing the first memory bank BANK0 of bottom memory district LDQ is 4, be used to compress and the quantity of global lines of data of testing the first memory bank BANK0 of top memory district UDQ also is 4.The result is, a necessary global lines of memory bank add up to 8.Therefore, in order to test semiconductor storage, need 64 global lines altogether with 8 memory banks.

Meanwhile, in order to improve the integrated level of semiconductor device, developed a plurality of chip laminates and be packaged in 3 D semiconductor device in the single encapsulation.Since stacked vertical two or more chips, the integrated level that the 3 D semiconductor device can have been realized improving in essentially identical space.

In addition, recently, this area discloses through-silicon through hole (TSV) N-type semiconductor N device, and in this TSV N-type semiconductor N device, the silicon through hole passes a plurality of chip stacked and forms, and makes whole chips be electrically connected to each other.With each chip is to compare through being adjacent to the semiconductor device that the bonding line of bonding is electrically connected with the edge of chip, and chip is the silicon through hole through vertically passing chip and the TSV N-type semiconductor N device that is electrically connected has reduced the package area of TSV N-type semiconductor N device.

In the 3 D semiconductor device, the quantity of compressing with the required global lines of test data in mode same as the prior art increases sharp.For example, making under the situation of single semiconductor device by stacked eight chips, if use with in the identical manufacturing process of prior art, need altogether 64 * 8 to be 512 global lines.Especially, in order after packaged semiconductor devices, to carry out test, need have TSV with the corresponding quantity of global lines quantity.Therefore, chip size and layout area increase, and cause the increase of manufacturing cost.

Summary of the invention

Various aspects of the present invention comprise a kind of semiconductor device, can be simultaneously with data compressing and testing circuit from the data compressing and testing (compression-test) of the memory bank output of a plurality of chips.

According to one embodiment of present invention, a kind of semiconductor storage with the first stacked chip and second chip comprises: the first chip testing signal generating unit, the described first chip testing signal generating unit is arranged in first chip, and is configured to determine signal and produce the first chip testing signal in response to the first chip packed data under test pattern; The second chip testing signal generating unit, the described second chip testing signal generating unit is arranged in second chip, and is configured to determine signal and produce the second chip testing signal in response to the second chip packed data under test pattern; With the final data determining unit, described final data determining unit is configured under test pattern in response to the first chip testing signal and the second chip testing signal and produces the final test signal.

According to another embodiment of the invention, a kind of semiconductor storage with the first stacked chip and second chip comprises: the first compression verification circuit, the described first compression verification circuit is arranged in first chip, and is configured to produce the first chip testing signal by memory bank output and compressed data from first chip; The second compression verification circuit, the described second compression verification circuit is arranged in second chip, and is configured to produce the second chip testing signal by memory bank output and compressed data from second chip; With the final data determining unit, described final data determining unit is configured in response to the first chip testing signal and the second chip testing signal and produces the final test signal.

According to still another embodiment of the invention, a kind of semiconductor storage with the first stacked chip and second chip comprises: the first compression verification circuit, the described first compression verification circuit is arranged in first chip, and the result who is configured to be stored in the data compressing and testing in first memory bank of first chip is sent to the first through-silicon through hole (TSV); The second compression verification circuit, the described second compression verification circuit is arranged in first chip, and the result who is configured to be stored in the data compressing and testing in second memory bank of first chip is sent to the 2nd TSV; The 3rd compression verification circuit, described the 3rd compression verification circuit is arranged in second chip, and the result who is configured to be stored in the data compressing and testing in first memory bank of second chip is sent to a TSV; The 4th compression verification circuit, described the 4th compression verification circuit is arranged in second chip, and the result who is configured to be stored in the data compressing and testing in second memory bank of second chip is sent to the 2nd TSV.

Description of drawings

Constitute the part of this instructions at appended accompanying drawing, represented and each embodiment that invention is consistent, and be used for explaining principle of the present invention with instructions.

Fig. 1 is the figure that schematically shows the structure of conventional semiconductor memory storage.

Fig. 2 is the block diagram that schematically shows the structure of semiconductor storage according to an embodiment of the invention.

Fig. 3 is the circuit diagram of the structure of the expression first chip testing signal generating unit shown in Figure 2.

Fig. 4 is the circuit diagram of the structure of expression final data determining unit shown in Figure 2.

Fig. 5 is the block diagram that schematically shows the structure of semiconductor storage according to an embodiment of the invention.

Embodiment

Advantages and features of the invention and being used to realize that the method for these advantages and feature will be by becoming clear below in conjunction with accompanying drawing to the description of embodiment.Yet the present invention is not limited to the exemplary embodiment of the following stated, but can different forms realize.Therefore, it is to make those skilled in the art in depth understand instruction of the present invention that exemplary embodiment is provided, and the scope of the present invention and exemplary embodiment of fully informing is only limited by the scope of claims.In instructions, identical Reference numeral is represented identical key element.

Fig. 2 is the block diagram that schematically shows the structure of semiconductor storage according to an embodiment of the invention.Referring to Fig. 2,, be clear that and use any amount of stacked die though be that the first chip C1 to the, eight chip C8 are stacked and constitute single semiconductor storage 1.The first chip C1 to the, eight chip C8 have compression verification circuit 110 to 180 respectively.

The first compression verification circuit 110 is set under test pattern the data GIO_c1 in the memory bank that is stored in the first chip C1 be carried out compression verification (compression-test), and the second compression verification circuit, 120 to the 8thcompression verification circuit 180 are set under test pattern the data GIO_c2 to GIO_c8 in the memory bank that is stored in the second chip C2 to the, eight chip C8 be carried out compression verification.As mentioned above, data compressing and testing is meant such test: will store the data compression of a plurality of storage unit of data with identity logic level, and whether all identical and make affirmation about the logic level of a plurality of data.

The first compression verification circuit 110 can be configured to and will compress from the data GIO_c1 that the memory bank of the first chip C1 is exported, and whether the logic level of definite data of being compressed is all identical.The first compression verification circuit 110 can produce the first chip testing signal TOUT_c1 according to definite result, and the first chip testing signal TOUT_c1 is sent to through-silicon through hole (TSV).For example, if the logic level of the data of being compressed is all identical, then the first compression verification circuit 110 can be forbidden the first chip testing signal TOUT_c1.If institute's compressed data packet is drawn together the data with Different Logic level, then the first compression verification circuit 110 can enable the first chip testing signal TOUT_c1.

The secondcompression verification circuit 120 can be configured to and will compress from the data GIO_c2 that the memory bank of the second chip C2 is exported, and whether the logic level of definite data of being compressed is all identical.The secondcompression verification circuit 120 can produce the second chip testing signal TOUT_c2 according to definite result, and the second chip testing signal TOUT_c2 is sent to TSV.For example, if the logic level of the data of being compressed is all identical, then the secondcompression verification circuit 120 can be forbidden the second chip testing signal TOUT_c2.If institute's compressed data packet is drawn together the data with Different Logic level, then the secondcompression verification circuit 120 can enable the second chip testing signal TOUT_c2.

The 3rdcompression verification circuit 130 to the 8thcompression verification circuit 180 can be configured to will be from data GIO_c3 to the GIO_c8 compression of the memory bank output that constitutes the 3rd chip C3 to the eight chip C8, determine the logic level of the data compressed and produce the 3rd chip testing signal TOUT_c3 to the eight chip testing signal TOUT_c8.The 3rd chip testing signal TOUT_c3 to the eight chip testing signal TOUT_c8 can be sent to TSV.For example, if the logic level of the data of being compressed is all identical, then each of the 3rdcompression verification circuit 130 to the 8thcompression verification circuit 180 forbidden the 3rd chip testing signal TOUT_c3 to the eight chip testing signal TOUT_c8 each.If institute's compressed data packet is drawn together the data with Different Logic level, then each of the 3rdcompression verification circuit 130 to the 8thcompression verification circuit 180 enables the 3rd chip testing signal TOUT_c3 to the eight chip testing signal TOUT_c8 each.

Preferably, the data of identical memory bank output are numbered in first compression verification circuit 110 to the 8th compression verification circuit, 180 compressions and test from relevant chip C1 to C8, but also can use other method.That is to say, if the first compression verification circuit 110 receives from the data of first memory bank output of the first chip C1, then the second compression verification circuit, 120 to the 8thcompression verification circuit 180 receive from the data of first memory bank output of the second chip C2 to the, eight chip C8.Correspondingly, even when stacked a plurality of chip, also can side by side carry out compression verification to the data in the identical memory bank of the numbering that is stored in a plurality of chips according to thesemiconductor storage 1 of the embodiment of the invention.In other words, each in the first chip C1 to the, eight chip C8 comprises under the situation of eight memory banks that structure shown in Figure 2 can be set to eight.

Referring to Fig. 2, the first compression verification circuit 110 comprises the firstdata determining unit 111 and the first chip testing signal generating unit 112.The firstdata determining unit 111 will be compressed from the data GIO_c1 that the memory bank of the first chip C1 is exported, and produces the result that the first chip packed data is determined the logic level of the definite data of being compressed of signal DET_c1 conduct.Like this, whole when identical when the logic level of the data of being compressed, the firstdata determining unit 111 determines that with the first chip packed data signal DET_c1 enables; And when working as in the data of being compressed any one and having different logic levels, the firstdata determining unit 111 determines that with the first chip packed data signal DET_c1 forbids.

The first chip testingsignal generating unit 112 can be configured to determine signal DET_c1 and produce the first chip testing signal TOUT_c1 in response to the first chip packed data under testpattern.Semiconductor storage 1 can enter test pattern in response to test mode signal TM.The first chip testingsignal generating unit 112 is forbidden the first chip testing signal TOUT_c1 when the first chip packed data determines that signal DET_c1 is enabled, and when the first chip packed data determines that signal DET_c1 is under an embargo the first chip testing signal TOUT_c1 is enabled.Therefore, the first chip testingsignal generating unit 112 can be sent to TSV with the forbidden first chip testing signal TOUT_c1 when the output of the memory bank of the first chip C1 and compressed data all have identical logic level, and is sent to TSV at the first chip testing signal TOUT_c1 that will be enabled when also any one the compressed data has different logic levels from the memory bank output of the first chip C1.

Referring to Fig. 2, the secondcompression verification circuit 120 can comprise the seconddata determining unit 121 and the second chip testing signal generating unit 122.The seconddata determining unit 121 can be compressed the data GIO_c2 that exports from the memory bank of the second chip C2, and produces the result that the second chip packed data is determined the logic level of the definite data of being compressed of signal DET_c2 conduct.Like this, whole when identical when the logic level of the data of being compressed, the seconddata determining unit 121 can determine that signal DET_c2 enables with the second chip packed data; And when working as in the data of being compressed any one and having different logic levels, the seconddata determining unit 121 can determine that signal DET_c2 forbids with the second chip packed data.

The second chip testingsignal generating unit 122 can be configured to determine signal DET_c2 and produce the second chip testing signal TOUT_c2 in response to the second chip packed data under test pattern.The second chip testingsignal generating unit 122 is forbidden the second chip testing signal TOUT_c2 when the second chip packed data determines that signal DET_c2 is enabled, and when the second chip packed data determines that signal DET_c2 is under an embargo the second chip testing signal TOUT_c2 is enabled.Therefore, the second chip testingsignal generating unit 122 can be sent to TSV with the forbidden second chip testing signal TOUT_c2 when the output of the memory bank of the second chip C2 and compressed data all have identical logic level, and is sent to TSV at the second chip testing signal TOUT_c2 that will be enabled when also any one the compressed data has different logic levels from the memory bank output of the second chip C2.

The firstdata determining unit 111 can have and existing test circuit 10 shown in Figure 1 and 20 identical structures with the second data determining unit 121.The 3rdcompression verification circuit 130 to the 8thcompression verification circuit 180 can dispose in the mode identical with the secondcompression verification circuit 120 with the first compression verification circuit 110, correspondingly, have omitted the explanation that repeats.

Finaldata determining unit 200 can be configured to receive the first chip testing signal TOUT_c1 to the, eight chip testing signal TOUT_c8 via TSV under test pattern, and produces final test signal TOUT in response to the first chip testing signal TOUT_c1 to the, eight chip testing signal TOUT_c8.Finaldata determining unit 200 can produce the final test signal TOUT that is enabled when the first chip testing signal TOUT_c1 to the, eight chip testing signal TOUT_c8 all are under an embargo, and in the first chip testing signal TOUT_c1 to the, eight chip testing signal TOUT_c8 any one produces forbidden final test signal TOUT when being enabled.In other words, finaldata determining unit 200 can enable final test signal TOUT when identical from the logic level of output of the memory bank of the first chip C1 to the, eight chip C8 and compressed data is whole, and in described data any one forbidden final test signal TOUT when having different logic levels.

Fig. 3 is the circuit diagram of the structure of the expression first chip testing signal generating unit shown in Figure 2.Referring to Fig. 3, the first chip testingsignal generating unit 112 comprises the first phase inverter IV1, latchs the LAT of portion, Sheffer stroke gate ND1 and P-type mos (PMOS) transistor P1.The first phase inverter IV1 determines that with the first chip packed data signal DET_c1 is anti-phase.Latch the output latch of the LAT of portion with the first phase inverter IV1.The output of the Sheffer stroke gate ND1 acceptance test mode signal TM and the first phase inverter IV1.PMOS transistor P1 has the grid of the output that receives Sheffer stroke gate ND1, the drain electrode that has been applied in the source electrode of outer power voltage VDD and has produced the first chip testing signal TOUT_c1.Like this, the first chip testingsignal generating unit 112 can be under test pattern be determined signal DET_c1 and the first chip testing signal TOUT_c1 is enabled to forbid being low level for high level or with the first chip testing signal TOUT_c1 in response to test mode signal TM and the first chip packed data.Particularly, when whole when identical from the logic level of output of the memory bank of the first chip C1 and compressed data, the first chip packed data is determined that signal DET_c1 can be enabled and is high level.Correspondingly, forbidden being low level signal by the first phase inverter IV1, so Sheffer stroke gate ND1 output has the signal of high level because Sheffer stroke gate ND1 receives.Thus, PMOS transistor P1 turn-offs, and the first chip testing signal TOUT_c1 is under an embargo.On the contrary, when in the data of being compressed any one had different logic levels, the first chip packed data was determined that signal DET_c1 is under an embargo and is low level.Correspondingly, enable to be the test mode signal TM of high level with being enabled because Sheffer stroke gate ND1 receives by the first phase inverter IV1, so Sheffer stroke gate ND1 output has low level signal for the signal of high level.Thus, PMOS transistor P1 connects, and can provide the signal that is enabled to level with outer power voltage VDD as the first chip testing signal TOUT_c1.

Because the second chip testing signal generating unit, 122 to the 8th chip testingsignal generating units 182 can have the configuration identical with the first chip testingsignal generating unit 112, therefore the repetitive description thereof will be omitted.

Fig. 4 is the circuit diagram of the structure of expression final data determining unit shown in Figure 2.Referring to Fig. 4, finaldata determining unit 200 comprises N type metal oxide semiconductor (NMOS) the transistor N1 and the second phase inverter IV2.The source electrode that nmos pass transistor N1 has the grid of acceptance test mode signal TM, the drain electrode that is connected with ground voltage VSS and is connected with node A.Node A is connected with TSV, and receives from the first chip testing signal TOUT_c1 to the, the eight chip testing signal TOUT_c8 of the first compression verification circuit, 110 to the 8th compression verification circuit, 180 outputs.The second phase inverter IV2 will have the final test signal TOUT output of the level opposite with the level of node A.

When whole when identical from the logic level of output of the memory bank of the first chip C1 to the, eight chip C8 and compressed data, because the forbidden first chip testing signal TOUT_c1 to the, eight chip testing signal TOUT_c8 are from 180 outputs of the first compression verification circuit, 110 to the 8th compression verification circuit, so node A has the level of ground voltage VSS because of nmos pass transistor N1.The second phase inverter IV2 makes the level inversion of ground voltage VSS, and produces to be enabled and be the final test signal TOUT of high level.On the contrary, when from output of the memory bank of the first chip C1 to the, eight chip C8 and compressed data any one had different logic levels, the first chip testing signal TOUT_c1 to the, eight chip testing signal TOUT_c8 were enabled.In this, below description has the situation of different logic levels from the memory bank output of the first chip C1 and any one the compressed data.

In the case, the first chip testing signal generating unit, 112 generations of the first compression verification circuit 110 are enabled and are the first chip testing signal TOUT_c1 of the level with outer power voltage VDD, and the second compression verification circuit, 120 to the 8thcompression verification circuit 180 produce the forbidden second chip testing signal TOUT_c2 to the, eight chip testing signal TOUT_c8.At this moment, preferably constitute, the driving force of the PMOS transistor P1 of the first chip testingsignal generating unit 112 is greater than the driving force of the nmos pass transistor N1 that constitutes finaldata determining unit 200, although also can adopt other embodiment.This is because when only having a chip testing signal to be enabled, the output of final test signal TOUT can be changed.Like this, owing to applied the first chip testing signal TOUT_c1 of the level that is in outer power voltage VDD, even nmos pass transistor N1 provides the level of ground voltage VSS, the voltage level of first node A also can be changed and be high level, its result, can produce is under an embargo is low level final test signal TOUT.The second chip testing signal generating unit, 122 to the 8th chip testingsignal generating units 182 can have the structure identical with the first chip testingsignal generating unit 112, and can operate in an identical manner.

In the semiconductor storage with a plurality of stacked dies according to the present invention, the compression verification result of the data relevant with a plurality of chips memory bank separately is sent to identical TSV, and produces final testing result.Therefore, owing to provide the TSV that has with the corresponding quantity of global lines quantity that is used in single chip just enough, therefore can guarantee the Butut surplus of semiconductor storage, and can reduce chip size the compression verification that is used for a plurality of chips.Especially, can be when the encapsulated semiconductor memory storage with effective value maximization of the present invention.

Fig. 5 is the block diagram that schematically shows the structure ofsemiconductor storage 2 according to an embodiment of the invention.Referring to Fig. 5, the first chip C1 comprises the first compression verification circuit 110A and the second compressor circuit 110B.The first compression verification circuit 110A and thesecond compressor circuit 110B can be configured to data GIO_c1＜0 from first memory bank of the first chip C1 and the output of second memory bank〉and GIO_c1＜1 carry out compression verification, and produce first chip testing signal TOUT_c1＜0〉and TOUT_c1＜1.The second chip C2 comprises the 3rdcompression verification circuit 120A and the 4th compressor circuit 120B.The 3rdcompression verification circuit 120A and the4th compressor circuit 120B can be configured to data GIO_c2＜0 from first memory bank of the second chip C2 and the output of second memory bank〉and GIO_c2＜1 carry out compression verification, and produce second chip testing signal TOUT_c2＜0〉and TOUT_c2＜1.Can dispose the 5th compression verification circuit to the 16 compression verification circuit 130A to 180A and the 130B to 180B that are arranged among the 3rd chip C3 to the eight chip C8 in an identical manner.

First chip testing signal TOUT_c1＜0 that the first compression verification circuit 110A is produced 〉, second chip testing signal TOUT_c2＜0 that produced of the 3rdcompression verification circuit 120A and the 8th chip testing signal TOUT_c8＜0 that produced of the 15compression verification circuit 180A be sent to a TSV TSV1.In addition, first chip testing signal TOUT_c1＜1 that produced of the secondcompression verification circuit 110B 〉, second chip testing signal TOUT_c2＜1 that produced of the 4thcompression verification circuit 120B and the 8th chip testing signal TOUT_c8＜1 that produced of the 16compression verification circuit 180B be sent to the 2nd TSV TSV2.

The first finaldata determining unit 200A can be configured to receive first chip testing signal TOUT_c1＜0 from TSV TSV1〉to the 8th chip testing signal TOUT_c8＜0th and export first final test data TOUT＜0, and can produce data GIO_c1＜0 from the output of first memory bank of the first chip C1 to the, eight chip C8 to GIO_c8＜0 the compression verification result.The second final data determining unit 200B can be configured to receive first chip testing signal TOUT_c1＜1 from TSV TSV2〉to the 8th chip testing signal TOUT_c8＜1st and export second final test data TOUT＜1, and can produce data GIO_c1＜1 from the output of second memory bank of the first chip C1 to the, eight chip C8 to GIO_c8＜1 the compression verification result.

As understanding from the above description, even a plurality of chip laminate also can be carried out the data compressing and testing to the identical memory bank of numbering in the stacked die simultaneously.Like this, can utilize the TSV that has with the corresponding quantity of quantity of the required global lines of the data compressing and testing of single chip to carry out compression verification to semiconductor storage.

Though below described some embodiment, person of skill in the art will appreciate that described embodiment only is exemplary.Therefore, the semiconductor storage of data compressing and testing circuit that comprises as herein described should not be limited to the embodiment of description.Exactly, the data compressing and testing circuit semiconductor memory storage that comprises as herein described should only limit according to appended claims and in conjunction with above instructions and accompanying drawing.

Claims (20)

1. one kind has the first stacked chip and the semiconductor storage of second chip, comprising:

The first chip testing signal generating unit, the described first chip testing signal generating unit is arranged in described first chip, and is configured to determine signal and produce the first chip testing signal in response to the first chip packed data under test pattern;

The second chip testing signal generating unit, the described second chip testing signal generating unit is arranged in described second chip, and is configured to determine signal and produce the second chip testing signal in response to the second chip packed data under described test pattern; With

Final data determining unit, described final data determining unit are configured under described test pattern in response to the described first chip testing signal and the described second chip testing signal and produce the final test signal.

2. semiconductor storage as claimed in claim 1, wherein, described final data determining unit is arranged in described first chip and described second chip one.

3. semiconductor storage as claimed in claim 1, wherein, described first chip testing signal and the described second chip testing signal are sent to described final data determining unit via through-silicon through hole TSV.

4. semiconductor storage as claimed in claim 1, wherein, when whole when identical from the level of the output of described first chip and compressed a plurality of data, the described first chip packed data determines that signal is enabled; And when having different level for one in described a plurality of data, the described first chip packed data determines that signal is under an embargo.

5. semiconductor storage as claimed in claim 4, wherein, the described first chip testing signal generating unit is configured to be enabled when the described first chip packed data determines that signal is under an embargo.

6. semiconductor storage as claimed in claim 1, wherein, when whole when identical from the level of the output of described second chip and compressed a plurality of data, the described second chip packed data determines that signal is enabled; And when having different level for one in described a plurality of data, the described second chip packed data determines that signal is under an embargo.

7. semiconductor storage as claimed in claim 6, wherein, the described second chip testing signal generating unit is configured to be enabled when the described second chip packed data determines that signal is under an embargo.

8. semiconductor storage as claimed in claim 1, wherein, described final data determining unit is configured to when being enabled for one in described first chip testing signal and the described second chip testing signal described final test signal-inhibiting.

9. one kind has the first stacked chip and the semiconductor storage of second chip, comprising:

The first compression verification circuit, the described first compression verification circuit is arranged in described first chip, and is configured to produce the first chip testing signal by memory bank output and compressed data from described first chip;

The second compression verification circuit, the described second compression verification circuit is arranged in described second chip, and is configured to produce the second chip testing signal by memory bank output and compressed data from described second chip; With

Final data determining unit, described final data determining unit are configured in response to the described first chip testing signal and the described second chip testing signal and produce the final test signal.

10. semiconductor storage as claimed in claim 9, wherein, the described first compression verification circuit comprises:

The first data determining unit, the described first data determining unit be configured to determine from the described memory bank output of described first chip and the logic level of compressed data, and produce the first chip packed data and determine signal; With

The first chip testing signal generating unit, the described first chip testing signal generating unit are configured to determine signal and produce the described first chip testing signal in response to the described first chip packed data.

11. semiconductor storage as claimed in claim 9, wherein, the described first data determining unit is configured to the described first chip packed data be determined that signal enables when the logic level of described data is whole when identical, and when having different logic levels for one in the described data the described first chip packed data is determined signal-inhibiting.

12. semiconductor storage as claimed in claim 9, wherein, the described first chip testing signal generating unit is configured to when the described first chip packed data determines that signal is enabled the described first chip testing signal-inhibiting, and when the described first chip packed data determines that signal is under an embargo the described first chip testing signal is enabled.

13. semiconductor storage as claimed in claim 9, wherein, the described second compression verification circuit comprises:

The second data determining unit, the described second data determining unit be configured to determine from the described memory bank output of described second chip and the logic level of compressed data, and produce the second chip packed data and determine signal; With

The second chip testing signal generating unit, the described second chip testing signal generating unit are configured to determine signal and produce the described second chip testing signal in response to the described second chip packed data.

14. semiconductor storage as claimed in claim 13, wherein, the described second data determining unit is configured to the described second chip packed data be determined that signal enables when the logic level of described data is whole when identical, and when having different logic levels for one in the described data the described second chip packed data is determined signal-inhibiting.

15. semiconductor storage as claimed in claim 13, wherein, the described second chip testing signal generating unit is configured to when the described second chip packed data determines that signal is enabled the described second chip testing signal-inhibiting, and when the described second chip packed data determines that signal is under an embargo the described second chip testing signal is enabled.

16. semiconductor storage as claimed in claim 9, wherein, described final data determining unit is arranged in described first chip and described second chip one.

17. semiconductor storage as claimed in claim 9, wherein, described first chip testing signal and the described second chip testing signal are sent to described final data determining unit via TSV.

18. one kind has the first stacked chip and the semiconductor storage of second chip, comprising:

The first compression verification circuit, the described first compression verification circuit is arranged in described first chip, and the result who is configured to be stored in the data compressing and testing in first memory bank of described first chip is sent to the first through-silicon through hole TSV;

The second compression verification circuit, the described second compression verification circuit is arranged in described first chip, and the result who is configured to be stored in the data compressing and testing in second memory bank of described first chip is sent to the 2nd TSV;

The 3rd compression verification circuit, described the 3rd compression verification circuit is arranged in described second chip, and the result who is configured to be stored in the data compressing and testing in first memory bank of described second chip is sent to a described TSV;

The 4th compression verification circuit, described the 4th compression verification circuit is arranged in described second chip, and the result who is configured to be stored in the data compressing and testing in second memory bank of described second chip is sent to described the 2nd TSV.

19. semiconductor storage as claimed in claim 18 also comprises:

The first final data determining unit, the described first final data determining unit are configured to produce the first final test signal according to the test result of described first compression verification circuit and described the 3rd compression verification circuit; With

The second final data determining unit, the described second final data determining unit are configured to produce the second final test signal according to the test result of described second compression verification circuit and described the 4th compression verification circuit.

20. semiconductor storage as claimed in claim 19, wherein, described first final data determining unit and the described second final data determining unit are arranged in described first chip and described second chip one.

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