CN102110033A - LSI, fail-safe LSI for railways, electronic device, and electronic device for railways - Google Patents
LSI, fail-safe LSI for railways, electronic device, and electronic device for railwaysDownload PDFInfo
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- CN102110033A CN102110033ACN2010106216340ACN201010621634ACN102110033ACN 102110033 ACN102110033 ACN 102110033ACN 2010106216340 ACN2010106216340 ACN 2010106216340ACN 201010621634 ACN201010621634 ACN 201010621634ACN 102110033 ACN102110033 ACN 102110033A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B61—RAILWAYS
- B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
- B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
- B61L27/50—Trackside diagnosis or maintenance, e.g. software upgrades
- B61L27/57—Trackside diagnosis or maintenance, e.g. software upgrades for vehicles or trains, e.g. trackside supervision of train conditions
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
- G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
- H03K19/0075—Fail-safe circuits by using two redundant chains
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
Translated fromChineseDescription
Technical field
The present invention relates to the semi-conductor chip of microprocessor built-in, related to signal system in the railway especially and need like that employed semi-conductor chip in the control system of high security.
Background technology
Signal system in railway needs in the control system of high security like that; thought according to " fail safe (Off エ one Le セ one Off; fail safe) " is come designing apparatus; taken place when unusual at intrasystem equipment even make; the also state that system is in jeopardy, and can under the state of safety, stop.Although in the realization of fail safe reliably checkout equipment be essential unusually,, in the control system of having used microprocessor, mutually monitor the unusual of measurement processor portion by processor being carried out multiplexed (multipleization).
In recent years, along with semi-conductive highly integrated, built-in two processors in a LSI chip, thus make it possible to movecomparison.Patent documentation 1 grade has been put down in writing this manner of comparison.Non-patentliterature 1 has been put down in writing the example that in fact makes 1 chip failure protection LSI.
Patent documentation 1: Japanese kokai publication hei 6-161798 communique
Non-patent literature 1:K.Shimamura etc.: " A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature ", IEEE 12ThPacific Rim International Symposium on Dependable Computing (PRDC ' 06) (18-20 day in Dec, 2006).
Recently, semi-conductive highly integrated more progressive, so far, can will be built in the chip by the peripheral circuit of tyre in chip.In order to effectively utilize the performance of processors of high speed motion, need be under high speed jumbo storer in addition.
For multiple peripheral circuit and high speed external memory storage etc. can be connected on the chip, need to increase the signal pin number of the encapsulation of chip and built-in chip.Because the operating frequency of peripheral circuit is high speed also, distribution postpones and the difference of electrical specification when just needing to consider the signal pin configuration.
On the other hand, in the prior art, from guaranteeing the viewpoint of reliability, mentioned the processor in the chip and the configuration of comparator circuit, still,, do not mentioned for the signal pin configuration of encapsulation and the component configuration of device substrate.And also only there is a kind of general bus in the peripheral circuit that the outside connected of chip, does not have the correspondence of consideration to multiple peripheral circuit and high speed external memory storage.
Usually, the built-in LSI of processor in order to keep versatility on purposes, keeps a plurality of functions on an external signal pin, come handoff functionality as required, and it is also a lot of to have the situation of having set the multiplexed signal pin of so-called pin.Thus, although the limited signal pin of usage quantity effectively is multiplexed for the pin among the fail safe LSI in the prior art, but do not consider.
Summary of the invention
The objective of the invention is to comprise the peripheral circuit of LSI chip and make security and high performance and deposit.
Make security and high performance in order to comprise peripheral circuit and deposit, will the signal pin relevant be configured in the position that the diagonal angle of encapsulation promptly leaves most mutually with 2 systems that comprise processor, and the signal pin that configuration is correlated with common system between the signal pin relevant with 2 systems.Have under 2 the situation configuration signal pin relevant on the zone between the signal relevant with per 1 peripheral circuit with 2 systems with 2 positions at the peripheral circuit of common system.
The invention effect
Because the signal pin of being correlated with common system by configuration between the signal pin relevant with 2 systems, can make the distance of the signal pin relevant become maximum with 2 systems, therefore can make by single main causes such as electromagnetic noise cause 2 systems simultaneously the possibility of malfunctions become littler.
Description of drawings
Fig. 1 is a synoptic diagram of the present invention.
Fig. 2 is the physical arrangement figure of fail safe LSI.
Fig. 3 is the internal structure figure of fail safe LSI.
Fig. 4 is the synoptic diagram of the distribution that connected of common system internal bus.
Fig. 5 is the internal structure figure of common system internal bus.
Fig. 6 is the sequential chart that is used to illustrate the action of internal bus.
Fig. 7 is the internal structure figure of comparison means.
Fig. 8 is the action diagram of alternating signal generator.
Fig. 9 is the internal structure figure of bus comparer.
Figure 10 is the internal structure figure of two-way multiplexing control circuit.
Figure 11 is the internal structure figure of general imput output circuit.
Figure 12 is used to illustrate the logic circuit arrangements in the LSI chip and the synoptic diagram of input/output pads (パ Star De) configuration.
Figure 13 is the synoptic diagram that is used to illustrate the external terminal configuration of LSI.
Figure 14 is the component configuration figure on the electronic circuit board.
Figure 15 is the internal structure figure of the fail safe LSI of second embodiment.
Figure 16 is the general imput output circuit of second embodiment and the internal structure figure of pin function selector switch.
Figure 17 is used to illustrate the logic circuit arrangements in the LSI chip of second embodiment and the synoptic diagram of input/output pads configuration.
Figure 18 is the synoptic diagram of external terminal configuration that is used to illustrate the LSI of second embodiment.
Figure 19 is the synoptic diagram with fail safe LSI of different physical arrangements.
Figure 20 is the synoptic diagram that is used to illustrate the external terminal configuration of the fail safe LSI with different external terminal structures.
The reference numeral explanation
10 fail safe LSI
11A, the 11B processor
12A, internal bus in the 12B system
13A, 13B high-speed memory interface circuit
14A, 14B external bus interface circuit
15A, the general imput output circuit of 15B
20 comparison means
21 common system internal buss
22 system bus interface circuits
23 network interface circuits
25A, 25B pin function selector switch
30 electronic circuit boards
100 fail safe LSI chips
200 normal anomalous discrimination signals
201 alternating signal generators
202 bus comparers
203 two-way multiplexing control circuits
204 more inconsistent signals
Embodiment
To Figure 14 the first embodiment of the present invention is described according to Fig. 1.Fig. 1 is the synoptic diagram of explanation summary of the present invention.The treating apparatus that comprises the processor and the identical formation of external interface (the following I/F of being) circuit has been carried in 2 systems in a LSI 10.In the present embodiment, 2 systems are called A system and B system.Treating apparatus separately has more than one processor and more than one exterior I/F circuit, and they all are connected to interior internal buss such as each system.Because the result of the processor in each system etc. appears on the internal bus, therefore, know that then the treating apparatus of 2 systems has carried out identical action if the comparison means that is connected with B internal system bus by A internal system bus compares the signal of both buses.To be illustrated in both by normalanomalous discrimination signal 200 has carried out under the situation of same action to output to the outside of failsafe LSI chip 100 under the situation normal, carried out different actions at both for anomalous signals.Under normal situation, promptly to have exported under the situation of same signal at the internal bus of 2 systems, comparison means is by selecting the individual common system internal bus that outputs to of one.For from the common system internal bus to the output of handling device, comparison means outputs on both of internal bus of 2 systems.By such bus single line, the action of 2 systems regularly (timing) can not staggered, thereby same treatment is continued.The common system external interface circuit is connected on the common system internal bus by a plurality of.External device (ED) separately can be connected on the exterior I/F and common system exterior I/F of identical formation of 2 systems.Like this, by the output of contrast from 2 processors, need not the outside of chip will directly be outputed to as prior art by the internal interface of single line, a plurality of external interface circuits can be connected to this common system internal bus by making in a single day just to be connected with the common system internal bus, thereby can connect multiple peripheral circuit, the performance that can obtain LSI improves.
In other words, owing to make it possible to built-in a plurality of external interface, therefore make it possible to a plurality of external device (ED)s are directly connected on the chip by the common system internal bus is set.
Fig. 2 is the synoptic diagram of summary of physical arrangement of the fail safe LSI of expression present embodiment.Fig. 2 (a) is the synoptic diagram in the cross section of expression failsafe LSI 10; the exterior I ofLSI chip 100/F signal and power supply are connected to base plate forpackaging 101 by bonding wire (ボ Application デ イ Application グ ワ イ ヤ) 103, are connected with outside via thesolder ball 104 of installing in the bottom of base plate for packaging 100.The top ofLSI chip 100 is by encapsulant 102 protections.Fig. 2 (b) is the vertical view that removes the state behind theencapsulant 102 from failsafe LSI 10, and itsexpression LSI chip 100 is by being configured in circuit face on the base plate forpackaging 101 towards top, and is connected on the base plate forpackaging 101 by bonding wire 103.Fig. 2 (c) is the synoptic diagram of the circuit face ofexpression LSI chip 100, and itsexpression LSI chip 100 is made of with the input/output pads zone 106 that is used to be connected signal and power supply the logicalcircuit installation region 105 of logical circuits such as the treating apparatus that has formed 2 systems and comparison means.In the present embodiment, disposed the treating apparatus of A system in the left side ofLSI chip 100, disposed the treating apparatus of B system on the right side, in central configuration the circuit of common system.About disposing aftermentioned in the chip.
Fig. 3 is that the inside of the fail safe LSI of expression present embodiment constitutes and the synoptic diagram of external unit.Fail safe LSI has theinternal bus 12A and the 12B of theprocessor 11A of 2 systems and 11B, 2 systems; as 2 exterior I/F of system, have high-speed memory I/F circuit F circuit imput output circuit 15A and 15B.As external device (ED) separately, on high-speed memory I/F circuit external RAM external ROM F circuit 14A and the 14B.In addition, failsafe LSI 10 has comparison means 20 and common systeminternal bus 21, as common system exterior I/F, has system bus I/F circuit 22 and network I/F circuit 23.As external device (ED) separately, on system bus I/F circuit 22, connectedsystem bus bridge 221, on network I/F circuit 23, connected networked physics layer 231.From the normalanomalous discrimination signal 200 of comparison means 20 outputs.
Fig. 4 is the synoptic diagram of summary of the distribution that connected of common systeminternal bus 21 of expression present embodiment.Connected on the common systeminternal bus 21 and comparison means 20 between I/F signal 205, and system bus I/F circuit 22 between I/F signal 222, and network I/F circuit 23 between I/F signal 232.I/F signal 205,222,232 is separated into themaster port 205M that is used for read/write is required to supply to internal bus respectively, and 222M, 232M and being used to accept theauxiliary port 205S that the read/write from internal bus requires, 222S, 232S.In the present embodiment, although 3 modules that common systeminternal bus 21 is connected all have master port and auxiliary port, usually, only have any one port and also be fine.The number of modules difference that theinternal bus 12A and the 12B of 2 systems only is connected, owing to have formation and the function same with common systeminternal bus 21, therefore omitted detailed explanation, still, for example and the I/F between high-speed memory I/F circuit 13A and the 13B only have auxiliary port.
Fig. 5 is that the inside of the common systeminternal bus 21 of expression present embodiment constitutes and the synoptic diagram of the details of the distribution that connected.In Fig. 5, separate easily for the flow direction that makes signal, separately show master port and auxiliary port.Common systeminternal bus 21 constitutes by bus control circuit 211 with to the distribution of each port.Bus control circuit 211 is made of request control circuit 212 and response control circuit 213.Each master port is made of address (output), write data (output), order (output), mandate (グ ラ Application ト) (input), read data (input), effective (バ リ Star De) (input) these 6 kinds of signals.Each auxiliary port by address (input), write data (input), order (input), the line is busy (PVC ジ one) (output), port sequence number (output), read data (output), effective (output) these 7 kinds of signals formations.The direction of input and output is facing to bus control circuit 211 from each port.The transmission requirement that request control circuit 212 is mediated from each master port is decoded the address, selects the auxiliary port of output destination.Bus reconciliation and geocoding are known technology, and detailed explanation is omitted.Response control circuit 213 is mediated and is returned requirement from the read data of each auxiliary port, and outputs to the master port that requires the source.Response control circuit 213 has the impact damper (buffer) (not diagram) that is used for temporarily keeping the read data that each auxiliary port uses, returning requirement and need not wait for from each auxiliary port.
Fig. 6 is the sequential chart that is used to illustrate the action of common system internal bus 21.In Fig. 6, the action of the write and read of the data betweenexpression master port 205M and auxiliary port 222S.Clock signal shown in the top of common systeminternal bus 21 and figure is synchronous, in per 1 clock period transmission data.When the coding that will represent to write (バ イ ト ラ イ ト) as address 2051M, expression 4 bytes in the address of the register of system bus I/F circuit 22 inside from comparison means 20 at clock period i as write data 2052M, when order 2053M grants bus control circuit 211, request control circuit 212 is judged the engaged condition of not issuing the auxiliary port of destination from the request and the request of other master ports, authorize 2054M to be in effectively (ア サ one ト by making, assert), the notice request source receives requirement.Simultaneously, request control circuit 212 outputs to address 2221S, write data 2222S, order 2223S theauxiliary port 222S of request distribution destination.The system bus I/F circuit 22 thatauxiliary port 222S is connected is according to the address of being accepted, and write data is written to register in module.
When the coding of writing as address 2051M, expression 4 bytes when the address of the register that will represent system bus bridge 221 inside that system bus I/F circuit 22 is connected at clock period j is granted bus control circuit 211 as order 2053M, request control circuit 212 is judged the state of bus, authorize 2054M to be in effectively (assert) by making, requirement is accepted in the notice request source.Simultaneously, request control circuit 212 outputs to address 2221S, order 2223S the auxiliary port 222S of request distribution destination.The system bus I/F circuit 22 that auxiliary port 222S is connected will read to require to supply to system bus bridge 221 according to the address of being accepted.At clock period j+1, system bus I/F circuit 22 makes that the line is busy, and 2227S is in effectively (assert), will not accept the advisory request control circuit 212 of other request.When under the ready situation of returning from the read data of system bus bridge 221 of clock period J+2, system bus I/F circuit 22 will output to response control circuit 213 with effective 2226S as coding and the read data 2225S of the port 205M that requires the source of the expression request of port sequence number 2228S.213 pairs of control circuits of response are by the represented port 205M of port sequence number 2228S, output read data 2055M and effective 2056M.
Like this, use common systeminternal bus 21, carry out data transmission at the intermodule that is connected.Especially, according to this bus, by asking control to separate with response control, even from a module read require, the data transmission that also can not hinder other intermodules realizes so-called separate type issued transaction (ス プ リ Star ト ト ラ Application ザ Network シ ヨ Application), therefore, even as network I/F and system bus I/F, there is the module of carrying out a large amount of DMA data transmission simultaneously, can not occupy bus yet, thereby avoid the bus throughput to reduce.Because the distribution between each port and bus control circuit can become 1pair 1,, also can make the influence of the distribution delay that is applied on the responsiveness of bus integral body become minimum even therefore module is placed physically separated position.
Fig. 7 is the synoptic diagram that the inside of the comparison means 20 of expression present embodiment constitutes.Comparison means 20 is made of alternatingsignal generator 201,bus comparer 202, two-waymultiplexing control circuit 203, and is connected with Ainternal system bus 121A, Binternal system bus 121B, common systeminternal bus 21.
Fig. 8 is the synoptic diagram of action of the alternatingsignal generator 201 of expression present embodiment.Alternatingsignal generator 201 is exported normalanomalous discrimination signal 200 according to the moreinconsistent signal 204 ofbus comparer 202 outputs.When normal or unusual and so on state is outputed to the outside with 1 level signal; owing to do not avoid the fault mode that signal level is fixed on ON (connection) or OFF (disconnection); therefore in railway signaling system etc.; according to prior art, use will be made as normally with the situation that certain frequency repeats ON, OFF, state in addition is made as unusual " alternating signal ".In the present embodiment, alternatingsignal generator 201 is promptly represented output frequency signal under the normal situation at moreinconsistent signal 204 for unanimity, promptly represents outputs level signals under the unusual situation inconsistent.Because the formation logic of alternating signal is known, therefore detailed explanation is omitted.
Fig. 9 is the synoptic diagram that the inside of thebus comparer 202 of expression present embodimentconstitutes.Bus comparer 202 will compare all the time from the signal of Ainternal system bus 121A output and the signal of Binternal system bus 121B output, detecting when inconsistent, connect (ON) more inconsistent signal 204.The data that compare are address 1211MA and 1211MB, write data 1212MA and 1212MB, order 1213MA and 1213MB, the line is busy 1217SA and 1217SB, port sequence number 1218SA and 1218SB, read data 1215SA and 1215SB, effectively 1216SA and 1216SB, even detect at the same time when inconsistent, the trigger ofbus comparer 202 inside also is set, and moreinconsistent signal 204 becomes ON (conducting) former state.And, although it is known in order to detect the misoperation of bus comparer self, comparer is multiplexed, on each certain hour, intentionally produce wrong technology again, in the present embodiment, the logic of the comparer of high reliability is as known, and detailed explanation is omitted.
Figure 10 is the synoptic diagram that the inside of the two-waymultiplexing control circuit 203 of expression present embodiment constitutes.Two-waymultiplexing control circuit 203 just will output to common systeminternal bus 21 from the signal that Ainternal system bus 121A exports as long as do not detect more inconsistently with bus comparer 202.That is, with address 1211MA, write data 1212MA, order 1213MA, the line is busy 1217SA, port sequence number 1218SA, read data 1215SA, effectively 1216SA is respectively as address 2051M, write data 2052M, order 2053M, the line is busy 2057S, port sequence number 2058S, readdata 2055S, effectively 2056S output.Detecting when more inconsistent, suppress order 1213MA and the effectively output of 1216SA by moreinconsistent signal 204, and therefore the distribution of common systeminternal bus 21 request of can not detecting and response, has stoped will become inconsistent data and output to common systeminternal bus 21.
Delivered to Ainternal system bus 121A and Binternal system bus 121B simultaneously from the signal of common systeminternal bus 21 outputs.That is, authorize 2054M, read data 2055M, effective 2056M, address 2051S, write data 2052S, order 2053S to be delivered to respectively and authorize 1214MA and 1214MB, read data 1215MA and 1215MB, effective 1216MA and 1216MB, address 1211SA and 1211SB, write data 1212SA and 1212SB, order 1213SA and 1213SB.Like this, by two-waymultiplexing control circuit 203, from common systeminternal bus 21, see that Ainternal system bus 121A and Binternal system bus 121B are as 1 bus (port 205), the action of Ainternal system bus 121A and Binternal system bus 121B is not regularly staggered yet, and therefore the processing in the treating apparatus of 2 systems is not staggered yet.
Figure 11 is the synoptic diagram that the inside of the generalimput output circuit 15A of expression present embodiment constitutes.Generalimput output circuit 15B also is same formation.Generalimput output circuit 15A has universal I read data register (PIORR_A) 151A, universal I write data register (PIOWR_A) 152A, universal I function setting register (PIOFR_A) 153A, and these registers are via the reading and writing ofinternal bus 12A byprocessor 11A value.PIORR_A and PIOWR_A have 8 data width, viainputoutput buffer 154A, are connected with theexternal signal line 150A of LSI 10.PIOFR_A has 1 data width, in its value is to become data output under 0 the situation, and the value of the last setting of PIOWR_A is output to external signal line 150A.Be to become the data input under 1 the situation in the value of PIOFR_A, the signal level ofexternal signal line 150A is imported into PIORR_A.
Figure 12 is used to illustrate the logic circuit arrangements in the LSI chip 100 of present embodiment and the synoptic diagram of input/output pads configuration.The treating apparatus of 2 systems causes identical mistake for fear of single main cause in both systems, wishing to leave in chip as much as possible, distance is configured.For this reason, the logic circuit arrangements of present embodiment, by treating apparatus in the left side of chip configuration A system, the treating apparatus in the right side of chip configuration B system, between is the exterior I/F of central portion configuration comparison means and common system, and the A system is separated with the logical circuit of B system.And, by the layout in the treating apparatus of B system being made as the transposition up and down of A system, make the distance between the identity logic circuit of A system and B system become maximum.Although the configuration of input/output pads becomes adjacent relation with logic circuit arrangements, but in the present embodiment, configuration makes the input/output pads of signal that will be relevant with the memory I/F of A system be in the left side of chip, the input/output pads of the signal relevant with the memory I/F of B system is in chip the right, the input/output pads of the signal relevant with exterior I/F except that the A system is in the left lower side of chip, the input/output pads of the signal relevant with exterior I/F except that the B system is in the top right-hand side of chip, thereby the signal of the signal of A system and B system is configured to the position at diagonal angle in the chip periphery.The input/output pads of the signal relevant with common system exterior I/F is configured in the bottom and upper segment of chip, feasible Signal Separation with A system and B system.And, in the present invention, the arrangement side of each I/F is that each I/F signal of A system and B system is configured to the diagonal angle respectively, and it is important will be therebetween separating with the signal of common system, details for the concrete boundary position of the concrete signal radical of each I/F, each I/F, concrete signal in each I/F are arranged does not mention.About chip, direction up and down and so on also is relative, be not limited in the shown direction of present embodiment.
And, in the configuration of the input/output pads of reality, the reservation pad of using such as power supply and diagnostic function etc., it is frequent having the situation of constraint in the input/output pads design.When in input/output pads configuration, existing under the situation of constraint, whole signals is disposed at the input/output pads of diagonal position with respect to the central point of chip, be difficult in reality.Imprecision of the present invention requires the signal configures to the input/output pads of diagonal position, as long as roughly the signal configures with 2 systems is just passable in the position at diagonal angle.For example, if putting in order of each I/F unit becomes the diagonal angle, do not hinder even between the signal under each I/F, change configuration yet.
Figure 13 is the synoptic diagram of external terminal configuration that is used to illustrate the LSI 10 of present embodiment.Figure 13 (a) be the indicated viewpoint of the outward appearance of LSI 10 in Figure 13 (b) promptly from LSI 10 just above the perspective pin configuration synoptic diagram.In the present embodiment, do not have configures signal pins, become the clear area at the central portion that encapsulates.External terminal configuration is same with logic circuit arrangements and input/output pads configuration in the LSI chip 100 shown in Figure 12, configuration makes the input and output pin of signal that will be relevant with the memory I/F of A system be in the left side of encapsulation, the input and output pin of the signal relevant with the memory I/F of B system is in encapsulation the right, the input and output pin of the signal relevant with exterior I/F except that the A system is in the left lower side of encapsulation, the input/output signal of the signal relevant with exterior I/F except that the B system is in the top right-hand side of encapsulation, thereby the signal pin of the signal of A system and B system is configured to the position at diagonal angle in the encapsulation periphery.The input and output pin of the signal relevant with common system exterior I/F is configured in the bottom and upper segment of encapsulation, makes the A system is separated with the signal pin of B system.And, in the present invention, the arrangement side of each I/F is that each I/F signal pin of A system and B system is configured to the diagonal angle with respect to the central point of encapsulation respectively, and it is important will be therebetween separating with the signal pin of common system, details for the concrete boundary position of the concrete signal pin number of each I/F, each I/F, concrete signal pin in each I/F are arranged does not mention.About encapsulation, direction up and down and so on also is relative, be not limited in the shown direction of present embodiment.
And, in the configuration of the signal pin of reality, the reservation pin of using such as power pin and diagnostic function etc., it is frequent having the situation of constraint on package design.When in pin configuration, existing under the situation of constraint, whole signal pins is disposed at diagonal position with respect to the central point that encapsulates, be difficult in reality.Imprecision of the present invention requires the pin configuration to diagonal position, as long as it is just passable roughly the signal pin of 2 systems to be configured in the position at diagonal angle.For example, if putting in order of each I/F unit becomes the diagonal angle, do not hinder even then between the signal pin under each I/F, change configuration yet.
Figure 14 be the expression present embodiment lift-launch the synoptic diagram of the component configuration on the electronic circuit board 30 of LSI 10 and external device (ED).On the high-speed memory I/F of fail safe LSI 10 circuit 13A and 13B, be connected RAM-A1 (1311A), RAM-A2 (1312A), RAM-B1 (1311B) and RAM-B2 (1312B), externally be connected ROM-A (141A) and ROM-B (141B) on bus I/F circuit 14A and the 14B.Connected system bus bridge LSI221 on the system bus I/F of fail safe LSI 10 circuit 22 connects networked physics layer LSI231 on network I/F circuit 23.The stain at angle of representing the figure of these external device (ED)s is that the mark (イ Application デ Star Network ス マ one Network) of differentiating semiconductor device is the symbol of the lift-launch direction of parts.In device that the A system is connected and device that the B system is connected, same with the configuration of signal pin, become up and down and put upside down.Be connected to state notifying with connector 2000 from the normal anomalous discrimination signal 200 of comparison means 20 output, and with the outside of state notifying electronic circuit board 30.Be connected to system bus with connector 2210 from the signal of system bus bridge LSI 221 output, and on the substrate that separates with electronic circuit board 30, exchange bus signals.Be connected to network with connector 2310 from the signal of networked physics layer LSI 231 output, and on the substrate that separates with electronic circuit board 30 the exchange network signal.As present embodiment, by at the relevant signal pin of the configuration of the top of LSI 10 and network I/F circuit 23, at the relevant signal pin of bottom configuration and system bus I/F circuit 22, can be on substrate circuitous and chaotic from each I/F to each external circuit distribution and draw, therefore, the design cost of substrate and performance all become favourable.
In theelectronic circuit board 30 of Figure 14, the regional 300B (hatched zone among the figure) that the regional 300A (hatched zone among the figure) of RAM-A1 (1311A) and RAM-A2 (1312A) has promptly been installed in the signal pin zone relevant with the high-speed memory I/F circuit 13A ofLSI 10 and RAM-B1 (1311B) and RAM-B2 (1312B) have promptly been installed in relevant signal pin zone with the high-speed memory I/F circuit 13B ofLSI 10 is a supply voltage and in addition regional different zone.Particularly, high-speed memory I/F is the supply voltage of 2.5V, and I/F in addition is 3.3V.Like this, different voltage regime can be divided right and left in the present embodiment, therefore,, the influence that action applied to the high-speed RAM of the system of opposition side is diminished for the noise of the action of following high-speed RAM.And essence of the present invention is, is what kind of supply voltage or has several different voltage regime by whichever I/F, all the identical function I/F of 2 systems is configured in the position at diagonal angle, thereby can make mutual interference for minimum.
To Figure 18 the second embodiment of the present invention is described according to Figure 15.In as the fail safe LSI of object of the present invention, set under the multiplexed situation of pin; relate between the signal relevant with the treating apparatus of 2 systems or the pin between the signal of common system multiplexed; be the problem that in the configuration of exterior I/F that first embodiment addresses, should solve, also can be with the diagonal angle of the signal configures relevant at LSI with the treating apparatus of 2 systems.But the pin of signal that relates to signal relevant with the treating apparatus of 2 systems and common system is multiplexed, also can be configured as second embodiment that addresses in view of the above.
Figure 15 is that the inside of the fail safe LSI of expression second embodiment constitutes and the synoptic diagram of external unit.With the difference of Fig. 3 of first embodiment be: have generalimput output circuit 24A and 24B and pinfunction selector switch imput output circuit 15A is not directly connected to the outside ofLSI 10, and by pinfunction selector switch imput output circuit 24A of common system together, selectively be connected to the outside, promptly multiplexed by pin.
Figure 16 is the synoptic diagram that the inside of expression generalimput output circuit 15A, the generalimput output circuit 24A of second embodiment and pinfunction selector switch 25A constitutes.Generalimput output circuit 15B, general imput output circuit 24B and pinfunction selector switch 25B also are same formations.Generalimput output circuit 15A is identical with first embodiment, have universal I read data register (PIORR_A) 151A, universal I write data register (PIOWR_A) 152A, universal I function setting register (PIOFR_A) 153A, these registers are via the reading and writing ofinternal bus 12A byprocessor 11A value.Generalimput output circuit 24A has universal I read data register (PIORR_C1) 241A, universal I write data register (PIOWR_C1) 242A, universal I function setting register (PIOFR_C1) 243A, the reading and writing that access is worth by fromprocessor internal bus 21 of these registers.
Pinfunction selector switch 25A is by universal I mask register (PIOSR_A) 251A andselect circuit 252A to constitute.The circuit that the register of PIOSR_A is taken (not diagram) is positioned at generalimput output circuit 15A, via the reading and writing ofinternal bus 12A byprocessor 11A value.PIORR_A and PIOWR_A have 8 data width, and PIOFR_A has 1 data width, are connected to select circuit 252A.PIORR_C1 and PIOWR_C1 have 8 data width, and PIOFR_C1 has 1 data width, are connected to select circuit 252A.PIOSR_A has 1 data width, is under 0 the situation in its value, selects the function of generalimput output circuit 24A, is under 1 the situation in its value, selects the function of general imput output circuit 15A.That is, under the situation of the function of having selected generalimput output circuit 24A, PIORR_C1 is connected with theexternal signal line 250A ofLSI 10 viainputoutput buffer 252A with PIOWR_C1, and decides the direction of input and output according to the value of PIOFR_C1.Under the situation of the function of having selected generalimput output circuit 15A, PIORR_A is connected with theexternal signal line 250A ofLSI 10 viainputoutput buffer 252A with PIOWR_A, and decides the direction of input and output according to the value of PIOFR_A.
Figure 17 is used to illustrate the logic circuit arrangements in theLSI chip 100 of second embodiment and the synoptic diagram of input/output pads configuration.With the difference of Figure 12 be: disposed at the lower left quarter of chip and be used for pin function selector switch that the exterior I/F of A system and common system exterior I/F are switched, disposed at the upper right quarter of chip and to be used for pin function selector switch that the exterior I/F of B system and common system exterior I/F are switched, the input/output pads that has disposed between the input/output pads of relevant signal at the input/output pads of the signal relevant with the exterior I/F of A system of lower left quarter with common system exterior I/F with the signal correction of being switched by the pin function selector switch is A system/common system Mixed Zone, disposed between the input/output pads of relevant signal at the input/output pads of the signal relevant of upper right quarter with common system exterior I/F with the exterior I/F of B system with input/output pads by the signal correction of pin function selector switch switching be B system/common system Mixed Zone.
The difference of Figure 18 is the synoptic diagram of external terminal configuration that is used to illustrate theLSI 10 of second embodiment. and Figure 13 is: same with Figure 17; The input and output pin that has disposed between the input and output pin of relevant signal at the input and output pin of the signal relevant with the exterior I/F of A system of lower left quarter with common system exterior I/F with the signal correction of being switched by the pin function selector is A system/common system Mixed Zone, and having disposed with input and output pin by the signal correction of pin function selector switching between the input and output pin of relevant signal at the input and output pin of the signal relevant with the exterior I/F of B system of upper right quarter with common system exterior I/F is B system/common system Mixed Zone. When the pin of the signal that carries out signal relevant with 2 system handles devices and common system is multiplexed,, can prevent to destroy the symmetry of the signal of A system and B system by becoming the such pin configuration of this second embodiment.
Figure 19 is the synoptic diagram of summary that expression has the fail safe LSI of the physical arrangement different with first embodiment.Figure 19 (a) is the synoptic diagram in the cross section of expression fail safe LSI, and the exterior I of LSI chip/F signal and power supply are connected to base plate for packaging by projection (バ Application プ) 107 on the chip.Figure 19 (b) is the vertical view that removes the state behind the seal member from fail safe LSI, and its expression LSI chip 100 is by being configured in circuit face on the base plate for packaging towards the bottom, and is connected on the base plate for packaging by projection 107 on the chip.Figure 19 (c) is the synoptic diagram of the circuit face of expression LSI chip, has disposed the treating apparatus of B system in the left side of LSI chip, has disposed the treating apparatus of A system on the right side, in central configuration the circuit of common system.But the external terminal of LSI encapsulation is identical with first embodiment, has disposed the signal pin of A system in the left side of LSI, has disposed the signal pin of B system on the right side, at the signal pin that has disposed common system up and down.That is, as this figure, when overleaf chip being installed, the signal configures of LSI chip and LSI encapsulation becomes reversed left to right.
Figure 20 is the synoptic diagram that is used to illustrate the external terminal configuration of the fail safe LSI with external terminal structure different with first embodiment.Figure 20 (a) is the situation of first embodiment, is the situation that does not have external terminal at the central portion of encapsulation, has disposed the signal pin of A system in the left side of LSI, has disposed the signal pin of B system on the right side, at the signal pin that has disposed common system up and down.But, in the figure, represent not to be the power pin (also comprising ground pin) of I/F signal with stain.And the configuration of whole number of pin, power pin and quantity depend on the design of encapsulation and change, and what kind of position relation the signal pin that the figure shows A system, B system and common system is installed into.Figure 20 (b) also has external terminal at the central portion of encapsulation, but central portion is all to be the situation of power pin, has disposed the signal pin of A system in the left side of LSI, disposed the signal pin of B system on the right side, at the signal pin that has disposed common system up and down.Owing to do not have signal pin at central portion, therefore same with Figure 20 (a), the signal pin of A system and B system separates by the signal pin of common system.Figure 20 (c) also has external terminal at the central portion of encapsulation, it is the situation that central portion also becomes signal pin, disposed the signal pin of A system in the left side of LSI, disposed the signal pin of B system on the right side, at the signal pin of common system that reached central configuration up and down.Like this, by the signal pin at central portion configuration common system, same with other examples, the signal pin of A system and B system separates by the signal pin of common system.
Claims (20)
Translated fromChineseApplications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009296659AJP5386342B2 (en) | 2009-12-28 | 2009-12-28 | LSI, Fail-safe LSI for railway, Electronic equipment, Electronic equipment for railway |
| JP2009-296659 | 2009-12-28 |
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| CN102110033Atrue CN102110033A (en) | 2011-06-29 |
| CN102110033B CN102110033B (en) | 2015-04-15 |
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| CN201010621634.0AExpired - Fee RelatedCN102110033B (en) | 2009-12-28 | 2010-12-28 | LSI, fail-safe LSI for railways, electronic device, and electronic device for railways |
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| Country | Link |
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| JP (1) | JP5386342B2 (en) |
| CN (1) | CN102110033B (en) |
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| WO (1) | WO2011081052A1 (en) |
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| CN1617334A (en)* | 2003-09-25 | 2005-05-18 | 罗姆股份有限公司 | Semiconductor device and electronic apparatus equipped with the semiconductor device |
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| JPH07295844A (en)* | 1994-04-28 | 1995-11-10 | Hitachi Ltd | Fail-safe control device and train control device |
| JP4401521B2 (en)* | 2000-03-08 | 2010-01-20 | 日本信号株式会社 | Duplex information processing device |
| JP2002135963A (en)* | 2000-10-19 | 2002-05-10 | Nissin Electric Co Ltd | Protective relay |
| JP2005049967A (en)* | 2003-07-30 | 2005-02-24 | Toshiba Corp | Fail-safe processor and railway safety control device |
- 2009
- 2009-12-28JPJP2009296659Apatent/JP5386342B2/ennot_activeExpired - Fee Related
- 2010
- 2010-12-21GBGB1211339.5Apatent/GB2489353A/ennot_activeWithdrawn
- 2010-12-21WOPCT/JP2010/072953patent/WO2011081052A1/enactiveApplication Filing
- 2010-12-28CNCN201010621634.0Apatent/CN102110033B/ennot_activeExpired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1617334A (en)* | 2003-09-25 | 2005-05-18 | 罗姆股份有限公司 | Semiconductor device and electronic apparatus equipped with the semiconductor device |
| CN1881810A (en)* | 2005-06-06 | 2006-12-20 | 株式会社瑞萨科技 | Radio frequency circuit for multi-mode operation |
| JP2006031727A (en)* | 2005-08-17 | 2006-02-02 | Hitachi Ltd | Fail-safe controller |
| CN101102177A (en)* | 2007-08-20 | 2008-01-09 | 杭州华三通信技术有限公司 | A method and device for implementing master-standby controller switchover |
Also Published As
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| CN102110033B (en) | 2015-04-15 |
| GB201211339D0 (en) | 2012-08-08 |
| GB2489353A (en) | 2012-09-26 |
| JP5386342B2 (en) | 2014-01-15 |
| WO2011081052A1 (en) | 2011-07-07 |
| JP2011138852A (en) | 2011-07-14 |
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