CN102097428A

Movatterモバイル変換

Info

Publication number: CN102097428A
Application number: CN2009102540484A
Authority: CN
Inventors: 黄耀生
Original assignee: Raydium Semiconductor Corp
Current assignee: Raydium Semiconductor Corp
Priority date: 2009-12-15
Filing date: 2009-12-15
Publication date: 2011-06-15

Abstract

An integrated circuit wafer and a method for cutting the integrated circuit wafer. The integrated circuit wafer comprises a wafer substrate, a plurality of integrated circuits, a plurality of test keys, a protective layer and a plurality of grooves. The integrated circuits are formed on the wafer substrate in a matrix distribution manner. The test keys are formed between the integrated circuits, respectively. The protective layer covers one side of the integrated circuits of the wafer substrate. The trench is formed between the integrated circuit and the test key in a manner extending downward from the surface of the protective layer. The integrated circuit wafer cutting method comprises the following steps: forming an integrated circuit and a test key on a wafer substrate; forming a protective layer; forming a plurality of grooves; and applying a force to the region of the protective layer sandwiched between the two adjacent parallel trenches to separate the wafer substrate along the bottom of at least one of the two adjacent parallel trenches and down along the crystal lattice of the wafer substrate.

Description

Translated fromChinese

集成电路晶圆以及集成电路晶圆切割方法Integrated circuit wafer and integrated circuit wafer cutting method

技术领域technical field

本发明是关于一种集成电路晶圆以及一种集成电路晶圆切割方法。其中，可藉由集成电路晶圆切割方法形成集成电路晶粒。The invention relates to an integrated circuit wafer and an integrated circuit wafer cutting method. Wherein, the integrated circuit die can be formed by cutting the integrated circuit wafer.

背景技术Background technique

硅晶圆是目前制作集成电路的基底材料(Substrate)，透过集成电路制造技术，经过一系列繁复的化学、物理和光学程序，完成的集成电路晶圆上可产生出数以千、百计的晶粒(die)。这些晶粒经由测试、切割、封装等过程，可进一步成为一颗颗具有各种功能的集成电路产品。Silicon wafers are currently the substrate material (Substrate) for making integrated circuits. Through integrated circuit manufacturing technology, after a series of complicated chemical, physical and optical procedures, thousands or hundreds of chips can be produced on the completed integrated circuit wafer. The grain (die). After testing, dicing, packaging and other processes, these dies can further become individual integrated circuit products with various functions.

如图1A及图1A中区域80的PP纵切面放大的图1B所示的习知技术，习知集成电路晶圆90包含晶圆基板100、复数个集成电路300、复数个测试键400及保护层500。习知技术进行晶圆切割时通常是以切割刀沿相邻的集成电路300间的路径对集成电路晶圆90施外力K。由于切割时仅以切割刀直接对集成电路晶圆90进行切割，因此，集成电路晶圆90会受切割应力破坏而产生有裂痕及损坏的情形。另一方面，测试键400分布在集成电路300间，亦即在切割路径上，故习知技术在切割时也容易因破坏测试键产生的金属碎屑飞溅至集成电路而导致良率下降。以上集成电路晶圆以及集成电路晶圆切割方法有改善的空间。As shown in Fig. 1A and the prior art shown in Fig. 1B of the enlarged PP longitudinal section ofregion 80 in Fig. 1A, the conventionalintegrated circuit wafer 90 comprises awafer substrate 100, a plurality ofintegrated circuits 300, a plurality oftest keys 400 and protection devices.Layer 500. In conventional wafer dicing, an external force K is usually applied to the integratedcircuit wafer 90 by a dicing knife along a path between adjacent integratedcircuits 300 . Since the integratedcircuit wafer 90 is only directly cut by a dicing knife during dicing, the integratedcircuit wafer 90 will be damaged by the cutting stress, resulting in cracks and damage. On the other hand, thetest keys 400 are distributed among the integratedcircuits 300 , that is, on the cutting path, so the conventional technology is prone to drop the yield rate due to metal debris generated by destroying the test keys and splashing to the integrated circuits during cutting. There is room for improvement in the above integrated circuit wafer and the cutting method of the integrated circuit wafer.

发明内容Contents of the invention

本发明的主要目的为提供一种集成电路晶圆，分离成集成电路晶粒的良率较高。The main purpose of the present invention is to provide an integrated circuit wafer, which can be separated into integrated circuit crystal grains with a high yield rate.

本发明的另一目的为提供一种集成电路晶圆切割方法，具有较佳的集成电路晶圆切割良率。Another object of the present invention is to provide a method for dicing integrated circuit wafers, which has better dicing yield of integrated circuit wafers.

本发明的集成电路晶圆包含晶圆基板、多个集成电路、多个测试键、保护层以及多条沟槽。集成电路以矩阵分布方式形成于晶圆基板上。测试键分别形成于集成电路之间。一保护层覆盖晶圆基板的集成电路的一侧。沟槽以自保护层表面向下延伸的方式形成于集成电路及测试键之间。The integrated circuit wafer of the present invention includes a wafer substrate, a plurality of integrated circuits, a plurality of test keys, a protection layer and a plurality of grooves. The integrated circuits are formed on the wafer substrate in a matrix distribution manner. Test keys are respectively formed between the integrated circuits. A protective layer covers the integrated circuit side of the wafer substrate. The groove is formed between the integrated circuit and the test key in a manner extending downward from the surface of the protection layer.

测试键是供晶圆基板接受度测试使用。测试键包含晶体管、电容、电阻、N型半导体、P型半导体、复型半导体或金属线元件。保护层包含二氧化硅或氮化硅。沟槽延伸至晶圆基板表面，晶圆基板表面构成沟槽的槽底。沟槽延伸也可进入晶圆基板。沟槽的侧壁为蚀刻表面。沟槽的侧壁为平滑表面。沟槽的侧壁近似垂直。沟槽的侧壁与晶圆基板表面的夹角介于88°至90°。沟槽的宽度小于5μm。The test key is for wafer substrate acceptance testing. The test key includes transistors, capacitors, resistors, N-type semiconductors, P-type semiconductors, complex semiconductors or metal wire components. The protective layer contains silicon dioxide or silicon nitride. The groove extends to the surface of the wafer substrate, and the surface of the wafer substrate forms the groove bottom of the groove. Trench extensions can also be made into the wafer substrate. The sidewalls of the trenches are etched surfaces. The sidewall of the groove is a smooth surface. The sidewalls of the trench are approximately vertical. The included angle between the side wall of the trench and the surface of the wafer substrate is between 88° and 90°. The width of the trench is less than 5 μm.

本发明的集成电路晶圆切割方法，包含以下步骤：于晶圆基板上形成多个集成电路以及多个测试键，其中集成电路是以矩阵分布，测试键分别形成于集成电路之间；形成保护层以覆盖晶圆基板的集成电路的一侧；形成多条沟槽，沟槽以自保护层表面向下延伸的方式形成于集成电路及测试键之间；以及施外力于保护层在两并排相邻的沟槽所夹的区域，使晶圆基板沿两并排相邻沟槽至少其中之一的底部向下沿晶圆基板的晶格分离。The integrated circuit wafer cutting method of the present invention includes the following steps: forming a plurality of integrated circuits and a plurality of test keys on the wafer substrate, wherein the integrated circuits are distributed in a matrix, and the test keys are respectively formed between the integrated circuits; forming protection Layer to cover one side of the integrated circuit of the wafer substrate; form a plurality of grooves, and the grooves are formed between the integrated circuit and the test key in a manner extending downward from the surface of the protective layer; and apply external force to the protective layer on both sides The area between the adjacent trenches enables the wafer substrate to be separated downward along the crystal lattice of the wafer substrate along the bottom of at least one of the two adjacent trenches.

保护层形成步骤包含使用化学气相沉积或物理气相沉积制程形成保护层。沟槽形成步骤包含使用蚀刻制程形成沟槽。沟槽形成步骤包含使沟槽延伸至晶圆基板表面。沟槽形成步骤包含使沟槽延伸进入晶圆基板。形成的沟槽的侧壁近似垂直。沟槽的侧壁与晶圆基板表面的夹角介于88°至90°。沟槽的宽度小于5μm。外力包含以切割刀具沿保护层于两并排相邻的沟槽所夹的区域划压。The protective layer forming step includes forming the protective layer using chemical vapor deposition or physical vapor deposition process. The trench forming step includes forming the trenches using an etching process. The trench forming step includes extending the trench to the surface of the wafer substrate. The trench forming step includes extending the trench into the wafer substrate. The sidewalls of the formed trenches are approximately vertical. The included angle between the side wall of the trench and the surface of the wafer substrate is between 88° and 90°. The width of the trench is less than 5 μm. The external force includes using a cutting tool to draw pressure along the protective layer on the area clamped by two adjacent grooves.

集成电路晶粒包含晶圆基板、集成电路以及保护层。集成电路形成于晶圆基板上。保护层覆盖晶圆基板的集成电路的一侧。其中，晶圆基板及保护层的侧壁分别为平滑表面。晶圆基板的侧壁近似垂直。晶圆基板的侧壁与晶圆基板表面的夹角介于88°至90°。保护层的侧壁近似垂直。保护层的侧壁与晶圆基板表面的夹角介于88°至90°。保护层包含二氧化硅或氮化硅。保护层的侧壁为蚀刻表面。晶圆基板及保护层的侧壁是共平面。晶圆基板的侧壁凸出于保护层的侧壁。晶圆基板的侧壁的上缘与保护层的侧壁是共平面，晶圆基板的侧壁的下部凸出于保护层的侧壁。An integrated circuit die includes a wafer substrate, an integrated circuit, and a protective layer. Integrated circuits are formed on wafer substrates. A protective layer covers the integrated circuit side of the wafer substrate. Wherein, the sidewalls of the wafer substrate and the protection layer are smooth surfaces respectively. The sidewalls of the wafer substrate are approximately vertical. The angle between the sidewall of the wafer substrate and the surface of the wafer substrate is between 88° and 90°. The sidewalls of the protective layer are approximately vertical. The included angle between the sidewall of the protective layer and the surface of the wafer substrate is between 88° and 90°. The protective layer contains silicon dioxide or silicon nitride. The sidewall of the protective layer is an etched surface. The sidewalls of the wafer substrate and the protection layer are coplanar. The sidewall of the wafer substrate protrudes from the sidewall of the protective layer. The upper edge of the side wall of the wafer substrate is coplanar with the side wall of the protective layer, and the lower part of the side wall of the wafer substrate protrudes from the side wall of the protective layer.

本发明的优点是集成电路晶圆的分离成集成电路晶粒的良率高，用本发明的集成电路晶圆切割方法时，具有较佳的集成电路晶圆切割良率。The advantage of the present invention is that the yield rate of separating the integrated circuit wafer into integrated circuit crystal grains is high, and when the integrated circuit wafer cutting method of the present invention is used, it has a better cutting yield rate of the integrated circuit wafer.

附图说明Description of drawings

图1A及图1B为习知技术示意图；1A and 1B are schematic diagrams of conventional technologies;

图2A为本发明实施例上视示意图；Figure 2A is a schematic diagram of an upper view of an embodiment of the present invention;

图2B至图3B为本发明不同实施例示意图；2B to 3B are schematic diagrams of different embodiments of the present invention;

图4A及图4B为本发明较佳实施例示意图；4A and 4B are schematic diagrams of a preferred embodiment of the present invention;

图5为本发明集成电路晶圆切割方法的实施例流程图。FIG. 5 is a flowchart of an embodiment of the method for cutting an integrated circuit wafer according to the present invention.

符号说明Symbol Description

100晶圆基板100 Wafer Substrate

101侧壁101 side wall

110晶圆基板表面110 wafer substrate surface

300集成电路300 integrated circuits

400测试键400 test keys

500保护层500 layers of protection

601路径601 path

602路径602 path

700沟槽700 groove

700’沟槽700' Trench

701侧壁701 side wall

740区域740 area

80区域80 area

800区域800 area

90集成电路晶圆90 integrated circuit wafer

900集成电路晶圆900 integrated circuit wafer

910集成电路晶粒910 integrated circuit die

1011上缘1011 upper edge

1012下部1012 lower part

F外力F external force

K外力K external force

具体实施方式Detailed ways

如图2A及图2A中区域800的PP纵切面放大的图2B所示的实施例，本发明的集成电路晶圆900包含晶圆基板100、多个集成电路300、多个测试键400、保护层500以及多条沟槽700。其中，集成电路300是以矩阵分布方式形成于晶圆基板100上。具体而言，在如图2A所示的实施例中，集成电路300以方型为单位，呈矩阵分布方式形成于晶圆基板100上，以便对准进行制造及切割，但不以实施例所示为限。2A and the embodiment shown in FIG. 2B in which the PP longitudinal section ofregion 800 in FIG. 2A is enlarged,integrated circuit wafer 900 of the present invention includeswafer substrate 100, multipleintegrated circuits 300,multiple test keys 400,protection layer 500 and a plurality oftrenches 700 . Wherein, theintegrated circuits 300 are formed on thewafer substrate 100 in a matrix distribution manner. Specifically, in the embodiment shown in FIG. 2A , theintegrated circuits 300 are formed on thewafer substrate 100 in a matrix distribution in square units for alignment, manufacturing and dicing. shown as a limit.

测试键400分别形成于集成电路300之间。举例而言，测试键400形成于后续用于分割晶圆基板100，而形成含有集成电路300的多个晶粒的切割道上。其中，测试键400供晶圆基板接受度测试(Wafer Acceptance Test)使用。具体而言，可藉由对分布在晶圆基板100上的测试键400进行电性测试获知晶圆基板100的接受度(亦即品质是否良好)。测试键400包含晶体管、电容、电阻、N型半导体、P型半导体、复型半导体或金属线元件等。Thetest keys 400 are respectively formed between theintegrated circuits 300 . For example, thetest key 400 is formed on a dicing line that is subsequently used to divide thewafer substrate 100 to form a plurality of dies including the integratedcircuit 300 . Wherein, thetest key 400 is used for the wafer substrate acceptance test (Wafer Acceptance Test). Specifically, the acceptance of the wafer substrate 100 (that is, whether the quality is good) can be known by performing an electrical test on thetest keys 400 distributed on thewafer substrate 100 . Thetest key 400 includes transistors, capacitors, resistors, N-type semiconductors, P-type semiconductors, complex semiconductors, or metal wire components.

保护层500覆盖晶圆基板100的集成电路300的一侧。具体而言，如图2B所示的实施例，集成电路300及测试键400设置于晶圆基板100上，保护层500同时覆盖集成电路300、测试键400及曝露于集成电路300及测试键400外的晶圆基板100。保护层300较佳包含二氧化硅或氮化硅。其中，保护层300的形成可使用化学气相沉积或物理气相沉积制程。Theprotective layer 500 covers one side of theintegrated circuit 300 of thewafer substrate 100 . Specifically, in the embodiment shown in FIG. 2B, theintegrated circuit 300 and thetest key 400 are arranged on thewafer substrate 100, and theprotective layer 500 covers theintegrated circuit 300, thetest key 400 and is exposed to theintegrated circuit 300 and thetest key 400. Theouter wafer substrate 100. Thepassivation layer 300 preferably includes silicon dioxide or silicon nitride. Wherein, theprotective layer 300 can be formed by chemical vapor deposition or physical vapor deposition process.

如图2A及图2B所示的实施例，沟槽700以自保护层500表面向下延伸的方式形成于集成电路300及测试键400之间。换言之，每一测试键400均以沟槽700与相邻的集成电路300相隔。如图2B所示的实施例，沟槽700延伸至晶圆基板100的表面110，晶圆基板100的表面110构成沟槽700的槽底。在较佳实施例中，沟槽700使用蚀刻制程形成，且较佳使用干式电浆蚀刻制程。然而在不同实施例中，沟槽700也可使用湿式化学蚀刻制程形成。由于沟槽700使用蚀刻制程形成，故沟槽700的侧壁701形成蚀刻表面。如图2B所示，侧壁701的蚀刻表面属于平滑表面，且近似垂直，亦即沟槽700的侧壁701与晶圆基板100的表面110的夹角较佳介于88°至90°。其中，沟槽700的宽度较佳是小于5μm，但不以实施例所示为限。In the embodiment shown in FIG. 2A and FIG. 2B , thetrench 700 is formed between theintegrated circuit 300 and thetest key 400 in a manner extending downward from the surface of theprotective layer 500 . In other words, eachtest key 400 is separated from the adjacentintegrated circuit 300 by thegroove 700 . In the embodiment shown in FIG. 2B , thetrench 700 extends to thesurface 110 of thewafer substrate 100 , and thesurface 110 of thewafer substrate 100 constitutes the bottom of thetrench 700 . In a preferred embodiment,trench 700 is formed using an etching process, preferably using a dry plasma etching process. However, in different embodiments, thetrench 700 may also be formed using a wet chemical etching process. Since thetrench 700 is formed using an etching process, thesidewall 701 of thetrench 700 forms an etched surface. As shown in FIG. 2B , the etched surface of thesidewall 701 is smooth and approximately vertical, that is, the angle between thesidewall 701 of thetrench 700 and thesurface 110 of thewafer substrate 100 is preferably between 88° and 90°. Wherein, the width of thetrench 700 is preferably less than 5 μm, but not limited to the embodiment shown.

其中，由于晶圆基板100是经由磊晶制程所制成具有整齐晶格的结晶物，故当一外力F施于保护层500在两并排相邻的沟槽700所夹的区域740(例如测试键400所在的区域)，晶圆基板100会沿两并排相邻沟槽700至少其中之一的底部向下沿晶圆基板100的晶格分离。例如在图2B所示的实施例中，晶圆基板100沿沟槽700’的底部向下沿晶圆基板100的晶格分离。另一方面，由于晶圆基板100沿晶格分离，晶圆基板100分离后形成的侧壁101会如图3所示为平滑表面。换言之，本发明的集成电路晶圆900无需如习知技术以切割工具强行于集成电路300间进行切割，即可将集成电路晶圆900分离成如图2C所示的集成电路晶粒910。因此，应用本发明技术不仅方便，也不会有习知技术因切割时测试键遭到破坏所产生金属碎屑飞溅至集成电路而导致良率下降的问题。Wherein, since thewafer substrate 100 is a crystalline object with a neat crystal lattice made through an epitaxial process, when an external force F is applied to theprotective layer 500 in theregion 740 between two adjacent grooves 700 (such as a test The area where the key 400 is located), thewafer substrate 100 will be separated along the crystal lattice of thewafer substrate 100 downward along the bottom of at least one of the twoadjacent grooves 700 . For example, in the embodiment shown in FIG. 2B , thewafer substrate 100 is separated along the crystal lattice of thewafer substrate 100 down the bottom of the trench 700'. On the other hand, since thewafer substrate 100 is separated along the crystal lattice, thesidewall 101 formed after thewafer substrate 100 is separated will have a smooth surface as shown in FIG. 3 . In other words, theintegrated circuit wafer 900 of the present invention can be separated into integratedcircuit chips 910 as shown in FIG. 2C without using a cutting tool to forcibly cut between theintegrated circuits 300 as in the conventional technology. Therefore, it is not only convenient to apply the technology of the present invention, but also there is no problem in the conventional technology that the test key is destroyed during cutting, and the metal debris generated by the chip splashes to the integrated circuit, resulting in a decrease in yield.

进一步而言，如图2C所示的实施例，本发明的集成电路晶圆900所分离成的集成电路晶粒910包含晶圆基板100、集成电路300以及保护层500。其中，集成电路300形成于晶圆基板100上。保护层500覆盖晶圆基板100的集成电路300的一侧。具体而言，集成电路300设置于晶圆基板100上，保护层500同时覆盖集成电路300及曝露于集成电路300外的晶圆基板100。其中，晶圆基板100的侧壁101及保护层500的侧壁701分别为平滑表面。进一步而言，保护层500的侧壁701即前述图2B的实施例中使用蚀刻制程形成的侧壁701，是蚀刻表面，且近似垂直，亦即侧壁701与晶圆基板100的表面110的夹角介于88°至90°。Further, in the embodiment shown in FIG. 2C , the integrated circuit die 910 separated from theintegrated circuit wafer 900 of the present invention includes thewafer substrate 100 , theintegrated circuit 300 and theprotection layer 500 . Wherein, theintegrated circuit 300 is formed on thewafer substrate 100 . Theprotective layer 500 covers one side of theintegrated circuit 300 of thewafer substrate 100 . Specifically, theintegrated circuit 300 is disposed on thewafer substrate 100 , and theprotective layer 500 simultaneously covers theintegrated circuit 300 and thewafer substrate 100 exposed outside theintegrated circuit 300 . Wherein, thesidewall 101 of thewafer substrate 100 and thesidewall 701 of thepassivation layer 500 are smooth surfaces respectively. Further, thesidewall 701 of theprotection layer 500, that is, thesidewall 701 formed by the etching process in the embodiment of FIG. The included angle is between 88° and 90°.

如图2C所示的实施例，本发明的集成电路晶粒910的晶圆基板100的侧壁101及保护层500的侧壁701是共平面。换言之，如图2B所示，当一外力F施于保护层500在两并排相邻的沟槽700所夹的区域740，晶圆基板100沿路径601向下沿晶圆基板100的晶格分离。分离形成的集成电路晶粒910的保护层500的侧壁701，即如图2C所示延伸与晶圆基板100的侧壁101衔接。其中，侧壁101由晶圆基板100沿晶格分离而形成，其表面性质与平滑的晶圆表面相同。侧壁701由保护层500经蚀刻形成，其表面性质与平滑的保护层表面相同。In the embodiment shown in FIG. 2C , thesidewall 101 of thewafer substrate 100 of the integrated circuit die 910 of the present invention and thesidewall 701 of thepassivation layer 500 are coplanar. In other words, as shown in FIG. 2B , when an external force F is applied to theprotective layer 500 in thearea 740 sandwiched by twoadjacent grooves 700 , thewafer substrate 100 will be separated along thepath 601 downward along the crystal lattice of thewafer substrate 100 . . Thesidewall 701 of thepassivation layer 500 of the separately formed integrated circuit die 910 extends to connect with thesidewall 101 of thewafer substrate 100 as shown in FIG. 2C . Wherein, thesidewall 101 is formed by separating thewafer substrate 100 along the crystal lattice, and its surface property is the same as that of a smooth wafer surface. Thesidewall 701 is formed by etching thepassivation layer 500 , and its surface property is the same as that of a smooth passivation layer surface.

沟槽700的分布方式可视需求而不同，在图2A所示的实施例中，沟槽700为连通晶圆基板100圆周上两点的直线，亦即沟槽700可视为晶圆基板100的弦线。然而在如图2D所示的不同实施例中，沟槽700包围集成电路300的方形线，且相邻的沟槽700方形线彼此不连通。The distribution ofgrooves 700 may vary depending on requirements. In the embodiment shown in FIG. strings. However, in a different embodiment as shown in FIG. 2D , thetrenches 700 surround the square lines of theintegrated circuit 300 , and the square lines ofadjacent trenches 700 are not connected to each other.

在不同实施例中，由于沟槽700槽底具有一定宽度，晶圆基板100可能自沟槽700槽底的不同位置沿不同路径向下沿晶圆基板100的晶格分离，这是自然发生的现象。如图3A所示，当一外力F施于保护层500在两并排相邻的沟槽700所夹的区域740，晶圆基板100沿路径602向下沿晶圆基板100的晶格分离。分离形成的集成电路晶粒910的晶圆基板100的侧壁101即如图3B所示凸出于保护层500的侧壁701。In different embodiments, since the groove bottom of thegroove 700 has a certain width, thewafer substrate 100 may be separated from different positions of the groove bottom of thegroove 700 along different paths down the crystal lattice of thewafer substrate 100, which is a natural occurrence. Phenomenon. As shown in FIG. 3A , when an external force F is applied to theregion 740 of thepassivation layer 500 between twoadjacent trenches 700 , thewafer substrate 100 is separated along thepath 602 downward along the crystal lattice of thewafer substrate 100 . Thesidewall 101 of thewafer substrate 100 of the separated integrated circuit die 910 protrudes beyond thesidewall 701 of theprotection layer 500 as shown in FIG. 3B .

另一方面，如图4A所示的较佳实施例，沟槽700可进一步延伸进入晶圆基板100。当一外力F施于保护层500在两并排相邻的沟槽700所夹的区域740，晶圆基板100沿路径602向下沿晶圆基板100的晶格分离。分离形成的集成电路晶粒910即如图4B所示，晶圆基板100的侧壁101的上缘1011与保护层500的侧壁701是共平面，晶圆基板100的侧壁101的下部1012、凸出于保护层500的侧壁701。On the other hand, thegroove 700 may further extend into thewafer substrate 100 in the preferred embodiment shown in FIG. 4A . When an external force F is applied to theregion 740 of thepassivation layer 500 between twoadjacent grooves 700 , thewafer substrate 100 is separated along thepath 602 downward along the crystal lattice of thewafer substrate 100 . The separated integrated circuit die 910 is as shown in FIG. 4B, the upper edge 1011 of theside wall 101 of thewafer substrate 100 is coplanar with theside wall 701 of theprotective layer 500, and the lower part 1012 of theside wall 101 of thewafer substrate 100 is , protruding from theside wall 701 of theprotection layer 500 .

如图5所示，本发明的集成电路晶圆切割方法，包含：As shown in Figure 5, the integrated circuit wafer cutting method of the present invention includes:

步骤1001，于晶圆基板上形成多个集成电路以及多个测试键，其中，集成电路以矩阵分布，测试键分别形成于集成电路之间。具体而言，是以形成氧化膜、涂布感光剂、结合光罩进行曝光、显影、蚀刻、去光阻、以及添加不纯物等步骤，于晶圆基板上形成集成电路以及测试键。其中，可藉由光罩图案控制集成电路以及测试键的形成位置。Step 1001 , forming a plurality of integrated circuits and a plurality of test keys on a wafer substrate, wherein the integrated circuits are distributed in a matrix, and the test keys are respectively formed between the integrated circuits. Specifically, an integrated circuit and a test key are formed on a wafer substrate by forming an oxide film, coating a photosensitive agent, exposing with a photomask, developing, etching, removing photoresist, and adding impurities. Wherein, the formation positions of the integrated circuit and the test key can be controlled by the mask pattern.

步骤1003，形成保护层以覆盖晶圆基板的集成电路的一侧。其中，保护层的形成可使用化学气相沉积或物理气相沉积制程。保护层包含二氧化硅或氮化硅。Step 1003, forming a protection layer to cover one side of the integrated circuit of the wafer substrate. Wherein, the protective layer can be formed by chemical vapor deposition or physical vapor deposition process. The protective layer contains silicon dioxide or silicon nitride.

步骤1005，形成多条沟槽，沟槽以自保护层表面向下延伸的方式形成于集成电路及测试键之间。沟槽的形成包含使用蚀刻制程，且较佳是使用干式电浆蚀刻制程。然而在不同实施例中，沟槽的形成也可使用湿式化学蚀刻制程或雷射切割。其中，沟槽可如图2B所示延伸至晶圆基板表面110或如图4A所示延伸进入晶圆基板100。Step 1005, forming a plurality of grooves, the grooves extending downward from the surface of the protection layer are formed between the integrated circuit and the test key. Forming the trenches involves using an etching process, preferably using a dry plasma etching process. However, in various embodiments, the trenches may also be formed using a wet chemical etching process or laser dicing. Wherein, the trench may extend to thewafer substrate surface 110 as shown in FIG. 2B or extend into thewafer substrate 100 as shown in FIG. 4A .

步骤1007，施一外力于保护层在两并排相邻的沟槽所夹的区域，使晶圆基板沿两并排相邻沟槽至少其中之一的底部向下沿晶圆基板的晶格分离。外力包含以切割刀具沿保护层于两并排相邻的沟槽所夹的区域划压。其中，切割刀具在此步骤中做为施力的工具，非强行对晶圆基板进行切割。在不同实施例中，也可以一片状物直接按压保护层于两并排相邻的沟槽所夹的区域，使晶圆基板分离。Step 1007 , applying an external force to the protective layer in the region between the two adjacent grooves, so that the wafer substrate is separated downward along the crystal lattice of the wafer substrate along the bottom of at least one of the two adjacent grooves. The external force includes using a cutting tool to draw pressure along the protective layer on the area clamped by two adjacent grooves. Wherein, the cutting tool is used as a force-applying tool in this step, and the wafer substrate is not forcibly cut. In different embodiments, a sheet may also be used to directly press the protective layer on the region between two adjacent grooves in a row, so as to separate the wafer substrate.

虽然前述的描述及图式已揭示本发明的较佳实施例，必须了解到各种增添、许多修改和取代可能使用于本发明较佳实施例，而不会脱离如所附申请专利范围所界定的本发明原理的精神及范围。熟悉本发明所属技术领域的一般技艺者将可体会，本发明可使用于许多形式、结构、布置、比例、材料、元件和元件的修改。因此，本文在此所揭示的实施例应被视为用以说明本发明，而非用以限制本发明。本发明的范围应由后附申请专利范围所界定，并涵盖其合法均等物，并不限于先前的描述。Although the foregoing description and drawings have disclosed preferred embodiments of the present invention, it must be understood that various additions, modifications and substitutions may be applied to the preferred embodiments of the present invention without departing from the scope of the appended patent application spirit and scope of the principles of the invention. Those of ordinary skill in the art to which the invention pertains will appreciate that the invention is applicable to many forms, structures, arrangements, proportions, materials, elements and modifications of elements. Therefore, the embodiments disclosed herein should be regarded as illustrating the present invention rather than limiting the present invention. The scope of the present invention should be defined by the claims of the appended claims and cover their legal equivalents, not limited by the foregoing description.