CN102054873B - Display and its thin film transistor array substrate and thin film transistor - Google Patents

Abstract

The invention relates to a display, a thin film transistor array substrate and a thin film transistor thereof. The display comprises a thin film transistor array substrate, a light-transmitting electrode substrate and a display medium layer arranged between the light-transmitting electrode substrate and the light-transmitting electrode substrate. The thin film transistor array substrate comprises a plurality of thin film transistors with oxide semiconductor layers, wherein grid electrodes and grid insulating layers of the thin film transistors are respectively arranged on the substrate, and the grid insulating layers cover the grid electrodes. The oxide semiconductor layer conformally covers the gate insulating layer and has a channel region located above the gate electrode. The source and the drain of the thin film transistor are respectively arranged on the oxide semiconductor layer and positioned at two sides of the channel region. Since the material of the oxide semiconductor layer is a light-permeable material, the patterning process of the oxide semiconductor layer can be omitted in the process of manufacturing the display, so as to save the cost of the manufacturing process and shorten the time of the manufacturing process.

Description

Translated fromChinese

显示器及其薄膜晶体管阵列基板与薄膜晶体管Display and its thin film transistor array substrate and thin film transistor

技术领域technical field

本发明涉及一种显示装置,特别是涉及一种具有不会因照光而产生漏电流之薄膜晶体管的显示器及其薄膜晶体管阵列基板与薄膜晶体管。The invention relates to a display device, in particular to a display with a thin film transistor which does not generate leakage current due to illumination, a thin film transistor array substrate and a thin film transistor.

背景技术Background technique

反射式显示器是利用经过反射的入射光线做为显示器显示画面的光源。由于反射式显示器不需要配置背光光源，使得元件的耗电量(powerconsumpt ion)降低，且整个显示器在设计上可以较为轻薄，因此近年来已在显示器产业中受到高度重视。A reflective display uses reflected incident light as a light source for displaying images on the display. Because the reflective display does not need to be equipped with a backlight source, the power consumption of the components is reduced, and the entire display can be designed to be thinner and lighter, so it has been highly valued in the display industry in recent years.

另一方面，目前的显示器大多可依其驱动元件而分为有源与无源。一般有源显示器大多是以薄膜晶体管作为驱动元件，且由于非晶硅薄膜晶体管(amorphous silicon thin film transistor,a-Si TFT)的制造工艺简单，价格低廉，因此目前多以非晶硅薄膜晶体管作为有源显示器的驱动元件。On the other hand, most current displays can be classified into active and passive according to their driving components. Generally, active displays mostly use thin film transistors as driving components, and because the manufacturing process of amorphous silicon thin film transistors (a-Si TFTs) is simple and low in price, amorphous silicon thin film transistors are mostly used as drive components at present. Driving elements for active displays.

图1为公知有源显示器之单一像素中薄膜晶体管阵列基板的剖面示意图。请参照图1，在薄膜晶体管阵列基板100的制造工艺中，系先在基板102上形成栅极104，接着再形成覆盖住栅极104的栅绝缘层106。之后，在栅绝缘层106上形成非晶硅半导体层(图未示)。由于非晶硅半导体层不透光，为了增加此像素的开口率(aperture rat io)，接着必须移除部分的非晶硅半导体层，仅留下位于栅极104上方的部分作为通道层108。FIG. 1 is a schematic cross-sectional view of a thin film transistor array substrate in a single pixel of a known active display. Referring to FIG. 1 , in the manufacturing process of theTFT array substrate 100 , thegate 104 is first formed on thesubstrate 102 , and then thegate insulating layer 106 covering thegate 104 is formed. Afterwards, an amorphous silicon semiconductor layer (not shown) is formed on thegate insulating layer 106 . Since the amorphous silicon semiconductor layer is opaque, in order to increase the aperture ratio of the pixel, part of the amorphous silicon semiconductor layer must be removed, leaving only the portion above thegate 104 as thechannel layer 108 .

之后，于栅绝缘层106上形成源极110与漏极112，以覆盖住部分的通道层108。此时，即大致完成薄膜晶体管101的制作。然后，在基板102上形成具有开口116的保护层114，以暴露出部分的漏极112。并且，在保护层114上形成像素电极118，且像素电极118系填入开口116内而与漏极112电性连接。Afterwards, asource electrode 110 and adrain electrode 112 are formed on thegate insulating layer 106 to cover part of thechannel layer 108 . At this point, the fabrication of thethin film transistor 101 is substantially completed. Then, apassivation layer 114 having anopening 116 is formed on thesubstrate 102 to expose part of thedrain electrode 112 . Moreover, apixel electrode 118 is formed on thepassivation layer 114 , and thepixel electrode 118 is filled in theopening 116 to be electrically connected to thedrain 112 .

然而，由于非晶硅材料具有光电特性，因此若在反射式显示器中使用薄膜晶体管阵列100，则当环境光从薄膜晶体管101上方入射至通道层108时，会于通道层108内产生漏电流，使得薄膜晶体管阵列100发生不正常作动，导致显示器发生显示异常的问题。However, since the amorphous silicon material has photoelectric properties, if the thinfilm transistor array 100 is used in a reflective display, when ambient light is incident on thechannel layer 108 from above thethin film transistor 101, a leakage current will be generated in thechannel layer 108, This causes theTFT array 100 to operate abnormally, resulting in abnormal display of the display.

为解决上述问题，公知系在通道层108上方形成金属遮光层(图未示)，以避免环境光照射到通道层108而产生漏电流。但是以此种方式避免薄膜晶体管101产生漏电流，必须在反射式显示器的制造工艺中多加一道光罩，并因此增加反射式显示器的制造工艺成本。To solve the above problems, it is known to form a metal light-shielding layer (not shown) above thechannel layer 108 to prevent ambient light from irradiating thechannel layer 108 to generate leakage current. However, in order to avoid the leakage current of thethin film transistor 101 in this way, it is necessary to add an additional photomask in the manufacturing process of the reflective display, and thus increase the manufacturing process cost of the reflective display.

由此可见，上述现有的显示器及其薄膜晶体管阵列基板与薄膜晶体管在产品结构、制造方法(加工方法)与使用上，显然仍存在有不便与缺陷，而亟待加以进一步改进。为了解决上述存在的问题，相关厂商莫不费尽心思来谋求解决之道，但长久以来一直未见适用的设计被发展完成，而一般产品及方法又没有适切的结构及方法能够解决上述问题，此显然是相关业者急欲解决的问题。因此如何能创设一种新的显示器及其薄膜晶体管阵列基板与薄膜晶体管,实属当前重要研发课题之一，亦成为当前业界极需改进的目标。It can be seen that the above-mentioned existing displays and their thin film transistor array substrates and thin film transistors obviously still have inconveniences and defects in product structure, manufacturing method (processing method) and use, and need to be further improved urgently. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure and method for general products and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve. Therefore, how to create a new display and its thin film transistor array substrate and thin film transistor is one of the current important research and development topics, and it has also become a goal that the industry needs to improve.

发明内容Contents of the invention

本发明的目的在于，克服现有的薄膜晶体管存在的缺陷，而提供一种新的薄膜晶体管，所要解决的技术问题是使其源极与漏极之间的通道层(channel layer)不具光电特性，因而可避免在受光线照射时产生漏电流，非常适于实用。The purpose of the present invention is to overcome the defects of existing thin film transistors and provide a new thin film transistor. The technical problem to be solved is to make the channel layer between the source and drain without photoelectric properties. , so it can avoid leakage current when exposed to light, which is very suitable for practical use.

本发明的另一目的在于，克服现有的薄膜晶体管阵列基板存在的缺陷，而提供一种新的薄膜晶体管阵列基板，所要解决的技术问题是使其可以利用光罩少且成本低的制造工艺制作而成，并具有不因受光照射而产生漏电流的薄膜晶体管，从而更加适于实用。Another object of the present invention is to overcome the defects of existing thin film transistor array substrates and provide a new thin film transistor array substrate. Manufactured, and has a thin film transistor that does not generate leakage current due to light irradiation, so it is more suitable for practical use.

本发明的再一目的在于，克服现有的显示器存在的缺陷，而提供一种新的显示器，所要解决的技术问题是使其薄膜晶体管不会在受光照后产生漏电流，因而可改善其显示效能，从而更加适于实用。Another object of the present invention is to overcome the defects of existing displays and provide a new display. The technical problem to be solved is to make its thin film transistors not generate leakage current after being illuminated, so that the display can be improved. performance, which is more suitable for practical use.

本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种薄膜晶体管，其包括栅极、栅绝缘层、源极、漏极及氧化物半导体层。栅极与栅绝缘层分别配置于第一基板上，且栅绝缘层覆盖住栅极。源极与漏极分别配置于栅绝缘层上方。氧化物半导体层共形地配置于源极及漏极上并完全覆盖源极及漏极。氧化物半导体层具有一通道区，通道区位于源极与漏极之间。The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A thin film transistor proposed according to the present invention includes a gate, a gate insulating layer, a source, a drain and an oxide semiconductor layer. The gate and the gate insulating layer are respectively disposed on the first substrate, and the gate insulating layer covers the gate. The source and the drain are respectively arranged above the gate insulating layer. The oxide semiconductor layer is conformally disposed on the source and the drain and completely covers the source and the drain. The oxide semiconductor layer has a channel region, and the channel region is located between the source and the drain.

本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种薄膜晶体管阵列基板，包括第一基板、多条资料线、多条扫描线、多个上述的薄膜晶体管、保护层与多个像素电极。扫描线与资料线大致上垂直于彼此，而在第一基板上定义出多个像素区域。各薄膜晶体管配置在对应的像素区域内，并且与对应的资料线与扫描线电性连接。保护层覆盖在第一基板上，并且具有暴露出各薄膜晶体管的部分漏极的接触窗开口。这些像素电极分别配置在对应的像素区域内，并填入对应的接触窗开口而与对应的漏极电性连接。The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. A thin film transistor array substrate according to the present invention includes a first substrate, a plurality of data lines, a plurality of scanning lines, a plurality of the above thin film transistors, a protection layer and a plurality of pixel electrodes. The scan lines and the data lines are substantially perpendicular to each other, and define a plurality of pixel areas on the first substrate. Each thin film transistor is arranged in a corresponding pixel area, and is electrically connected with a corresponding data line and a scanning line. The protection layer covers the first substrate and has a contact window opening exposing part of the drain of each thin film transistor. The pixel electrodes are respectively arranged in the corresponding pixel regions, and fill the corresponding contact window openings to be electrically connected with the corresponding drain electrodes.

本发明的目的及解决其技术问题另外再采用以下技术方案来实现。依据本发明提出的一种显示器，包括上述的薄膜晶体管阵列基板、透光电极基板以及配置在透光电极基板与薄膜晶体管阵列基板之间的显示介质层。The purpose of the present invention and its technical problems are solved by adopting the following technical solutions in addition. A display according to the present invention includes the above-mentioned thin film transistor array substrate, a light-transmitting electrode substrate, and a display medium layer arranged between the light-transmitting electrode substrate and the thin film transistor array substrate.

本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

在本发明的一实施例中，上述的薄膜晶体管还包括第一欧姆接触层与第二欧姆接触层，其中第一欧姆接触层配置于源极与氧化物半导体层之间，第二欧姆接触层则是配置于漏极与氧化物半导体层之间。In an embodiment of the present invention, the above-mentioned thin film transistor further includes a first ohmic contact layer and a second ohmic contact layer, wherein the first ohmic contact layer is disposed between the source electrode and the oxide semiconductor layer, and the second ohmic contact layer It is disposed between the drain electrode and the oxide semiconductor layer.

借由上述技术方案，本发明显示器及其薄膜晶体管阵列基板与薄膜晶体管至少具有下列优点及有益效果：本发明是以氧化物半导体材料作为显示器的薄膜晶体管的通道层，而由于氧化物半导体不具光电特性，因此可避免薄膜晶体管在照光后产生漏电流的问题。此外，由于氧化物半导体层的材质为可透光材质，因此在本发明的显示器的制造工艺中，可省略氧化物半导体层的图案化制造工艺，以节省制造工艺成本并缩短制造工艺时间。By means of the above technical solution, the display and its thin film transistor array substrate and thin film transistor of the present invention have at least the following advantages and beneficial effects: the present invention uses oxide semiconductor material as the channel layer of the thin film transistor of the display, and since the oxide semiconductor has no photoelectric characteristics, so it can avoid the problem of leakage current of thin film transistors after being illuminated. In addition, since the material of the oxide semiconductor layer is a light-transmitting material, in the manufacturing process of the display of the present invention, the patterning manufacturing process of the oxide semiconductor layer can be omitted, so as to save the manufacturing process cost and shorten the manufacturing process time.

综上所述，本发明是有关于一种显示器及其薄膜晶体管阵列基板与薄膜晶体管。该显示器，包括薄膜晶体管阵列基板、透光电极基板及配置于两者之间的显示介质层。薄膜晶体管阵列基板包括多个具有氧化物半导体层的薄膜晶体管，其中薄膜晶体管的栅极与栅绝缘层分别配置于基板上，且栅绝缘层覆盖住栅极。氧化物半导体层共形地覆盖于栅绝缘层上，并具有位在栅极上方的通道区。薄膜晶体管的源极与漏极分别配置于氧化物半导体层上，并位于通道区的两侧。由于氧化物半导体层的材质为可透光材质，因此在此显示器的制造工艺中，可省略氧化物半导体层的图案化制造工艺，以节省制造工艺成本并缩短制造工艺时间。本发明在技术上有显著的进步，并具有明显的积极效果,诚为一新颖、进步、实用的新设计。To sum up, the present invention relates to a display and its thin film transistor array substrate and thin film transistor. The display includes a thin film transistor array substrate, a light-transmitting electrode substrate and a display medium layer arranged between them. The thin film transistor array substrate includes a plurality of thin film transistors with oxide semiconductor layers, wherein gates and gate insulation layers of the thin film transistors are respectively arranged on the substrate, and the gate insulation layer covers the gates. The oxide semiconductor layer conformally covers the gate insulation layer and has a channel region above the gate. The source and the drain of the thin film transistor are respectively arranged on the oxide semiconductor layer and located at two sides of the channel region. Since the material of the oxide semiconductor layer is a light-transmitting material, in the manufacturing process of the display, the patterning manufacturing process of the oxide semiconductor layer can be omitted, so as to save the manufacturing process cost and shorten the manufacturing process time. The present invention has significant progress in technology, and has obvious positive effects, and is a novel, progressive and practical new design.

上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图,详细说明如下。The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows.

附图说明Description of drawings

图1为公知有源显示器的单一像素中薄膜晶体管阵列基板的剖面示意图。FIG. 1 is a schematic cross-sectional view of a thin film transistor array substrate in a single pixel of a known active display.

图2为本发明的一实施例中显示器的剖面示意图。FIG. 2 is a schematic cross-sectional view of a display in an embodiment of the present invention.

图3为本发明的另一实施例中显示器的剖面示意图。FIG. 3 is a schematic cross-sectional view of a display in another embodiment of the present invention.

图4为本发明的一实施例中薄膜晶体管阵列基板的示意图。FIG. 4 is a schematic diagram of a thin film transistor array substrate in an embodiment of the present invention.

图5为图4的薄膜晶体管阵列基板在一实施例中的局部剖面示意图。FIG. 5 is a schematic partial cross-sectional view of the thin film transistor array substrate in FIG. 4 in an embodiment.

图6为图4的薄膜晶体管阵列基板在另一实施例中的局部剖面示意图。FIG. 6 is a schematic partial cross-sectional view of the thin film transistor array substrate in FIG. 4 in another embodiment.

图7为图4的薄膜晶体管阵列基板在另一实施例中的局部剖面示意图。FIG. 7 is a schematic partial cross-sectional view of the thin film transistor array substrate in FIG. 4 in another embodiment.

100、210：薄膜晶体管阵列基板100, 210: TFT array substrate

101、300：薄膜晶体管101, 300: thin film transistor

102：基板102: Substrate

104、310：栅极104, 310: grid

106、320：栅绝缘层106, 320: gate insulating layer

108：通道层108: Channel layer

110、340：源极110, 340: source

112、350：漏极112, 350: drain

114、214：保护层114, 214: protective layer

116、217：开口116, 217: opening

118、215：像素电极118, 215: Pixel electrodes

200、201：显示器200, 201: display

211：第一基板211: First Substrate

212：资料线212: data line

213：扫描线213: scan line

216：像素区域216: pixel area

220：显示介质层220: display medium layer

230：透光电极基板230: Translucent electrode substrate

232：第二基板232: Second substrate

234：透明电极234: transparent electrode

236：彩色滤光膜236: Color filter film

330：氧化物半导体层330: oxide semiconductor layer

332：通道区332: Passage area

370、380：欧姆接触层370, 380: ohmic contact layer

具体实施方式Detailed ways

为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例，对依据本发明提出的显示器及其薄膜晶体管阵列基板与薄膜晶体管的具体实施方式、结构、方法、步骤、特征及其功效，详细说明如后。In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation methods, Structure, method, step, feature and effect thereof are as follows in detail.

图2为本发明的一实施例中显示器的剖面示意图。请参照图2，显示器200包括薄膜晶体管阵列基板210、显示介质层220及透光电极基板230，其中透光电极基板230是位于薄膜晶体管阵列基板210上方，显示介质层220则是配置于透光电极基板230与薄膜晶体管阵列基板210之间。FIG. 2 is a schematic cross-sectional view of a display in an embodiment of the present invention. Please refer to FIG. 2, thedisplay 200 includes a thin filmtransistor array substrate 210, adisplay medium layer 220 and a light-transmittingelectrode substrate 230, wherein the light-transmittingelectrode substrate 230 is located above the thin-filmtransistor array substrate 210, and thedisplay medium layer 220 is arranged on the light-transmittingelectrode substrate 230. Between theelectrode substrate 230 and the thin filmtransistor array substrate 210 .

透光电极基板230包括第二基板232与透明电极234。透明电极234配置于第二基板232上，并位于第二基板232与显示介质层220之间。而且，第二基板232的材质可以是玻璃或塑胶。在本实施例中，第二基板232的材质例如是聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene Naphthalate，PEN)或聚甲基丙烯酸甲酯(Polymethacrylate，PMMA)。Thetransparent electrode substrate 230 includes asecond substrate 232 and atransparent electrode 234 . Thetransparent electrode 234 is disposed on thesecond substrate 232 and located between thesecond substrate 232 and thedisplay medium layer 220 . Moreover, the material of thesecond substrate 232 can be glass or plastic. In this embodiment, the material of thesecond substrate 232 is, for example, polyethylene terephthalate (Polyethylene Terephthalate, PET), polyethylene naphthalate (Polyethylene Naphthalate, PEN) or polymethyl methacrylate. (Polymethacrylate, PMMA).

另一方面，显示介质层220可以是微胶囊电泳层(microcapsuleelectrophoretic layer)、微杯电泳层(microcup electrophoretic layer)、胆固醇型液晶层(cholesteric liquid crystal layer)、电湿润层(electro-wetting layer)或粉体移动层(quick response-liquid powderlayer)。On the other hand, thedisplay medium layer 220 may be a microcapsule electrophoretic layer, a microcup electrophoretic layer, a cholesteric liquid crystal layer, an electro-wetting layer, or Powder moving layer (quick response-liquid powder layer).

特别的是，在另一实施例中，透光电极基板230还可以包括彩色滤光膜(color filter film)236，其是配置于透明电极234与第二基板232之间，如图3所示。也就是说，图3所绘示之显示器201为彩色显示器。Particularly, in another embodiment, thetransparent electrode substrate 230 may also include a color filter film (color filter film) 236, which is configured between thetransparent electrode 234 and thesecond substrate 232, as shown in FIG. 3 . That is to say, thedisplay 201 shown in FIG. 3 is a color display.

图4为本发明的一实施例中薄膜晶体管阵列基板的示意图。请参照图4，薄膜晶体管阵列基板210包括第一基板211、多条资料线212、多条扫描线213、多个薄膜晶体管300、保护层214与多个像素电极215。其中，第一基板211的材质可以是玻璃或塑胶。在本实施例中，第一基板211的材质例如是与第二基板232的材质相同，如聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二酯或聚甲基丙烯酸甲酯。换言之，图2所绘示的显示器200可以是可挠式显示器。FIG. 4 is a schematic diagram of a thin film transistor array substrate in an embodiment of the present invention. Referring to FIG. 4 , the thin filmtransistor array substrate 210 includes afirst substrate 211 , a plurality ofdata lines 212 , a plurality ofscan lines 213 , a plurality ofthin film transistors 300 , aprotective layer 214 and a plurality ofpixel electrodes 215 . Wherein, the material of thefirst substrate 211 may be glass or plastic. In this embodiment, the material of thefirst substrate 211 is, for example, the same as that of thesecond substrate 232 , such as polyethylene terephthalate, polyethylene naphthalate or polymethyl methacrylate. In other words, thedisplay 200 shown in FIG. 2 may be a flexible display.

这些资料线212是相互平行地配置于第一基板211上，扫描线213则是大致与资料线212垂直地配置在第一基板211上，而与资料线212在第一基板211上定义出多个像素区域216。这些薄膜晶体管300是分别配置在对应的像素区域216内，并与对应的扫描线213及资料线212电性连接。以下将详述本实施例的薄膜晶体管300的结构。Thesedata lines 212 are arranged parallel to each other on thefirst substrate 211, and thescanning lines 213 are arranged on thefirst substrate 211 approximately perpendicular to thedata lines 212, and define multiple lines on thefirst substrate 211 with the data lines 212.pixel area 216. Thesethin film transistors 300 are respectively arranged in correspondingpixel regions 216 and electrically connected withcorresponding scan lines 213 anddata lines 212 . The structure of thethin film transistor 300 of this embodiment will be described in detail below.

图5为图4的薄膜晶体管阵列基板的局部剖面示意图。请参照图5，薄膜晶体管300包括栅极310、栅绝缘层320、氧化物半导体层330、源极340及漏极350。其中，栅极310与栅绝缘层320分别配置于第一基板211上，且栅绝缘层320覆盖住栅极310。氧化物半导体层330共形地覆盖于栅绝缘层320上，且其具有位在栅极310上方的通道区332。源极340与漏极350分别配置于氧化物半导体330上，并位于通道区332的两侧。请同时参照图4及图5，源极340电性连接至其所对应的资料线212，漏极350则是与配置在像素区域216内的像素电极215(见图4)电性连接。FIG. 5 is a schematic partial cross-sectional view of the thin film transistor array substrate of FIG. 4 . Referring to FIG. 5 , thethin film transistor 300 includes agate 310 , agate insulating layer 320 , anoxide semiconductor layer 330 , asource 340 and adrain 350 . Wherein, thegate 310 and thegate insulating layer 320 are respectively disposed on thefirst substrate 211 , and thegate insulating layer 320 covers thegate 310 . Theoxide semiconductor layer 330 conformally covers thegate insulating layer 320 and has achannel region 332 above thegate 310 . Thesource 340 and thedrain 350 are respectively disposed on theoxide semiconductor 330 and located at two sides of thechannel region 332 . Please refer to FIG. 4 and FIG. 5 at the same time. Thesource electrode 340 is electrically connected to itscorresponding data line 212 , and thedrain electrode 350 is electrically connected to the pixel electrode 215 (see FIG. 4 ) disposed in thepixel region 216 .

栅极310的材质为金属材料或透明导电材料。以本实施例来说，栅极310的材质例如是钼或铬，且其厚度例如是2000埃(angstrom)。栅绝缘层320的材质例如是氧化硅，且其厚度例如是2000埃。氧化物半导体层330的材质例如是铟镓锌氧化物(IGZO)或铟锌氧化物(IZO)，且其厚度例如是900埃。源极340与漏极350的材质则可以与栅极310相同或不同，以本实施例来说，源极340与漏极350的材质可以是钼或铬，且其厚度例如是2000埃。Thegate 310 is made of metal material or transparent conductive material. In this embodiment, the material of thegate 310 is, for example, molybdenum or chromium, and its thickness is, for example, 2000 angstrom. The material of thegate insulating layer 320 is, for example, silicon oxide, and its thickness is, for example, 2000 angstroms. The material of theoxide semiconductor layer 330 is, for example, indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), and its thickness is, for example, 900 angstroms. The material of thesource electrode 340 and thedrain electrode 350 can be the same as or different from that of thegate electrode 310. In this embodiment, the material of thesource electrode 340 and thedrain electrode 350 can be molybdenum or chromium, and the thickness thereof is, for example, 2000 angstroms.

值得一提的是，为了降低源极340/漏极350与氧化物半导体层330之间的阻抗，在另一实施例中，薄膜晶体管300还可以包括欧姆接触层370与欧姆接触层380，其分别配置于源极340与氧化物半导体层330之间以及漏极350与氧化物半导体层330之间，如图6所示。特别的是，欧姆接触层370与欧姆接触层380的材质可以是导电性高于氧化物半导体层330的铟镓锌氧化物(IGZO)或铟锌氧化物(IZO)。详细来说，在薄膜晶体管300的制造工艺(即制程，以下均称为制造工艺)中，其例如是在单次镀膜制造工艺中，以不同通氧量来同时制成氧化物半导体层330、欧姆接触层370与欧姆接触层380。It is worth mentioning that, in order to reduce the resistance between thesource 340/drain 350 and theoxide semiconductor layer 330, in another embodiment, thethin film transistor 300 may further include anohmic contact layer 370 and anohmic contact layer 380, which They are respectively arranged between thesource electrode 340 and theoxide semiconductor layer 330 and between thedrain electrode 350 and theoxide semiconductor layer 330 , as shown in FIG. 6 . In particular, the material of theohmic contact layer 370 and theohmic contact layer 380 can be Indium Gallium Zinc Oxide (IGZO) or Indium Zinc Oxide (IZO) which has higher conductivity than theoxide semiconductor layer 330 . In detail, in the manufacturing process (that is, the manufacturing process, hereinafter referred to as the manufacturing process) of thethin film transistor 300, for example, in a single coating manufacturing process, theoxide semiconductor layer 330, theoxide semiconductor layer 330, theOhmic contact layer 370 andohmic contact layer 380 .

需要注意的是，本发明并不将氧化物半导体层330的位置限定在栅绝缘层320与源极340/漏极350之间，在另一实施例中，源极340与漏极350是配置于栅绝缘层320上，而氧化物半导体层330则是共形地覆盖于源极340与漏极350上，并使其通道区332位在源极340与漏极350之间，如图7所示。由于此实施例先在栅绝缘层320上形成源极340与漏极350，之后再在源极340与漏极350上形成氧化物半导体层330，因此可避免氧化物半导体层330在源极340与漏极350的图案化制造工艺中因蚀刻不当而受损的问题。It should be noted that the present invention does not limit the position of theoxide semiconductor layer 330 between thegate insulating layer 320 and thesource 340/drain 350, in another embodiment, thesource 340 and thedrain 350 are configured on thegate insulating layer 320, and theoxide semiconductor layer 330 conformally covers thesource electrode 340 and thedrain electrode 350, and makes thechannel region 332 between thesource electrode 340 and thedrain electrode 350, as shown in FIG. 7 shown. In this embodiment, thesource electrode 340 and thedrain electrode 350 are formed on thegate insulating layer 320 first, and then theoxide semiconductor layer 330 is formed on thesource electrode 340 and thedrain electrode 350, so that theoxide semiconductor layer 330 can be avoided. The problem of damage due to improper etching in the patterning process of thedrain electrode 350 .

而且，在图7所示的实施例中，薄膜晶体管300同样也可以包括前述实施例所述的欧姆接触层370与欧姆接触层380。Moreover, in the embodiment shown in FIG. 7 , thethin film transistor 300 may also include theohmic contact layer 370 and theohmic contact layer 380 described in the foregoing embodiments.

在前述这些实施例中，由于氧化物半导体层330不具光电特性，因此即使环境光从薄膜晶体管300上方入射至氧化物半导体层330，薄膜晶体管300也不会发生漏电流的问题。特别的是，由于构成氧化物半导体层330的材质可透光，因此在本发明的薄膜晶体管阵列基板210的制造工艺中，不需要移除部分的氧化物半导体层330也不会对其所对应的像素区域内的开口率(aperture ratio)造成影响。换言之，本发明的薄膜晶体管阵列基板210的制造工艺与公知的薄膜晶体管阵列基板100的制造工艺相较之下，不但制造工艺简单且生产成本低。In the above-mentioned embodiments, since theoxide semiconductor layer 330 has no photoelectric properties, even if ambient light is incident on theoxide semiconductor layer 330 from above thethin film transistor 300 , thethin film transistor 300 will not have leakage current. In particular, since the material constituting theoxide semiconductor layer 330 can transmit light, in the manufacturing process of the thin filmtransistor array substrate 210 of the present invention, part of theoxide semiconductor layer 330 does not need to be removed and will not correspond to it. The aperture ratio (aperture ratio) in the pixel area affects. In other words, compared with the manufacturing process of the known thin filmtransistor array substrate 100 , the manufacturing process of the thin filmtransistor array substrate 210 of the present invention is not only simple in manufacturing process but also low in production cost.

请再次参照图5，薄膜晶体管阵列基板210中的保护层214是配置于第一基板211上，并具有多个开口217(图中仅绘出一个)。这些开口217是分别对应至各像素区域216，以暴露出其所对应的像素区域216内的薄膜晶体管300的漏极350的一部分。值得一提的是，本实施例的保护层214的材质例如是树脂，而其例如是以自旋涂布(spin coating)的方式形成在第一基板211上，因而具有较佳的平坦化效果。另外，保护层214的厚度约为2.5微米。Referring to FIG. 5 again, theprotective layer 214 in the thin filmtransistor array substrate 210 is disposed on thefirst substrate 211 and has a plurality of openings 217 (only one is shown in the figure). Theseopenings 217 are respectively corresponding to eachpixel region 216 to expose a part of thedrain 350 of thethin film transistor 300 in thecorresponding pixel region 216 . It is worth mentioning that the material of theprotective layer 214 in this embodiment is, for example, resin, and it is formed on thefirst substrate 211 by, for example, spin coating, so it has a better planarization effect . In addition, the thickness of theprotective layer 214 is about 2.5 microns.

像素电极215是分别配置在其所对应的像素区域216内，并填入保护层214的开口217内而与漏极350电性连接。在本实施例中，像素电极215的材质例如是铟锌氧化物(ITO)、铟锡氧化物(IZO)或其他的金属导电材料，而其厚度例如是500埃。Thepixel electrodes 215 are respectively disposed in the correspondingpixel regions 216 , and fill in theopenings 217 of theprotective layer 214 to be electrically connected to thedrain 350 . In this embodiment, the material of thepixel electrode 215 is, for example, indium zinc oxide (ITO), indium tin oxide (IZO) or other conductive metal materials, and its thickness is, for example, 500 angstroms.

综上所述，本发明具有下列优点：In summary, the present invention has the following advantages:

1.本发明是以氧化物半导体材料作为显示器的薄膜晶体管的通道层，而由于氧化物半导体不具光电特性，因此可避免薄膜晶体管在照光后产生漏电流的问题。1. The present invention uses oxide semiconductor material as the channel layer of the thin film transistor of the display, and since the oxide semiconductor does not have photoelectric properties, the problem of leakage current generated by the thin film transistor after being illuminated can be avoided.

2.由于氧化物半导体层可在室温下成膜，因而能够直接在耐热度不佳的塑胶基板上完成制造工艺。换言之，在具可挠性的显示器的制造工艺中，以具有氧化物半导体层的薄膜晶体管作为驱动元件可简化制造工艺并降低成本。2. Since the oxide semiconductor layer can be formed at room temperature, the manufacturing process can be completed directly on the plastic substrate with poor heat resistance. In other words, in the manufacturing process of the flexible display, using the thin film transistor with the oxide semiconductor layer as the driving element can simplify the manufacturing process and reduce the cost.

3.由于氧化物半导体层的材质为可透光材质，因此在本发明的显示器的制造工艺中，可省略氧化物半导体层的图案化制造工艺，以节省制造工艺成本并缩短制造工艺时间。3. Since the material of the oxide semiconductor layer is a light-transmitting material, in the manufacturing process of the display of the present invention, the patterning manufacturing process of the oxide semiconductor layer can be omitted, so as to save the manufacturing process cost and shorten the manufacturing process time.

4.本发明可利用树脂来作为薄膜晶体管阵列基板上的保护层，因而可获得良好的平坦化效果。4. In the present invention, the resin can be used as the protective layer on the thin film transistor array substrate, so a good planarization effect can be obtained.

以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the method and technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but if they do not depart from the content of the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims (6)

1. a thin-film transistor, is characterized in that comprising:

One grid, is disposed on a first substrate;

One gate insulation layer, is disposed on this first substrate and covers this grid;

One source pole, is disposed at this gate insulation layer top;

One drain electrode, is disposed at this gate insulation layer top; And

Monoxide semiconductor layer, is conformally disposed at this source electrode and this drain electrode upper, and this oxide semiconductor layer has a ，Gai channel region, channel region between this source electrode and this drain electrode;

Wherein, this source electrode and this drain electrode all have end face towards this oxide semiconductor layer, towards the bottom surface of this gate insulation layer and be connected in this end face and this bottom surface and away from the side of this channel region, and this oxide semiconductor layer more covers the described side of this source electrode and this drain electrode.

2. thin-film transistor as claimed in claim 1, characterized by further comprising:

One first ohmic contact layer, is disposed between this source electrode and this oxide semiconductor layer; And

One second ohmic contact layer, is disposed between this drain electrode and this oxide semiconductor layer.

3. a thin-film transistor array base-plate, is characterized in that comprising:

One first substrate;

Many data lines, are disposed on this first substrate in parallel with each other;

Multi-strip scanning line, is disposed on this first substrate, and those scan lines are parallel to each other and vertical those data lines, and on this first substrate, defines a plurality of pixel regions;

A plurality of thin-film transistors, be disposed at respectively those corresponding pixel regions in one of them, and one of them is electrically connected with corresponding those data lines one of them and corresponding those scan lines, respectively this thin-film transistor comprises a grid, a gate insulation layer, monoxide semiconductor layer, one source pole and a drain electrode; This gate configuration is on this first substrate; This gate insulation layer is disposed on this first substrate and covers this grid; It is upper that this oxide semiconductor layer is conformally disposed at this source electrode and this drain electrode, and this oxide semiconductor layer has a channel region, is positioned at this grid top; This source electrode is disposed at this gate insulation layer top, and is positioned at a side of this channel region; This drain configuration is in this gate insulation layer top, and is positioned at the opposite side of this channel region; This source electrode and this drain electrode all have end face towards this oxide semiconductor layer, towards the bottom surface of this gate insulation layer and be connected in this end face and this bottom surface and away from the side of this channel region, and this oxide semiconductor layer more covers the described side of this source electrode and this drain electrode;

One protective layer, is covered on this first substrate, and this protective layer has a plurality of contact windows of the part that exposes respectively those drain electrodes; And

A plurality of pixel electrodes, are disposed at respectively those corresponding pixel regions in one of them, and respectively this pixel electrode insert in this corresponding contact window and with corresponding this drain electrode electric connection.

4. thin-film transistor array base-plate as claimed in claim 3, is characterized in that wherein respectively this thin-film transistor also comprises:

One first ohmic contact layer, is disposed between this source electrode and this oxide semiconductor layer; And

One second ohmic contact layer, is disposed between this drain electrode and this oxide semiconductor layer.

5. a display, is characterized in that comprising:

One thin-film transistor array base-plate, it comprises a first substrate, many data lines, multi-strip scanning line, a plurality of thin-film transistor, a protective layer and a plurality of pixel electrodes; Those data lines are disposed on this first substrate in parallel with each other; Those scan lines are disposed on this first substrate, and those scan lines are parallel to each other and vertical those data lines, and on this first substrate, define a plurality of pixel regions, those thin-film transistors are disposed at respectively those corresponding pixel regions in one of them, and with corresponding those data lines one of them and corresponding one of them electric connection of those scan lines; Respectively this thin-film transistor comprises a grid, a gate insulation layer, monoxide semiconductor layer, one source pole and a drain electrode; This gate configuration is on this first substrate; This gate insulation layer is disposed on this first substrate and covers this grid; It is upper that this oxide semiconductor layer is conformally disposed at this source electrode and this drain electrode, and this oxide semiconductor layer has a channel region, is positioned at this grid top; This source electrode is disposed at this gate insulation layer top, and is positioned at a side of this channel region; This drain configuration is in this gate insulation layer top, and is positioned at the opposite side of this channel region; This protective layer is covered on this first substrate, and this protective layer has a plurality of contact windows of the part that exposes respectively those drain electrodes; Those pixel electrodes are disposed at respectively those corresponding pixel regions in one of them, and respectively this pixel electrode is inserted in this corresponding contact window, and are electrically connected with this corresponding drain electrode; This source electrode and this drain electrode all have end face towards this oxide semiconductor layer, towards the bottom surface of this gate insulation layer and be connected in this end face and this bottom surface and away from the side of this channel region, and this oxide semiconductor layer more covers the described side of this source electrode and this drain electrode;

One euphotic electrode substrate, comprises a second substrate and a transparency electrode, and this second substrate is disposed at this thin-film transistor array base-plate top, and this transparency electrode is disposed on this second substrate, and between this thin-film transistor array base-plate and this second substrate; And

One display dielectric layer, is disposed between this thin-film transistor array base-plate and this euphotic electrode substrate.

6. display as claimed in claim 5, is characterized in that wherein respectively this thin-film transistor also comprises:

One first ohmic contact layer, is disposed between this source electrode and this oxide semiconductor layer; And

One second ohmic contact layer, is disposed between this drain electrode and this oxide semiconductor layer.

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