CN101995718B - Display panel and method for reducing data lines used by same - Google Patents
Display panel and method for reducing data lines used by sameDownload PDFInfo
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- CN101995718B CN101995718BCN 200910189769CN200910189769ACN101995718BCN 101995718 BCN101995718 BCN 101995718BCN 200910189769CN200910189769CN 200910189769CN 200910189769 ACN200910189769 ACN 200910189769ACN 101995718 BCN101995718 BCN 101995718B
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Abstract
Translated fromChineseDescription
Technical field
The invention belongs to the display panel field, relate in particular to a kind of display panel, with the method that reduces the employed data line of display panel.
Background technology
See also Fig. 1, it is the simple synoptic diagram of general LCD module 100.LCD module 100 comprises adisplay panel 110, onescan driver element 120, a data-drivenunit 130, time schedule controller (Timing Controller) 140, one reference voltage source 150, abacklight driving unit 160, an andmodule 170 backlight.Time schedule controller 140 exports data to data-drivenunit 130, and exports control signal to scandrive cell 120, with the driving of transistor and pixel electrode on the control display panel 110.Scan drive cell 120 and data-drivenunit 130 required power supplys are provided by 150 of reference voltagesources.Display panel 110 required light sources are also provided bybacklight driving unit 160controls module 170 backlight.In Fig. 1, data-drivenunit 130 included a plurality of data lines are represented with Sn, andscan drive cell 120 included a plurality of sweep traces are represented with Gn.When a certain transistor on thedisplay panel 110 and and the pixel electrode of electric connection will be activated the time; These a plurality of sweep trace Gn go up one of them and correspond to this transistorized sweep trace and can be triggered byscan drive cell 120; And these a plurality of data line Sn go up one of them correspond to this transistorized data line can receive by data-drivenunit 130 by the data of correspondence converted voltage, with voltage with these pixel electrode charge or discharge to corresponding GTG.
Please consult Fig. 2 again, it isdisplay panel 110 shown in Figure 1,scan drive cell 120, and the simple synoptic diagram of data-driven unit 130.As shown in Figure 2,display panel 110 shows the sub-pixel of three kinds of different colours, comprises red sub-pixel R, green sub-pixels G, blue subpixels B; And displayable sub-pixel adds up to 480*3*272 on thehypothesis display panel 110; Wherein 480*3 represents that 480 pixels of same row multiply by three kinds of included different colours sub-pixels of each pixel on thedisplay panel 110, and the quantity of representativedata driver element 130 employed a plurality of data line Sn and corresponding drive integrated circult unit is 1440; 272 represent the pixel of included 272 row on thedisplay panel 110, and represent the quantity of drive integrated circult unit of quantity and the correspondence ofscan drive cell 120 employed a plurality of sweep trace Gn be 272.Can know by above hypothesis; Concerningsingle display panel 110; 1440 drive integrated circult unit need be set in data-drivenunit scan drive cell 120, can letdisplay panel 110 carry out the work of display pixel smoothly; Yet under light-weighted processing procedure direction, the quantity of above-mentioned drive integrated circult unit also need be reduced at display panel.Note that in general display panel the quantity of data line is far beyond next many of sweep trace, and above-mentioned hypothesis for data line and sweep trace quantity also is based on this characteristic and discusses.
Summary of the invention
The object of the present invention is to provide a kind of display panel, be intended to solve the many problems of quantity of the data line of the display panel that prior art provides.
The present invention is achieved in that a kind of display panel, and said display panel comprises:
A plurality of rowed transistor groups, one first scanline groups, one second scanline groups, and a plurality of data lines.
Said a plurality of rowed transistor group is arranged as a transistor matrix.Each rowed transistor group of said a plurality of rowed transistor groups is arranged on the said transistor matrix with row (Row) mode.Each rowed transistor group of said a plurality of rowed transistor groups comprises:
A plurality of strange sub-pixel transistor modules (Odd Sub-pixel Transistor Module); And
A plurality of even sub-pixel transistor modules (Even Sub-pixel Transistor Module).
Said a plurality of even sub-pixel transistor module and said a plurality of strange sub-pixel transistor module are staggered, and said a plurality of even sub-pixel transistor module corresponds respectively to said a plurality of strange sub-pixel transistor module.
Said first scanline groups comprises a plurality of first sweep traces.
Each first sweep trace of said a plurality of first sweep traces corresponds respectively to said a plurality of rowed transistor group, and each first sweep trace of said a plurality of first sweep traces is electrically connected at one of them included a plurality of strange sub-pixel transistor module of said a plurality of rowed transistor groups.
Said second scanline groups comprises a plurality of second sweep traces.
Each second sweep trace of said a plurality of second sweep traces corresponds respectively to said a plurality of rowed transistor group, and each second sweep trace of said a plurality of second sweep traces is electrically connected at one of them included a plurality of even sub-pixel transistor module of said a plurality of rowed transistor groups.
Each data line of said a plurality of data lines is arranged with row (Column) mode in said transistor matrix, and each data line of said a plurality of data lines is electrically connected at a strange sub-pixel transistor module and an even sub-pixel transistor module in each rowed transistor groups of said a plurality of rowed transistor groups.
Adjacent one another are in said rowed transistor group and form a transistor unit by said strange sub-pixel transistor module that each data line of said a plurality of data lines electrically connected and said even sub-pixel transistor module in same rowed transistor group;
In each rowed transistor group of said a plurality of rowed transistor groups, the strange sub-pixel transistor module of each of said a plurality of strange sub-pixel transistor modules comprises:
One strange sub-pixel transistor; And
One first pixel electrode is electrically connected at said strange sub-pixel transistor;
Wherein in each rowed transistor group of said a plurality of rowed transistor groups, the even sub-pixel transistor module of each of said a plurality of even sub-pixel transistor modules comprises:
One even sub-pixel transistor; And
One second pixel electrode is electrically connected at said even sub-pixel transistor;
Wherein a data-driven unit is electrically connected at said a plurality of data line, and the one scan driver element is electrically connected at said first scanline groups and said second scanline groups;
Said scan drive cell is opened said first scanline groups and said second scanline groups in turn according to an odd even control signal, with the said a plurality of strange sub-pixel transistor module in each rowed transistor group of the said a plurality of rowed transistor groups of mutual driving and said a plurality of even sub-pixel transistor module;
Said data-driven unit determines the GTG that said a plurality of strange sub-pixel transistor module and said a plurality of even sub-pixel transistor module are exported according to a data-signal, and implements reversal of poles according to a polarity control signal.
Another object of the present invention is to provide a kind of method that reduces the employed data line of display panel, said method comprises the steps:
On a display panel; Electrically connect with same data line respectively with a plurality of strange sub-pixel transistor module in each rowed transistor group of a plurality of rowed transistor groups and with the adjacent respectively a plurality of even sub-pixel transistor module of said a plurality of strange sub-pixel transistor modules, and form a plurality of transistor units;
Each transistor unit included to each rowed transistor group of said a plurality of rowed transistor groups is electrically connected at the included strange sub-pixel transistor module of each transistor unit of said a plurality of transistor units with one first sweep trace;
Each transistor unit included to each rowed transistor group of said a plurality of rowed transistor groups is electrically connected at the included even sub-pixel transistor module of each transistor unit of said a plurality of transistor units with one second sweep trace;
In the opening time to each rowed transistor group of said a plurality of rowed transistor groups, open said first sweep trace and said second sweep trace in turn;
And according to opening said first sweep trace or said second sweep trace; And according to a polarity control signal; Online data being electrically connected at said strange sub-pixel transistor module and said even sub-pixel transistor module provides a voltage, said voltage is write said strange sub-pixel transistor module or said even sub-pixel transistor module;
Said strange sub-pixel transistor module comprises:
One strange sub-pixel transistor; And
One first pixel electrode is electrically connected at said strange sub-pixel transistor;
Wherein said even sub-pixel transistor module comprises:
One even sub-pixel transistor; And
One second pixel electrode is electrically connected at said even sub-pixel transistor;
In the said opening time to each rowed transistor group of said a plurality of rowed transistor groups, open said first sweep trace in turn and said second sweep trace comprises:
Open said strange sub-pixel transistor and said even sub-pixel transistor in turn;
According to opening said first sweep trace or said second sweep trace; And according to said polarity control signal; Said online data being electrically connected at said strange sub-pixel transistor module and said even sub-pixel transistor module provides a voltage, said voltage is write said strange sub-pixel transistor module or said even sub-pixel transistor module comprises:
Said voltage is write said first pixel electrode or said second pixel electrode;
In the said opening time to each rowed transistor group of said a plurality of rowed transistor groups, the step of opening said first sweep trace and said second sweep trace in turn specifically comprises:
The one scan control module is opened said first sweep trace and said second sweep trace in turn;
According to opening said first sweep trace or said second sweep trace; And according to said polarity control signal; Said online data being electrically connected at said strange sub-pixel transistor module and said even sub-pixel transistor module provides said voltage, said voltage is write said strange sub-pixel transistor module or said even sub-pixel transistor module comprises:
One DCU data control unit is according to opening said first sweep trace or said second sweep trace, and according to said polarity control signal, said voltage is provided.
Another object of the present invention is to provide a kind of LCD module that on display panel, reduces data line, said LCD module comprises:
One display panel, one scan driver element, an and data-driven unit.
Said display panel comprises:
A plurality of rowed transistor groups, one first scanline groups, one second scanline groups, and a plurality of data lines.
Said a plurality of rowed transistor group is arranged as a transistor matrix.
Each rowed transistor group of said a plurality of rowed transistor groups is arranged on the said transistor matrix with the row mode.
Each rowed transistor group of said a plurality of rowed transistor groups comprises:
A plurality of strange sub-pixel transistor modules and a plurality of even sub-pixel transistor module
Said a plurality of even sub-pixel transistor module and said a plurality of strange sub-pixel transistor module are staggered, and said a plurality of even sub-pixel transistor module corresponds respectively to said a plurality of strange sub-pixel transistor module.
Said first scanline groups comprises a plurality of first sweep traces.
Each first sweep trace of said a plurality of first sweep traces corresponds respectively to said a plurality of rowed transistor group, and each first sweep trace of said a plurality of first sweep traces is electrically connected at one of them included a plurality of strange sub-pixel transistor module of said a plurality of rowed transistor groups.
Said second scanline groups comprises a plurality of second sweep traces.
Each second sweep trace of said a plurality of second sweep traces corresponds respectively to said a plurality of rowed transistor group, and each second sweep trace of said a plurality of second sweep traces is electrically connected at one of them included a plurality of even sub-pixel transistor module of said a plurality of rowed transistor groups.
Each data line of said a plurality of data lines is arranged with line mode in said transistor matrix, and each data line of said a plurality of data lines is electrically connected at a strange sub-pixel transistor module and an even sub-pixel transistor module in each rowed transistor groups of said a plurality of rowed transistor groups.
Adjacent one another are in said rowed transistor group and form a transistor unit by a strange sub-pixel transistor module that each data line of said a plurality of data lines electrically connected and an even sub-pixel transistor module in same rowed transistor group.
Said scan drive cell is electrically connected at said first scanline groups and said second scanline groups.
Said scan drive cell is used for opening in turn said first scanline groups and said second scanline groups, with the output and the reversal of poles of the said a plurality of strange sub-pixel transistor module in each rowed transistor group of the said a plurality of rowed transistor groups of mutual driving and said a plurality of even sub-pixel transistor modules.
Said data-driven unit is electrically connected at said a plurality of data line.
Said data-driven unit is according to opening said first sweep trace or said second sweep trace; And according to a polarity control signal; One voltage is provided, said voltage write said strange sub-pixel transistor module or said even sub-pixel transistor module and to implement reversal of poles;
Said LCD module also comprises:
Time schedule controller provides a data-signal, said polarity control signal, an enabling signal week, reaches an odd even control signal to said data-driven unit, and controls the sweep trace that said scan drive cell is opened according to said odd even control signal;
In each transistor unit of said a plurality of transistor units; Said data letter signal is used for controlling the GTG that said strange sub-pixel transistor module or said even sub-pixel transistor module are shown, said enabling signal is used for starting the program that each transistor units of said a plurality of transistor units is opened by corresponding scanning line;
Said scan drive cell is opened said first scanline groups and said second scanline groups in turn according to said odd even control signal, with the said a plurality of strange sub-pixel transistor module in each rowed transistor group of the said a plurality of rowed transistor groups of mutual driving and said a plurality of even sub-pixel transistor module;
In each rowed transistor group of said a plurality of rowed transistor groups, the strange sub-pixel transistor module of each of said a plurality of strange sub-pixel transistor modules comprises:
One strange sub-pixel transistor; And
One first pixel electrode is electrically connected at said strange sub-pixel transistor;
Wherein in each rowed transistor group of said a plurality of rowed transistor groups, the even sub-pixel transistor module of each of said a plurality of even sub-pixel transistor modules comprises:
One even sub-pixel transistor; And
One second pixel electrode is electrically connected at said even sub-pixel transistor.
In the present invention, sub-pixel transistor module adjacent in twos in each rowed transistor group is electrically connected to same data line, makes the employed data line quantity of display panel reduce by half.
Description of drawings
Fig. 1 is the simple synoptic diagram of general LCD module;
Fig. 2 is display panel shown in Figure 1, scan drive cell, and the simple synoptic diagram of data-driven unit;
Fig. 3 is the simple synoptic diagram according to the LCD module that one embodiment of the invention disclosed;
Fig. 4 is according to one embodiment of the invention, the synoptic diagram of the display panel shown in Figure 3 210 that discloses;
Fig. 5 by according to one embodiment of the invention the synoptic diagram of the included transistor unit of display panel among exposure Fig. 4;
Fig. 6 is that the data on Fig. 3 and the display panel shown in Figure 4 shift synoptic diagram;
Fig. 7 is the waveform operation figure on Fig. 3 and the display panel shown in Figure 4;
Fig. 8 is the reversal of poles synoptic diagram according to resultant two pictures of playing continuously of the waveform operation figure of Fig. 7;
Fig. 9, Figure 10, Figure 11 are according to other embodiments of the invention, the synoptic diagram that included being used for of display panel of the present invention prevents the transistor unit of perpendicular line phenomenon that illustrates;
Figure 12 is the process flow diagram that on display panel, reduces the method for data line according to one embodiment of the invention disclosed.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In the middle of instructions and follow-up claim, used some vocabulary to censure specific assembly.Having common knowledge the knowledgeable in the affiliated field should understand, and same assembly may be called with different nouns by manufacturer.This instructions and follow-up claim are not used as distinguishing the mode of assembly with the difference of title, but the benchmark that is used as distinguishing with the difference of assembly on function.Be an open term mentioned " comprising " in the middle of instructions and the follow-up claim in the whole text, so should be construed to " comprise but be not limited to ".In addition, " electric connection " speech comprises any indirect means that are electrically connected that directly reach at this.Therefore, be electrically connected at one second device, then represent this first device can be directly connected in this second device, or be connected to this second device through other device or the intersegmental ground connection of connection hand if describe one first device in the literary composition.
In embodiments of the present invention, in order to improve the display panel processing procedure, and avoid the perpendicular line phenomenon that display panel takes place in the prior art, the present invention to disclose a kind of display panel that reduces data line, comprise LCD module, and the correlation technique of this display panel.In the display panel that the present invention disclosed; Mainly adopt same data line to be electrically connected to a strange sub-pixel transistor module and an even sub-pixel transistor module simultaneously, cooperate sweep trace to control the way that the odd even sub-pixel shows and controls reversal of poles simultaneously, reach the purpose of the quantity of the drive integrated circult unit that reduces data line and correspondence.In addition; The present invention is the design to being used against each other and disperse by a pair of strange sub-pixel transistor module that same data line electrically connected and the included separately transistorized configuration of strange/even sub-pixel of even sub-pixel transistor module also; Make the transistorized light transmission capacity of sub-pixel to be evenly dispersed and reduce the perpendicular line phenomenon, and make the observer of display panel be difficult for finding perpendicular line.
See also Fig. 3, it is the simple synoptic diagram according to the LCD module 200 that one embodiment of the invention disclosed.As shown in Figure 3, LCD module 200 comprises a display panel 210, one scan driver element 220, a data-driven unit 230, and time schedule controller 240.The included sub-pixel transistor number of display panel 210 and Fig. 1, display panel shown in Figure 2 110 is identical; But and the data line between the data-driven unit 230 only have the S1 of comprising, S2, S3 ..., S718, S719, S720 720, that is only comprise data line Sn shown in Figure 2 half quantity data line of totally 1440; And the sweep trace between display panel 210 and the scan drive cell 220 comprise G1, G2, G3 ..., totally 544 of G543, G544, that is comprise sweep trace Gn shown in Figure 2 totally 272 the sweep trace of diploidy number amount.Though compared to display panel shown in Figure 2 110; Display panel 210 has increased by one times sweep trace; But because number far beyond sweep trace be many data line decreased number half the, therefore generally speaking, display panel 210 employed lines remain minimizing; In other words, the number of the drive integrated circult unit of display panel 210 required uses also can reduce.Time schedule controller 240 provides a polarity control signal POL, an enabling signal STH, an odd even control signal OEH, reaches a data-signal DATA to data-driven unit 230; The sweep trace that time schedule controller 240 also comes gated sweep driver element 220 to be opened according to odd even control signal OEH, the function of above-mentioned these signals can after explanation separately.
See also Fig. 4, it is according to one embodiment of the invention, the synoptic diagram of the display panel shown in Figure 3 210 that discloses.As shown in Figure 4; Display panel 210 comprised a plurality of rowed transistor group R1, R2 ..., R271, R272; And a plurality of rowed transistor group R1, R2 ..., R271, R272 arrange with the mode of transistor matrix, and each rowed transistor group is arranged in formed this transistor matrix on the display panel 210 with the row mode.A plurality of rowed transistor group R1, R2 ..., each rowed transistor group of R271, R272 comprises a plurality of strange sub-pixel transistor modules (Odd Sub-pixel Transistor Module) OB and a plurality of even sub-pixel transistor module (Even Sub-pixel Transistor Module) EB.Observing Fig. 4 can know, in each rowed transistor group, a plurality of strange sub-pixel transistor module OB are staggered with a plurality of even sub-pixel transistor module EB and are corresponding respectively.In single rowed transistor group, a pair ofly be electrically connected at same data line and adjacent strange sub-pixel transistor module and even sub-pixel transistor module can be regarded as a transistor unit; For instance, in rowed transistor group R1, transistor unit 121 included a pair of strange sub-pixel transistor module OB and even sub-pixel transistor module EB all are electrically connected at data line S1 and adjacent one another are; In like manner, included a pair of strange sub-pixel transistor module OB of transistor unit 122,123,12718,12719,12720,341,342,343,34718,34719,34720,5415421,5415422,5415423,541542718,541542719,541542720,5435441,5435442,5435443,543544718,543544719,543544720 and even sub-pixel transistor module EB all are electrically connected at same data line and are adjacent one another are.Please note; Though in each transistor unit shown in Figure 4, strange sub-pixel transistor module OB is positioned at the left side, and even sub-pixel transistor module EB is positioned at the right side; Right transistor unit is merely a kind of and is used for explaining that same data line is electrically connected at two adjacent strange sub-pixel transistor modules and even sub-pixel transistor module and the notion stated; And in other embodiments of the invention, strange sub-pixel transistor module OB can be positioned at the right side of transistor unit, and even sub-pixel transistor module EB can be positioned at the left side of transistor unit; Difference only is the online exchange down of two corresponding scannings, and does not receive the illustrated restriction of Fig. 4.
Sweep trace G1, G3, G5 ..., G541, G543 is corresponding respectively and be electrically connected at the included a plurality of strange sub-pixel transistor module of each rowed transistor group on thedisplay panel 210, to start the corresponding included said a plurality of strange sub-pixel transistor module of rowed transistor group respectively; Sweep trace G1, G3, G5 ..., G541, the formed set of G543 can be regarded as one first scanline groups.In like manner, sweep trace G2, G4 ..., G540, G542, G544 is corresponding respectively and be electrically connected at the included a plurality of even sub-pixel transistor module of each rowed transistor group on thedisplay panel 210 to start respectively; Sweep trace G2, G4 ..., G540, G542, the formed set of G544 can be regarded as one second scanline groups.
A plurality of data line S1, S2, S3 ..., each data line of S718, S719, S720 arranges with row (Column) mode ondisplay panel 210 formed these transistor matrixs.A plurality of data line S1, S2, S3 ..., each data line of S718, S719, S720 be electrically connected at a plurality of rowed transistor group R1, R2 ..., a strange sub-pixel transistor module and an even sub-pixel transistor module in each rowed transistor group of R271, R272.
See also Fig. 5, its by according to one embodiment of the invention the synoptic diagram of the included transistor unit of display panel 210 among exposure Fig. 4.Note that in Fig. 5 with transistor unit 342 shown in Figure 4 to be illustration, right Fig. 5 in fact also equivalence illustrates other transistor unit shown in Figure 4 included assembly and arrangement.As shown in Figure 5, transistor unit 342 comprises a strange sub-pixel transistor group OB and an even sub-pixel transistor module EB.Strange sub-pixel transistor module OB comprises a strange sub-pixel transistor OT and a pixel electrode (Pixel Electrode) OPE, and wherein pixel electrode OPE is electrically connected at strange sub-pixel transistor OT; Idol sub-pixel transistor module EB comprises an even sub-pixel transistor ET and a pixel electrode EPE, and wherein pixel electrode EPE is electrically connected at even sub-pixel transistor ET.Sweep trace G3 is electrically connected at strange sub-pixel transistor module OB and included strange sub-pixel transistor OT thereof, to control the on off state of strange sub-pixel transistor OT; In like manner, sweep trace G4 is electrically connected at even sub-pixel transistor module EB and included even sub-pixel transistor ET thereof, to control the on off state of even sub-pixel transistor ET.Scan drive cell 220 only needs the opening time of gated sweep line G3 and G4; Just can in a set time, open strange sub-pixel transistor OT and even sub-pixel transistor ET easily in turn, and make the voltage on the data line S2 can be pixel electrode OPE or EPE charge or discharge in the opening time of sweep trace G3 and G4.
See also Fig. 6 and Fig. 7.Fig. 6 is that the data on Fig. 3 and the display panel 210 shown in Figure 4 shift synoptic diagram, and Fig. 7 is the waveform operation figure on Fig. 3 and the display panel 210 shown in Figure 4.Fig. 6 and Fig. 7 are used for explaining the transistor controls mode on the display panel 210.In the data-driven unit 230 in sometime hypothesis include 1440 buffered datas, and in Fig. 6 with B1, B2 ..., the mode of B1440 representes that these buffered datas are to produce via the data-signal DATA that time schedule controller 240 is provided.Then buffered data B1, B2 ..., B1440 can be read in regular turn according to the selection of odd even control signal OEH data line S1, S2, S3 ..., among the S719, S720, with as a plurality of digital revolving die analog signal DAC_output.Please note; Though odd even control signal OEH shown in Figure 6 shows its selecteed buffered data in different time with the mode of multiplexer; Yet odd even control signal OEH need not implement with multiplexer in fact, that is multiplexer shown in Figure 6 is merely and explains orally purposes and illustrate.Synchronizing signal SYNC shown in Figure 7 is 240 uses of time schedule controller.Enabling signal STH is used for starting the program that each transistor unit is opened by sweep trace, and the time span that is unlocked corresponding to the one-transistor unit between two noble potential pulses (Pulse) of enabling signal STH.Odd even control signal OEH be used for the one-transistor unit be unlocked during, determine a pair of strange sub-pixel transistor module that this transistor unit is included and even sub-pixel transistor module by the order that drives in turn with time span.Numeral revolving die analog signal DAC_output be one-transistor be unlocked during, the current potential of the pairing online data of this transistor is used for indicating the GTG that pixel electrode showed that is recharged or discharges.Sweep trace G1, G2, G3 ... current potential when being noble potential, will open each the strange sub-pixel transistor module or each the even sub-pixel transistor module that electrically connect with it.
Polarity control signal POL is used for controlling the reversal of poles of the included a plurality of pixel electrodes of included odd sub-pixel transistor module and even sub-pixel transistor module on the display panel 210.See also Fig. 8, it is according to resultant two picture (Frame) F (n) that play continuously of the waveform operation figure of Fig. 7 and the reversal of poles synoptic diagram of F (n+1).The change in polarity of each odd data (being strange pixel) and even data (being dual pixel) in the single picture of simple and easy diagram among Fig. 8, and come representing positive polarity with+symbol is come representing negative polarity with-symbol.As shown in Figure 7, when sweep trace G1 is in noble potential, each the even sub-pixel transistor that electrically connects with sweep trace G1 is unlocked, at this moment, digital revolving die analog signal DAC_output is as shown in Figure 8 to export even data with positive polarity.And when sweep trace G2 was in noble potential, each the strange sub-pixel transistor that electrically connects with sweep trace G2 was unlocked, and at this moment, digital revolving die analog signal DAC_output is as shown in Figure 8 to export odd data with negative polarity.Then when sweep trace G3 is in noble potential; Each the even sub-pixel transistor that electrically connects with sweep trace G3 will be unlocked; And this moment, polarity control signal POL can transfer electronegative potential to by noble potential, and the even data of digital revolving die analog signal DAC_output output negative pole property as shown in Figure 8.In like manner, when sweep trace G4 was in noble potential, each the strange sub-pixel transistor that electrically connects with sweep trace G4 was unlocked, and the odd data of digital revolving die analog signal DAC_output output cathode property as shown in Figure 8.The rest may be inferred, and last resulting polarity driven changes as shown in Figure 8.
Through the controlling mechanism of polarity control signal POL shown in Figure 7, except can stop direct current residual, also cpable of lowering power consumption, reduce flicker (Flicker) and avoid string news (Crosstalk).
As shown in Figure 7; In the opening time of the one-transistor unit of being opened by start signal STH (Fig. 7 representes with 1H should the opening time); The noble potential of odd even control signal OEH has occupied this half the opening time, and electronegative potential has occupied this half the in addition opening time; When odd even control signal OEH is in noble potential, the strange sub-pixel transistor module that is unlocked by the decision of the sweep trace that is unlocked; Anti-, when odd even control signal OEH is in electronegative potential, the even sub-pixel transistor module that is unlocked by the sweep trace decision that is unlocked.Please note; In other embodiments of the invention; Open even sub-pixel transistor module in the time of also can making odd even control signal OEH be in noble potential, and odd even control signal OEH opens strange sub-pixel transistor module when being in electronegative potential, and not limited by odd even open mode shown in Figure 7.In addition; Though in Fig. 7; In the start-up time of one-transistor unit; Odd even control signal OEH just transfers noble potential to after being introduced into electronegative potential, but just transfers electronegative potential to after also can making odd even control signal OEH be introduced into noble potential in other embodiments of the invention, and does not receive restriction shown in Figure 7.Letter speech, the height potential change of odd even control signal OEH in the opening time of one-transistor unit shown in Fig. 7 and strange/even sub-pixel transistor module corresponding opened to see be or the high electronegative potential sequencing of odd even control signal OEH carries out rational permutation and combination and the various embodiment that produce must belong to category of the present invention.
Mentioned perpendicular line phenomenon before the structure of transistor unit shown in Figure 5 also can be used to prevent.Because the included even sub-pixel transistor ET of strange sub-pixel transistor OT that strange sub-pixel transistor module OB is included and even sub-pixel transistor module EB distributes with the mode of (0pposed) and dispersion (Separated) against each other in transistor unit; Also promptly strange as shown in Figure 5 sub-pixel transistor OT is positioned at the upper left corner of strange sub-pixel transistor module EB; And even sub-pixel transistor ET is positioned at the mode in the lower left corner of even sub-pixel transistor module EB; Come the average light transmission capacity of two sub-pixel transistors on display panel 210 that disperse, make the perpendicular line phenomenon can not occur on the display panel 210.Please note; If the strange sub-pixel transistor OT shown in Fig. 5 is arranged in other position among the strange sub-pixel transistor module OB; Can make that then the light transmission capacity of the even sub-pixel transistor ET that strange sub-pixel transistor OT and other adjacent transistors unit are included is comparatively concentrated, and make the perpendicular line phenomenon take place once more.See also Fig. 9, Figure 10, Figure 11, it is according to other embodiments of the invention, illustrates the synoptic diagram that included being used for of display panel of the present invention prevents the transistor unit of perpendicular line phenomenon.As shown in Figure 9, strange sub-pixel transistor OT is positioned at the lower left in strange sub-pixel transistor module OB, and even sub-pixel transistor ET is positioned at the upper left side in even sub-pixel transistor module EB.Shown in figure 10, strange sub-pixel transistor OT is positioned at the upper right side in strange sub-pixel transistor module OB, and even sub-pixel transistor ET is positioned at the lower right in even sub-pixel transistor module EB.Shown in figure 11, strange sub-pixel transistor OT is positioned at the lower right in strange sub-pixel transistor module OB, and even sub-pixel transistor ET is positioned at the upper right side in even sub-pixel transistor module EB.The design of also adopting against each other and disperseing between strange sub-pixel transistor OT and even sub-pixel transistor ET among Fig. 9, Figure 10, Figure 11, with on average both between and and other transistor unit between light transmission capacity, and avoid the generation of perpendicular line phenomenon.
See also Figure 12, it is the process flow diagram that on display panel, reduces the method for data line according to one embodiment of the invention disclosed.The described step of Figure 12 is the summary of above-mentioned Fig. 3 to the narration of Figure 11, so do not give unnecessary details once more at this.Shown in figure 12, the step that the method that on display panel, reduces data line that the present invention disclosed comprises is following:
Step 300: on a display panel, form a plurality of transistor units with same data line electric connection respectively with a plurality of adjacent strange sub-pixel transistor module in each rowed transistor group of a plurality of rowed transistor groups and with adjacent respectively a plurality of even sub-pixel transistor module;
Step 302: each transistor unit included to this each rowed transistor group is electrically connected at the included strange sub-pixel transistor module of this each transistor unit with one first sweep trace;
Step 304: each transistor unit included to this each rowed transistor group is electrically connected at the included even sub-pixel transistor module of this each transistor unit with one second sweep trace;
Step 306: in the opening time to this each rowed transistor group, open this first sweep trace and this second sweep trace in turn; And
Step 308: according to opening this first sweep trace or this second sweep trace; And according to a Polarity Control signal; Online data being electrically connected at this strange sub-pixel transistor module and this idol sub-pixel transistor module provides a voltage, this voltage is write this strange sub-pixel transistor module or should idol sub-pixel transistor module.
Each included step of process flow diagram shown in Figure 12 is merely a preferred embodiment of the present invention, and each step shown in Figure 12 is reasonably made up and arrange other embodiment that is produced must belong to category of the present invention.
The present invention discloses a kind of display panel that reduces data line quantity, comprises the LCD module and the method for this display panel.In the display panel and method that the present invention disclosed, sub-pixel transistor module adjacent in twos in each rowed transistor group is electrically connected to same data line, make the employed data line quantity of display panel reduce by half; Though can be accompanied by the cost that sweep trace quantity doubles; But because generally the data line quantity of display panel is much larger than the characteristic of sweep trace quantity, the employed drive integrated circult element number of display panel that therefore generally speaking the present invention disclosed still can significantly reduce.In display panel of the present invention and method, also cooperate polarity control signal to realize reversal of poles the voltage of online data, avoiding the residual shortcoming of direct current, and reduce power consumption, reduce flicker and avoid the string news through this.In addition; Included each transistor unit in the display panel that the present invention disclosed, included separately sub-pixel transistor are also through against each other and the arrangement that disperses overcomes because the higher shortcoming that causes the perpendicular line phenomenon to take place of the light transmission capacity of sub-pixel transistor own.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a display panel is characterized in that, said display panel comprises:
A plurality of rowed transistor groups are arranged as a transistor matrix, and each rowed transistor group of said a plurality of rowed transistor groups is arranged on the said transistor matrix with the row mode, and each rowed transistor group of said a plurality of rowed transistor groups comprises:
A plurality of strange sub-pixel transistor modules; And
A plurality of even sub-pixel transistor modules be staggered with said a plurality of strange sub-pixel transistor modules, and said a plurality of even sub-pixel transistor module correspond respectively to said a plurality of strange sub-pixel transistor module;
One first scanline groups; Comprise a plurality of first sweep traces; Each first sweep trace of said a plurality of first sweep traces corresponds respectively to said a plurality of rowed transistor group, and each first sweep trace of said a plurality of first sweep traces is electrically connected at one of them included a plurality of strange sub-pixel transistor module of said a plurality of rowed transistor groups;
One second scanline groups; Comprise a plurality of second sweep traces; Each second sweep trace of said a plurality of second sweep traces corresponds respectively to said a plurality of rowed transistor group, and each second sweep trace of said a plurality of second sweep traces is electrically connected at one of them included a plurality of even sub-pixel transistor module of said a plurality of rowed transistor groups; And
A plurality of data lines; Each data line of said a plurality of data lines is arranged with line mode in said transistor matrix; And each data line of said a plurality of data lines is electrically connected at a strange sub-pixel transistor module and an even sub-pixel transistor module in each rowed transistor groups of said a plurality of rowed transistor groups, and is wherein adjacent one another are in said rowed transistor group and form a transistor unit by said strange sub-pixel transistor module that each data line of said a plurality of data lines electrically connected and said even sub-pixel transistor module in same rowed transistor group;
In each rowed transistor group of said a plurality of rowed transistor groups, the strange sub-pixel transistor module of each of said a plurality of strange sub-pixel transistor modules comprises:
One strange sub-pixel transistor; And
One first pixel electrode is electrically connected at said strange sub-pixel transistor;
Wherein in each rowed transistor group of said a plurality of rowed transistor groups, the even sub-pixel transistor module of each of said a plurality of even sub-pixel transistor modules comprises:
One even sub-pixel transistor; And
One second pixel electrode is electrically connected at said even sub-pixel transistor;
Wherein a data-driven unit is electrically connected at said a plurality of data line, and the one scan driver element is electrically connected at said first scanline groups and said second scanline groups;
Said scan drive cell is opened said first scanline groups and said second scanline groups in turn according to an odd even control signal, with the said a plurality of strange sub-pixel transistor module in each rowed transistor group of the said a plurality of rowed transistor groups of mutual driving and said a plurality of even sub-pixel transistor module;
Said data-driven unit determines the GTG that said a plurality of strange sub-pixel transistor module and said a plurality of even sub-pixel transistor module are exported according to a data-signal, and implements reversal of poles according to a polarity control signal.
2. display panel as claimed in claim 1; It is characterized in that; In said transistor unit, the included said even sub-pixel transistor of the included said even sub-pixel transistor module of said strange sub-pixel transistor AND gate of said strange sub-pixel transistor module with against each other and the mode of disperseing arrange.
3. display panel as claimed in claim 2 is characterized in that, in said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the upper left corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the lower left corner of said even sub-pixel transistor module; In said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the lower left corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the upper left corner of said even sub-pixel transistor module; In said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the upper right corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the lower right corner of said even sub-pixel transistor module; In said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the lower right corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the upper right corner of said even sub-pixel transistor module.
4. a method that reduces the employed data line of each described display panel of claim 1 to 3 is characterized in that said method comprises the steps:
On a display panel; Electrically connect with same data line respectively with a plurality of strange sub-pixel transistor module in each rowed transistor group of a plurality of rowed transistor groups and with the adjacent respectively a plurality of even sub-pixel transistor module of said a plurality of strange sub-pixel transistor modules, and form a plurality of transistor units;
Each transistor unit included to each rowed transistor group of said a plurality of rowed transistor groups is electrically connected at the included strange sub-pixel transistor module of each transistor unit of said a plurality of transistor units with one first sweep trace;
Each transistor unit included to each rowed transistor group of said a plurality of rowed transistor groups is electrically connected at the included even sub-pixel transistor module of each transistor unit of said a plurality of transistor units with one second sweep trace;
In the opening time to each rowed transistor group of said a plurality of rowed transistor groups, open said first sweep trace and said second sweep trace in turn; And
According to opening said first sweep trace or said second sweep trace; And according to a polarity control signal; Online data being electrically connected at said strange sub-pixel transistor module and said even sub-pixel transistor module provides a voltage, said voltage is write said strange sub-pixel transistor module or said even sub-pixel transistor module;
Said strange sub-pixel transistor module comprises:
One strange sub-pixel transistor; And
One first pixel electrode is electrically connected at said strange sub-pixel transistor;
Wherein said even sub-pixel transistor module comprises:
One even sub-pixel transistor; And
One second pixel electrode is electrically connected at said even sub-pixel transistor;
In the said opening time to each rowed transistor group of said a plurality of rowed transistor groups, open said first sweep trace in turn and said second sweep trace comprises:
Open said strange sub-pixel transistor and said even sub-pixel transistor in turn;
According to opening said first sweep trace or said second sweep trace; And according to said polarity control signal; Said online data being electrically connected at said strange sub-pixel transistor module and said even sub-pixel transistor module provides a voltage, said voltage is write said strange sub-pixel transistor module or said even sub-pixel transistor module comprises:
Said voltage is write said first pixel electrode or said second pixel electrode;
In the said opening time to each rowed transistor group of said a plurality of rowed transistor groups, the step of opening said first sweep trace and said second sweep trace in turn specifically comprises:
The one scan control module is opened said first sweep trace and said second sweep trace in turn;
According to opening said first sweep trace or said second sweep trace; And according to said polarity control signal; Said online data being electrically connected at said strange sub-pixel transistor module and said even sub-pixel transistor module provides said voltage, said voltage is write said strange sub-pixel transistor module or said even sub-pixel transistor module comprises:
One DCU data control unit is according to opening said first sweep trace or said second sweep trace, and according to said polarity control signal, said voltage is provided.
5. method as claimed in claim 4; It is characterized in that; In said transistor unit, the included said even sub-pixel transistor of the included said even sub-pixel transistor module of said strange sub-pixel transistor AND gate of said strange sub-pixel transistor module with against each other and the mode of disperseing arrange.
6. method as claimed in claim 5 is characterized in that, in said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the upper left corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the lower left corner of said even sub-pixel transistor module; In said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the lower left corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the upper left corner of said even sub-pixel transistor module; In said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the upper right corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the lower right corner of said even sub-pixel transistor module; In said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the lower right corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the upper right corner of said even sub-pixel transistor module.
7. a LCD module is characterized in that, said LCD module comprises:
One display panel, said display panel comprises:
A plurality of rowed transistor groups are arranged as a transistor matrix, and each rowed transistor group of said a plurality of rowed transistor groups is arranged on the said transistor matrix with the row mode, and each rowed transistor group of said a plurality of rowed transistor groups comprises:
A plurality of strange sub-pixel transistor modules; And
A plurality of even sub-pixel transistor modules be staggered with said a plurality of strange sub-pixel transistor modules, and said a plurality of even sub-pixel transistor module correspond respectively to said a plurality of strange sub-pixel transistor module;
One first scanline groups; Comprise a plurality of first sweep traces; Each first sweep trace of said a plurality of first sweep traces corresponds respectively to said a plurality of rowed transistor group, and each said a plurality of first sweep trace of said a plurality of first sweep traces are electrically connected at one of them included a plurality of strange sub-pixel transistor module of said a plurality of rowed transistor groups;
One second scanline groups; Comprise a plurality of second sweep traces; Said a plurality of second sweep traces of each of said a plurality of second sweep traces correspond respectively to said a plurality of rowed transistor group, and each second sweep trace of said a plurality of second sweep traces is electrically connected at one of them included a plurality of even sub-pixel transistor module of said a plurality of rowed transistor groups; And
A plurality of data lines; Each data line of said a plurality of data lines is arranged with line mode in said transistor matrix; And each data line of said a plurality of data lines is electrically connected at a strange sub-pixel transistor module and an even sub-pixel transistor module in each rowed transistor groups of said a plurality of rowed transistor groups, and is wherein adjacent one another are in said rowed transistor group and form a transistor unit by a strange sub-pixel transistor module that each data line of said a plurality of data lines electrically connected and an even sub-pixel transistor module in same rowed transistor group;
The one scan driver element; Be electrically connected at said first scanline groups and said second scanline groups; Said scan drive cell is used for opening in turn said first scanline groups and said second scanline groups, with the output and the reversal of poles of the said a plurality of strange sub-pixel transistor module in each rowed transistor group of the said a plurality of rowed transistor groups of mutual driving and said a plurality of even sub-pixel transistor modules; And
One data-driven unit; Be electrically connected at said a plurality of data line; Said data-driven unit is according to opening said first sweep trace or said second sweep trace; And, a voltage is provided according to a polarity control signal, said voltage write said strange sub-pixel transistor module or said even sub-pixel transistor module and to implement reversal of poles;
Said LCD module also comprises:
Time schedule controller is used to provide a data-signal, said polarity control signal, an enabling signal, reaches an odd even control signal to said data-driven unit, and controls the sweep trace that said scan drive cell is opened according to said odd even control signal;
In each transistor unit of said a plurality of transistor units; Said data letter signal is used for controlling the GTG that said strange sub-pixel transistor module or said even sub-pixel transistor module are shown, said enabling signal is used for starting the program that each transistor units of said a plurality of transistor units is opened by corresponding scanning line;
Said scan drive cell is opened said first scanline groups and said second scanline groups in turn according to said odd even control signal, with the said a plurality of strange sub-pixel transistor module in each rowed transistor group of the said a plurality of rowed transistor groups of mutual driving and said a plurality of even sub-pixel transistor module;
In each rowed transistor group of said a plurality of rowed transistor groups, the strange sub-pixel transistor module of each of said a plurality of strange sub-pixel transistor modules comprises:
One strange sub-pixel transistor; And
One first pixel electrode is electrically connected at said strange sub-pixel transistor;
Wherein in each rowed transistor group of said a plurality of rowed transistor groups, the even sub-pixel transistor module of each of said a plurality of even sub-pixel transistor modules comprises:
One even sub-pixel transistor; And
One second pixel electrode is electrically connected at said even sub-pixel transistor.
8. LCD module as claimed in claim 7; It is characterized in that; In said transistor unit, the included said even sub-pixel transistor of the included said even sub-pixel transistor module of said strange sub-pixel transistor AND gate of said strange sub-pixel transistor module with against each other and the mode of disperseing arrange.
9. LCD module as claimed in claim 8; It is characterized in that; In said transistor unit, said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the upper left corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the lower left corner of said even sub-pixel transistor module;
Module is in said transistor unit, and said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the lower left corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the upper left corner of said even sub-pixel transistor module; Module is in said transistor unit, and said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the upper right corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the lower right corner of said even sub-pixel transistor module; Module is in said transistor unit, and said strange sub-pixel transistor module is arranged in the left of said transistor unit, and said even sub-pixel transistor module is arranged in the right-hand of said transistor unit;
In said strange sub-pixel transistor module, said strange sub-pixel transistor layout is in the lower right corner of said strange sub-pixel transistor module;
In said even sub-pixel transistor module, said even sub-pixel transistor layout is in the upper right corner of said even sub-pixel transistor module.
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| CN105093761B (en)* | 2015-09-21 | 2019-05-14 | 京东方科技集团股份有限公司 | Array substrate, display device and wearable device |
| KR102486413B1 (en)* | 2016-06-15 | 2023-01-10 | 삼성디스플레이 주식회사 | Display panel and display apparatus including the same |
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| JPH08278485A (en) | 1995-02-06 | 1996-10-22 | Casio Comput Co Ltd | Driving method of active matrix LCD |
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