CN101977152A - High-performance network-on-chip system suitable for reconfiguration - Google Patents

Abstract

The invention belongs to the technical field of network-on-chip system designs, and in particular relates to a high-performance network-on-chip system suitable for reconfiguration. By adding a plurality of reconfigurable circuit IP cores, such as an FPGAIP (Field Programmable Gate Array Internet Protocol) core, and a plurality of configuration bit stream storage unit IP cores in a network-on-chip node, a reconfigurable parallel operating system is realized. The traditional network-on-chip structure is improved, and a sub-network suitable for reconfiguration is added, so that the reconfiguration of the system can be completed at high speed during the reconfiguration, without influencing the normal network communication function. The high-performance network-on-chip system ensures that the network integrates double characteristics of packet switching and circuit switching, and has an important meaning for constructing a high-performance reconfiguration system.

Description

A kind of high-performance network-on-a-chip that is suitable for reconstruct

Technical field

The invention belongs to the network-on-a-chip design field, be specifically related to a kind of high-performance network-on-a-chip that is suitable for reconstruct.

Background technology

Along with improving constantly of single-chip integrated level, the continuous increase of IP module in the system, bus-structured organizational form shows increasing constraint.Module constantly increases, and bus performance but can not correspondingly promote.In recent years, the proposition of network-on-chip (NoC) structure efficiently solved this contradiction.

But, when network-on-chip is used for the restructural application, unsatisfactory.Owing to when reshuffling, require configuration to finish as early as possible, reshuffle the bit stream high efficiency of transmission, traditional NoC network can't adapt to.At this situation, the present invention proposes the high-performance network-on-a-chip framework that is suitable for reconstruct, and improved network configuration, carried out the optimal design of network at the reconstruct feature.

Summary of the invention

Goal of the invention of the present invention is to provide a kind of high performance network-on-a-chip that is suitable for reconstruct.

High-performance network-on-a-chip provided by the invention is to add reconfigurable circuit IP kernel and bit stream memory cell IP kernel in network-on-a-chip, and has improved network service foundation structure, has made up the high performance parallel arithmetic system that is suitable for reconstruct.

In network-on-a-chip, add the reconfigurable circuit IP kernel, as the FPGA IP kernel, just make SOC (system on a chip) have the restructural characteristic.This system uses for realizing that restructural is parallel, is significant.

Make up the reconfigurable network system, promptly on the network-on-chip basis, each node is inserted various computing units and reconstructed module respectively, as processor (CPU), memory (SRAM), reconfigurable circuit (FPGA), configuration bit stream memory cell, dedicated processes hardware (ASIC, RFID), Peripheral Interface etc.Each unit all has resource network interface (RNI) to be connected to router.

Because during reshuffling, reshuffle the unit and need great amount of data transmission, traditional packet network communication structure can't satisfy its bandwidth demand.For this reason, the present invention adds in network configuration and reshuffles private access, make itself and conventional communication networks is parallel exists, during reshuffling, be connected to form special use and reshuffle the circuit switching path, make and reshuffle and can finish at a high speed.In addition, because the adding of this configuration network, must add in the routing infrastructure has the module that connects control for reshuffling.This structure combines the flexibility and the Circuit-switched high performance nature of packet network.

In addition, any universal or special IP kernel that needs high speed data transfer can be connected to high-speed data channel (promptly reshuffling private access) and come up, can improve the performance of total system like this, as: processor IP, DSP IP, exclusive data processing ASIC IP kernel etc.

Technique effect:

After having adopted this reconfigurable network-on-chip, system can have both the high-performance of concurrent operation and the advantage of the flexibility that restructural calculates.

Description of drawings

Fig. 1 is a restructural network-on-a-chip example.

Fig. 2 is a restructural network-on-chip routing interface.

Embodiment

At first in network node, add reconfigurable circuit FPGA IP kernel and dispose bit stream storage unit circuit IP kernel accordingly.In conventional network-on-chip, add the configure dedicated express network, and make route add configuration transmission controlled function.Describe with an example below.

Accompanying drawing 1 is a possible restructural network-on-a-chip example.It is made of the mesh network of a 3x3, comprises 9 routing nodes, is designated as R11, R12, R13, R21, R22, R23, R31, R32, R33.Node inserts various possible IP kernels respectively, as processor (CPU), memory (SRAM), reconfigurable circuit (FPGA), and configuration bit stream memory cell, dedicated processes hardware (ASIC, RFID), Peripheral Interface etc.Each unit all has resource network interface (RNI) to be connected to router.Yellow arrows has been represented the general communication network, and red arrow is the specialized configuration passage at the restructural characteristics design.As seen from the figure, the FPGA IP kernel has been connected designated lane to router with configuration bit stream memory cell IP kernel.When reshuffling when carrying out, configuration bit stream is by the high-speed channel high efficiency of transmission, and this has improved allocative efficiency on the one hand, has saved the general communication resource on the other hand again, makes layoutprocedure not influence the operate as normal of other modules.

Accompanying drawing 2 is depicted as the routing interface part in this network.Because the adding of configuration sub-network is different with conventional route, need in this route to add and reshuffle transmission control module, comprise the route control of reshuffling transmission, and conventional transmission and the coordination control of reshuffling transmission.In addition, the resource network interface also has been divided into conventional coffret and reconfiguration data interface, and the reconfiguration data interface often is included in the configuration control circuit of reshuffling IP kernel.When reshuffling transmission when carrying out, Route Selection is determined switched circuit, makes configuration data reshuffle the interface high-speed transfer from the bit stream memory cell to RNI then.In this stage, the conventional route transmission of this route still can be moved, and still can correctly transmit by this route based on the networking data of packet switch.Like this, one in conjunction with packet switch and Circuit-switched routing infrastructure, can effectively improve systematic function.

The example system of Fig. 1 realizes encryption and decryption functions.Owing in the encryption and decryption computing, have a large amount of general-purpose operation, and computing has concurrency, this for the reconstruct concurrent operation provides may.Universal operating unit is designed to special-purpose ASIC IP kernel, and with the difference circuit be set to respectively two kinds the configuration bit streams be stored in two bit stream memory cell.When encrypting, configuration all is configured to encrypted circuit with two FPGA, all is configured to decrypt circuit during deciphering, and this just can allow encryption and decryption parallel running in two FPGA.In addition, RFID can be used for chip identification, makes the chip can be tracked; Peripheral Interface IP is used for peripheral hardware mutual; Other adds CPU, makes that whole system can be by CPU control operation.

Workflow is as follows:

1, after system powered on, CPU started and carries out initial configuration by configure dedicated network control FPGA;

When 2, system carries out cryptographic calculation, can allow FPGA and ASIC work in coordination with and finish, and allow two FPGA carry out parallel computation;

3, when needs are decrypted, CPU control FPGA reshuffles, and at this moment, FPGA reshuffles by the configure dedicated network high-speed once more, notifies CPU by the NoC network after finishing;

4, after this, the CPU control FPGA decrypt operation that walks abreast.

As seen, this system has realized high performance restructural concurrent operation.

Claims (3)

Translated fromChinese

1.一种适合于重构的高性能片上网络系统，其特征在于是在片上网络系统中加入可重构电路IP核和位流存储单元IP核，并改进网络通信基础结构，构建适合于重构的高性能并行运算系统，即在片上网络基础上，将各节点分别接入各种计算单元和重构模块，包括处理器、存储器、可重配置电路、配置位流存储单元、专用处理硬件和外设接口；每个单元均有资源网络接口连接到路由器；并且在网络结构中加入重配置专用通路，该重配置专用通路与传统通信网络并行存在。1. A high-performance network-on-chip system suitable for reconfiguration is characterized in that a reconfigurable circuit IP core and a bit stream storage unit IP core are added to the network-on-chip system, and the network communication infrastructure is improved to construct a system suitable for reconfiguration. A high-performance parallel computing system, that is, on the basis of the network-on-chip, connect each node to various computing units and reconfiguration modules, including processors, memories, reconfigurable circuits, configuration bit stream storage units, and dedicated processing hardware and peripheral interfaces; each unit has a resource network interface connected to the router; and a reconfiguration dedicated path is added to the network structure, and the reconfiguration dedicated path exists in parallel with the traditional communication network.2.根据权利要求1所述的适合于重构的高性能片上网络系统，其特征在于在路由结构中加入有对于重配置连接控制的模块。2. The high-performance network-on-chip system suitable for reconfiguration according to claim 1, characterized in that a module for reconfiguration connection control is added to the routing structure.3.根据权利要求1所述的适合于重构的高性能片上网络系统，其特征在于所有IP核都连接到重配置专用通路上。3. The high-performance network-on-chip system suitable for reconfiguration according to claim 1, characterized in that all IP cores are connected to reconfiguration dedicated paths.

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