CN101977021B - Multi-channel digital down-conversion device - Google Patents

Abstract

The invention discloses a multi-channel digital down-conversion device, which comprises a signal acquisition module, an m*n-way switch matrix, a digital down-conversion module and an FPGA controller. Firstly, the FPGA controller controls the digital down-conversion module and determines the working mode of the digital down-conversion module, such as a narrow-band parallel mode, an orthogonal joint mode and an orthogonal alternative joint mode; secondly, the FPGA controller controls the input/output connection state of the m*n-way switch matrix to further finish the paired connection between an m-channel signal acquisition channel and a digital down-conversion channel so as to carry out demodulation according to different down-conversion working modes; and thirdly, the FPGA controller controls each digital down-converter and writes the index parameters of a numerical control oscillator, the index parameters of a digital extractor and the index parameters of a low-pass filter into corresponding internal registers so that each digital down-converter can be independently programmed. The digital down-conversion device of the invention can realize digital down-conversion processing of various band widths and various index parameters for multiple-channel digital intermediate-frequency signals, ensuring better real-time performance.

Description

A kind of multi-channel digital down-conversion device

Technical field

The invention belongs to the digital down-conversion technology field, more specifically, relate to a plurality of analog if signals are carried out the device that Digital Down Convert is handled.

Background technology

Analog if signal must be moved the gained digital medium-frequency signal to base band after sampling through analog to digital converter (ADC), and this moves process is exactly so-called digital down-conversion technology.The Digital Down Convert process comprises quadrature demodulation, digital decimation and LPF.

Fig. 1 is the concrete realization block diagram of digital down converter.As shown in Figure 1, digital down converter mainly is made up of digital controlled oscillator NCO, digital decimation device and low pass filter.Sampled data that digital down converter will carry out obtaining after the ADC sampling to analog if signal and the output signal of NCO carry out quadrature mixing (frequency of NCO is the centre frequency of required narrow band signal); Make desired signal by medium-frequency transformation to base band; And make suitable filtering extraction, thereby reduce sample rate according to the relation of baseband bandwidth and sample rate.Digital down converter is finally exported baseband I, Q two paths of signals.Therefore, the task that Digital Down Convert part institute will accomplish, one side is that required narrow band signal is extracted, and it is moved to base band; On the other hand, the narrow band signal for after separating can reduce sample rate greatly, and this also just means can reduce data volume greatly, to alleviate the Base-Band Processing part to the requirement of the computation rate of DSP with to the requirement of follow-up data real-time Transmission.

The multi-channel digital down-conversion device is based on a kind of digital processing device of digital down-conversion technology, can accomplish quadrature demodulation, digital decimation and LPF to a plurality of channel sample data.

Fig. 2 is the multi-channel digital down-conversion device of prior art.As shown in Figure 2; Each road signal sampling channel can only be connected with a fixing way word down-conversion passage, and separate between every way word down-conversion passage, and mode of operation is more single; Because this multi-channel digital down-conversion device functional structure is relatively limited to; Therefore when receiving burst or accidental unknown signaling, then need carry out the storage of certain hour to this signal earlier, and then attempt repeatedly Digital Down Convert and handle and just can obtain more parameter information and confirm this unknown signaling; This device processing capability in real time very a little less than, and poor effect.

Summary of the invention

The objective of the invention is to overcome the deficiency of prior art, a kind of multi-channel digital down-conversion device that has more property versatile and flexible, has more real-time is provided.

For realizing above-mentioned purpose, multi-channel digital down-conversion device of the present invention comprises:

One signal acquisition module is made up of m road separate signal acquisition channel, and every road signal sampling channel comprises analog signal conditioner circuit and analog to digital converter; Be used for the multi-channel analog intermediate-freuqncy signal is nursed one's health and digitlization; Obtain m road sampled data, wherein, signal sampling channel way m >=2;

It is characterized in that, also comprise:

One m * n way switch matrix; Its m road input is connected with the m road sampled data of signal acquisition module output, is used for m road sampled data is selected, and any one tunnel sampled data is connected with any one or more of switch matrix n road output; Wherein, switch matrix output way n=4m;

One Digital Down Converter Module; Form by n programmable digital down converter; The input of n programmable digital down converter links to each other with the output of switch matrix n road respectively, and each programmable digital down converter carries out quadrature demodulation, digital decimation and low-pass filtering treatment to the sampled data that is input to this digital down converter;

One FPGA controller, as the control command of main control chip reception host computer, realize three kinds of controls through command analysis and distribution:

The first, the control figure down conversion module, confirm the mode of operation of Digital Down Converter Module:

1), the work of arrowband parallel schema: n programmable digital down converter independent parallel, form n Digital Down Convert passage;

2), quadrature united mode: per two programmable digital down converter associated working; Form n/2 Digital Down Convert passage; In the same Digital Down Convert passage, the real part of complex data after the digital down converter output orthogonal demodulation, and the imaginary part of another digital down converter output complex data; Under this mode of operation, the Base-Band Processing bandwidth is 2 times of arrowband parallel schema;

3), quadrature replaces united mode: per four programmable digital down converter associated working; Form n/4 Digital Down Convert passage; In the same Digital Down Convert passage, two digital down converters are exported the real part and the imaginary part of even time input signal complex data after quadrature demodulation respectively, and two other digital down converter is exported the real part and the imaginary part of strange time input signal complex data after quadrature demodulation respectively; Under this mode of operation, the Base-Band Processing bandwidth is 4 times of arrowband parallel schema;

The second, the input and output connection status of control m * n way switch matrix, and then accomplish m road signal sampling channel and be connected with the pairing of Digital Down Convert passage, make it carry out demodulation according to different down-conversion mode of operations;

The 3rd, control each digital down converter, the index parameter of digital controlled oscillator (NCO), the index parameter of digital decimation device and the index parameter of low pass filter are write corresponding internal register, make each digital down converter independently programmable.

Goal of the invention of the present invention is to realize like this; One host computer; Be any personal computer, industrial computer or embedded computer, have specific transmission routine module maybe can be installed, can pass through computer bus; Like pci bus; Send the index parameter configuration data of programmable digital down converter in mode of operation select command and the Digital Down Converter Module of control command to switch matrix, Digital Down Converter Module to the FPGA controller, the order that FPGA will receive and data are carried out command analysis and distribution, thereby reach the purpose of passage pairing, model selection and the setting of each digital down converter parameter.

Compare with multi-channel digital down-conversion device commonly used; Multi-channel digital down-conversion device of the present invention can work in three kinds of different patterns; And m road signal sampling channel and g (g=n under each pattern; N/2 n/4) can match connection arbitrarily between the individual Digital Down Convert passage, have property versatile and flexible; At synchronization; When selecting the arrowband parallel schema; The by-pass cock matrix, then a signal sampling channel can be connected with n programmable digital down-converter passage pairing at most simultaneously, can obtain simultaneously through the base-band information after the processing of n kind different digital down-conversion parameter; When selecting the quadrature united mode; The by-pass cock matrix; Then a signal sampling channel can be connected with n/2 programmable digital down-converter passage pairing at most simultaneously; Base-band information after can obtaining simultaneously to handle through n/2 kind different digital down-conversion parameter, and to obtain the Base-Band Processing bandwidth in this case be 2 times of arrowband parallel schema; When selecting quadrature to replace united mode; The by-pass cock matrix; Then a signal sampling channel can be connected with n/4 programmable digital down-converter passage pairing at most simultaneously; Base-band information after can obtaining simultaneously to handle through n/4 kind different digital down-conversion index, and to obtain the Base-Band Processing bandwidth in this case be 4 times of arrowband parallel schema.

It is thus clear that Digital Down Convert device provided by the invention is through multichannel intersection, the parallel mode of multi-mode; Can handle in the Digital Down Convert that synchronization carries out various bandwidth, multiple index parameter the multichannel unknown signaling; Solved the functional structure limitation of multi-channel digital down-conversion device commonly used; Special in burst or accidental unknown signaling, can obtain many group base-band informations simultaneously through once sampling, real-time performance is better.

Description of drawings

Fig. 1 is the concrete realization block diagram of digital down converter;

Fig. 2 is the multi-channel digital down-conversion device of prior art;

Fig. 3 is the structure chart under three kinds of mode of operations of Digital Down Converter Module;

Fig. 4 be signal sampling channel with the Digital Down Convert passage between be connected sketch map;

Fig. 5 is the theory diagram of a kind of embodiment of multi-channel digital down-conversion device of the present invention;

Fig. 6 is that the internal register of each programmable digital down converter in the present embodiment is formed sketch map.

Embodiment

Describe below in conjunction with the accompanying drawing specific embodiments of the invention, so that those skilled in the art understands the present invention better.What need point out especially is that in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these were described in here and will be left in the basket.

Fig. 3 is the structure chart under three kinds of mode of operations of Digital Down Converter Module.

As shown in Figure 3, Digital Down Converter Module is made up of n programmable digital down converter, and each programmable digital down converter carries out quadrature demodulation, digital decimation and low-pass filtering treatment to the digital signal that is input to this digital down converter.Digital Down Converter Module is connected with the FPGA controller, under the control of FPGA controller, can work in three kinds of different patterns, comprising:

1) arrowband parallel schema: n programmable digital down converter 1～n independent parallel work forms n Digital Down Convert passage 1～n, shown in Fig. 3 (a).

2) quadrature united mode: per two programmable digital down converter associated working; Form n/2 Digital Down Convert passage; Shown in Fig. 3 (b); In the same Digital Down Convert passage, the real part of complex data after the digital down converter output orthogonal demodulation, and the imaginary part of another digital down converter output complex data.Shown in Fig. 3 (b), programmable digital down converter 1,2 is formed Digital Down Convert passage 1, and programmable digital down converter 3,4 is formed Digital Down Convert passage 2, and the like, programmable digital down converter n-1, n form Digital Down Convert passage n/2.Under the quadrature united mode, the Base-Band Processing bandwidth is 2 times of arrowband parallel schema.

3) quadrature replaces united mode: per four programmable digital down converter associated working; Form n/4 Digital Down Convert passage; Shown in Fig. 3 (c); Digital Down Convert passage 1 is made up of digital down converter 1～4, and digital down converter 1 and digital down converter 2 are exported the real part and the imaginary part of even time input signal complex data after quadrature demodulation respectively, and digital down converter 3 and digital down converter 4 are exported the real part and the imaginary part of strange time input signal complex data after quadrature demodulation respectively.The composition of Digital Down Convert passage 2～n/4 and the like.Under this mode of operation, the Base-Band Processing bandwidth is 4 times of arrowband parallel schema;

Fig. 4 be signal sampling channel with the Digital Down Convert passage between be connected sketch map.

M * n way switch matrix is connected with Digital Down Converter Module; Be used for controlling the annexation of g Digital Down Convert passage in the signal acquisition module m road separate signal acquisition channel and Digital Down Converter Module under every kind of mode of operation; Arrowband parallel schema: g=n; Quadrature united mode: g=n/2, quadrature replaces united mode: g=n/4.At synchronization, the by-pass cock matrix can make each Digital Down Convert passage select a signal sampling channel as its signal source input arbitrarily.As shown in Figure 4; Like this, m road separate signal acquisition channel can match arbitrarily with g Digital Down Convert passage in the Digital Down Converter Module and be connected: signal sampling channel 1 is connected i=1,2 with down-conversion passage i; ..., g, signal sampling channel 2 is connected j=1 with down-conversion passage j; 2 ..., g, and j ≠ i; Signal sampling channel m is connected with down-conversion passage k, k=1, and 2 ...; G, and k ≠ i, j, the annexation of Digital Down Convert passage in other signal sampling channels and the Digital Down Converter Module.

Fig. 5 is the theory diagram of a kind of embodiment of multi-channel digital down-conversion device of the present invention.

In the present embodiment; As shown in Figure 5; The multi-channel digital down-conversion device comprises signal acquisition module 1, switch matrix 2, Digital Down Converter Module 3, FPGA digital signal processing module 4,FPGA controller 5, FIFO memory 6,communication interface modules 7 and host computer 8, and FPGA digital signal processing module 4 communicates throughcommunication interface modules 7 and host computer 8 withFPGA controller 5.

In the present embodiment; Signal acquisition module 1 is made up of 4 separate signal acquisition channels; Label is followed successively by CH1, CH2, CH3, CH4 from top to bottom, and Digital Down Converter Module is made up of 16 programmable digital down converters, label is followed successively by 1,2,3 from top to bottom ..., 15,16; Inner several registers that exist of each programmable digital down converter are called internal register.Internal register comprises the target component register and replaces time register (SAMPLE_REG), and is as shown in Figure 6.The target component register comprises digital controlled oscillator NCO parameter register, digital decimation device parameter register and low pass filter parameter register etc., and digital down converter is carried out the work of corresponding digital down-conversion according to the parameter value of these registers; Alternately time register (SAMPLE_REG) is confirmed the time series mode that digital down converter is handled, and supposes through the data sequence that is input to digital down converter after the ADC sampling to be:

f＝{x[0]，x[1]，x[2]，x[3]，x[4]，...，x[i]，...}

Then when SAMPLE_REG=0, digital down converter will carry out Digital Down Convert to this sequence to be handled; When SAMPLE_REG=1, digital down converter will be to the idol of this sequence time, and is promptly right:

f1＝{x[0]，x[2]，x[4]，x[6]，x[8]，...，x[2i]，...}

Carrying out Digital Down Convert handles; When SAMPLE_REG=2, digital down converter will be to the odd item of this sequence, and is promptly right:

f2＝{x[1]，x[3]，x[5]，x[7]，x[9]，...，x[2i+1]，...}

Carrying out Digital Down Convert handles;

In the present embodiment; The logic control process of 5 pairs of digital down converters of FPGA controller is achieved in that each digital down converter internal register is corresponding one by one with a destination address, andFPGA controller 5 is connected with the data/address bus ofcommunication interface modules 7 the data/address bus port of digital down converter respectively with the address bus port with address bus; When needs carry out write operation to digital down converter; Host computer 8 will send one toFPGA controller 5 throughcommunication interface modules 7 and write enable command; AndFPGA controller 5 will be written to internal register with the data on the address bus ofcommunication interface modules 7 immediately according to the write operation control timing of digital down converter; Wherein,FPGA controller 5 is called register configuration with the process that control command writes the digital down converter internal register.

In the present embodiment; At first,FPGA controller 5 is confirmed the passage mode of operation in the Digital Down Converter Module 3 according to the Digital Down Converter Module mode of operation select command that receives; Layoutprocedure is described below: when being operated in the arrowband parallel schema; 16 digital down converter independent parallel work form 16 Parallel Digital down-conversion passages, and alternately time register (SAMPLE_REG) value that disposes each digital down converter is 0; When being operated in the quadrature united mode, per two digital down converter associated working form eight Parallel Digital down-conversion passages, and promptly 1,2 unite and are first passage, and 3,4 to unite be second passage ..., 15,16 to unite be the 8th passage.Dispose the phase deviation that pi/2 is arranged between the quadrature mixed frequency signal of digital controlled oscillator NCO output of two digital down converters in each Digital Down Convert passage, alternately time register (SAMPLE_REG) value that disposes all digital down converters is 0; When being operated in quadrature and replacing united mode; Per four digital down converter associated working; Form four Parallel Digital down-conversion passages, promptly 1,2,3,4 unite and are first passage, and 5,6,7,8 to unite be second passage; 9,10,11,12 to unite be the 3rd passage, and 13,14,15,16 to unite be the 4th passage.Dispose the phase deviation that pi/2 is arranged between the quadrature mixed frequency signal of digital controlled oscillator NCO output of the digital down converter 1,2 in each passage; The phase deviation of pi/2 is arranged between the quadrature mixed frequency signal of the digital controlled oscillator NCO output of configuration digital down converter 3,4; Alternately time register (SAMPLE_REG) value of configuration digital down converter 1,2 is 1, and alternately time register (SAMPLE_REG) value of configuration digital down converter 3,4 is 2.

Then; The switch matrix control command thatFPGA controller 5 receives from host computer 8; The input and output connection status of switch matrix 2 is switched and adjusted, realize matching accordingly between the Digital Down Convert passage in 4 signal sampling channels and the Digital Down Converter Module 3 in the signal acquisition module 1 and be connected;

At last, fpgalogic control circuit 5 is configured target component register in each digital down converter internal register, makes each digital down converter according to the user work is set.

In the present embodiment; For baseband sampling data bit width and the data fifo bus bit wide that makes each passage output in the Digital Down Converter Module 3 is complementary; FPGA digital signal processing circuit 4 will carry out corresponding bit wide to these baseband digital data to be handled, and is sent in the follow-up FIFO memory 6 and carries out buffer memory;

In the present embodiment; Be difficult to the problem that is complementary withcommunication interface modules 7 message transmission rates for the image data speed that solves signal acquisition module 1; Utilize FIFO memory 6 to make the data buffer memory; The baseband sampling data that to pass through after FPGA handles are stored, and then bycommunication interface modules 7, are sent to host computer 8.

In practical application; The user can select a signal sampling channel or a plurality of signal sampling channel according to self-demand; Selection is imported same digital medium-frequency signal or different digital medium-frequency signals to a plurality of signal sampling channels; Select the mode of operation of Digital Down Converter Module and the pairing annexation of signal sampling channel and Digital Down Convert passage, to accomplish specific function.Import a certain unknown digital medium-frequency signal such as selecting to one road signal sampling channel; Digital Down Converter Module is set to be operated under the arrowband parallel schema; The by-pass cock matrix; This signal sampling channel is matched with 16 programmable digital down converters simultaneously to be connected; And 16 digital down converter target component registers are carried out separate configurations, the base-band information after can obtaining simultaneously to handle through 16 kinds of different digital down-conversion parameters has greatly improved the detectability to this unknown digital medium-frequency signal.Selection is imported four road unknown digital medium-frequency signals simultaneously to four road signal sampling channels; Digital Down Converter Module is set to be operated under the arrowband parallel schema; The by-pass cock matrix; Make four road signal sampling channels match simultaneously and be connected with a, b, c, the individual Digital Down Convert passage of d (a+b+c+d≤16) respectively; And 16 digital down converter target component registers are carried out separate configurations, the base-band information after then can obtaining respectively simultaneously to handle through a, b, c, d kind different digital down-conversion index is easy to detect simultaneously this four road unknown digital medium-frequency signal.

Selection is imported a certain known digital intermediate-freuqncy signal to one road signal sampling channel; Or to multiplexed signal sampling passage input multichannel known digital intermediate-freuqncy signal; Digital Down Converter Module 3 is set to be operated in quadrature united mode and quadrature and to replace united mode following time; Can carry out the Digital Down Convert processing of 2 times and 4 times Base-Band Processing bandwidth to these input signals, can obtain abundant more base-band information, help the user to carry out follow-up data and handle; The present invention can be built into high speed real-time data acquisition system, can be widely used in fields such as radar, signal of communication processing.

Although above the illustrative embodiment of the present invention is described; So that the technical staff of present technique neck understands the present invention, but should be clear, the invention is not restricted to the scope of embodiment; To those skilled in the art; As long as various variations appended claim limit and the spirit and scope of the present invention confirmed in, these variations are conspicuous, all utilize innovation and creation that the present invention conceives all at the row of protection.

Claims (2)

1. multi-channel digital down-conversion device; Comprise: a signal acquisition module, to form by m road separate signal acquisition channel, every road signal sampling channel comprises analog signal conditioner circuit and analog to digital converter; Be used for the multi-channel analog intermediate-freuqncy signal is nursed one's health and digitlization; Obtain m road sampled data, wherein, signal sampling channel way m >=2; It is characterized in that, also comprise:

One m * n way switch matrix; Its m road input is connected with the m road sampled data of signal acquisition module output, is used for m road sampled data is selected, and any one tunnel sampled data is connected with any one or more of switch matrix n road output; Wherein, switch matrix output way n=4m;

One Digital Down Converter Module; Form by n programmable digital down converter; The input of n programmable digital down converter links to each other with the output of switch matrix n road respectively, and each programmable digital down converter carries out quadrature demodulation, digital decimation and low-pass filtering treatment to the sampled data that is input to programmable digital down converter;

One FPGA controller, as the control command of main control chip reception host computer, realize three kinds of controls through command analysis and distribution:

The first, the control figure down conversion module, confirm the mode of operation of Digital Down Converter Module:

1), the work of arrowband parallel schema: n programmable digital down converter independent parallel, form n Digital Down Convert passage;

2), quadrature united mode: per two programmable digital down converter associated working; Form n/2 Digital Down Convert passage; In the same Digital Down Convert passage, the real part of complex data after the programmable digital down converter output orthogonal demodulation, and the imaginary part of another programmable digital down converter output complex data; Under this mode of operation, the Base-Band Processing bandwidth is 2 times of arrowband parallel schema;

3), quadrature replaces united mode: per four programmable digital down converter associated working; Form n/4 Digital Down Convert passage; In the same Digital Down Convert passage; Two programmable digital down converters are exported the real part and the imaginary part of even time input signal complex data after quadrature demodulation respectively; Two other programmable digital down converter is exported the real part and the imaginary part of strange time input signal complex data after quadrature demodulation respectively, and under this mode of operation, the Base-Band Processing bandwidth is 4 times of arrowband parallel schema;

The second, the input and output connection status of control m * n way switch matrix, and then accomplish m road signal sampling channel and be connected with the pairing of Digital Down Convert passage, make it carry out demodulation according to different down-conversion mode of operations;

The 3rd, control each programmable digital down converter, the index parameter of digital controlled oscillator, the index parameter of digital decimation device and the index parameter of low pass filter are write corresponding internal register, make each programmable digital down converter independently programmable.

2. multi-channel digital down-conversion device according to claim 1 is characterized in that, described internal register comprises the target component register and replaces time register;

The target component register comprises digital controlled oscillator NCO parameter register, digital decimation device parameter register and low pass filter parameter register etc., and programmable digital down converter is carried out the work of corresponding digital down-conversion according to the parameter value of these registers; Alternately time register is confirmed the time series mode that programmable digital down converter is handled, and the data sequence that is input to programmable digital down converter is:

f＝{x[0]，x[1]，x[2]，x[3]，x[4]，...，x[i]，...}

Then when replacing time register SAMPLE_REG=0, programmable digital down converter will carry out Digital Down Convert to this sequence to be handled;

When time register SAMPLE_REG=1 alternately, programmable digital down converter will be to the idol of this sequence time, and is promptly right: f₁=x [0], and x [2], x [4], x [6], x [8] ..., x [2i] ... } carry out Digital Down Convert and handle;

When SAMPLE_REG=2, programmable digital down converter will be to the odd item of this sequence, and is promptly right: f₂=x [1], and x [3], x [5], x [7], x [9] ..., x [2i+1] ... } carry out Digital Down Convert and handle;

When being operated in the arrowband parallel schema, n programmable digital down converter independent parallel work forms n Parallel Digital down-conversion passage, and the alternately time register SAMPLE_REG value that disposes each programmable digital down converter is 0;

When being operated in the quadrature united mode, per two programmable digital down converter associated working form n/2 Parallel Digital down-conversion passage; Dispose the phase deviation that pi/2 is arranged between the quadrature mixed frequency signal of digital controlled oscillator output of two programmable digital down converters in each Digital Down Convert passage, the alternately time register SAMPLE_REG value of configuration all programmable digital down converter is 0;

When being operated in quadrature and replacing united mode, per four programmable digital down converter associated working form n/4 Parallel Digital down-conversion passage; Dispose the phase deviation that pi/2 is arranged between the quadrature mixed frequency signal of digital controlled oscillator output of preceding two programmable digital down converters in each passage; Dispose the phase deviation that pi/2 is arranged between the quadrature mixed frequency signal of digital controlled oscillator output of latter two programmable digital down converter; The alternately time register SAMPLE_REG value that disposes preceding two programmable digital down converters is 1, and the alternately time register SAMPLE_REG value that disposes latter two programmable digital down converter is 2.

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