CN101924536A - Low frequency oscillator applied to burst mode dimming control of CCFL driving system - Google Patents

Abstract

The invention provides a low frequency oscillator applied to burst mode dimming control of a CCFL driving system.The oscillator system comprises a first voltage-current converter configured to receive first voltage and generate first current at least based on information related to the first voltage and a second voltage-current converter configured to receive second voltage and generate second current at least based on information related to the second voltage.In addition, the oscillator system also comprises a current mode N-bit digital to analog converter configured to at least receive the second current and a first clock signal and to generate third current at least based on information related to the second current and the first clock signal.N is a first integral number.The first time clock signal is related to a first time clock frequency corresponding to a first time clock period.In addition, the oscillator system also comprises a current comparator which is coupled to the first current-voltage converter and current mode N-bit digital to analog converter.

Description

The low-frequency oscillator that is used for the burst mode brightness adjustment control of CCFL drive system

Technical field

The present invention relates to oscillator.More particularly, the invention provides the oscillator that low-frequency periodic signal (periodic signal) can be provided with high accuracy.

Background technology

Only as example, the present invention has been applied to the burst mode brightness adjustment control (burst mode dimming control) of cold-cathode fluorescence lamp (CCFL) backlight driving system.Yet, will be appreciated that the present invention has wideer range of application.For example, the present invention can be applied to the integrated circuit (IC) system except that the CCFL backlight driving system.In another example, the present invention can be applied to the equipment except that integrated circuit.

The burst mode dimming control technique has used widely in cold-cathode fluorescence lamp (CCFL) backlight driving system, is used to control the brightness of CCFL.In the burst mode brightness adjustment control, need low-frequency oscillator usually.In order to realize low-frequency oscillator, various conventional arts are used to generate the periodic signal of expected frequency.

For example, traditional relaxation oscillator (relaxation oscillator) or multivibrator are widely used as the low-frequency oscillator in the monolithic integrated circuit design.Such relaxation oscillator can be that R-C discharges and recharges oscillator, constant current charge-discharge oscillator and/or emitter-base bandgap grading coupled harmonic oscillator.In order to realize low oscillator frequency, need outer (off-chip) resistor of sheet and sheet external capacitive body usually.

Fig. 1 is the simplification diagrammatic sketch that traditional low frequency relaxation oscillator is shown.Oscillator 100 passes through the threshold voltage levels V between two inner settings_HAnd V_LBetween external definition capacitor C_ExtAlternately discharge and recharge, operate.Discharging and recharging like this causes generating periodically clock signal LCLK, and the frequency of this periodicity clock signal LCLK and the capacitance of time capacitor are inversely proportional to.

Fig. 2 is the simplification tradition diagrammatic sketch that the waveform that is generated by the low frequency relaxation oscillator is shown.For example, the low frequency relaxation oscillator is an oscillator 100.In another example, V_H, V_L, V_RampAll represent signal voltage with in the waveform of LCLK each as the function of time.

As depicted in figs. 1 and 2, one or more resistors are normally used for forming constant-current source I_CWith constant inflow current source (constant current sink) I_DElectric current I_CBe used for according to following formula outside time capacitor C_ExtCharging:

$T_{\mathrm{ON}}=\frac{(V_H-V_L)\×C_O}{I_C}$(equation 1)

T wherein_ONBe the charging interval, and C_OBe time capacitor C_ExtElectric capacity.In addition, electric current I_DBe used for according to following formula time capacitor C_ExtDischarge:

$T_{\mathrm{OFF}}=\frac{(V_H-V_L)\×C_O}{I_D}$(equation 2)

T wherein_OFFIt is discharge time.Therefore, according to following formula by capacitor being discharged and recharged determine switching frequency F_S:

$F_S=\frac{1}{T_{\mathrm{ON}}+T_{\mathrm{OFF}}}=\frac{1}{(V_H-V_L)C_O}\×\frac{I_C{I}_D}{I_C+I_D}$(equation 3)

Yet common cost height of traditional low-frequency oscillator and/or precision are low.Therefore, the technology that is used for oscillator is demanded urgently improving.

Summary of the invention

The present invention relates to oscillator.More particularly, the invention provides the oscillator that low-frequency periodic signal can be provided with high accuracy.Only as example, the present invention has been applied to the burst mode brightness adjustment control of cold-cathode fluorescence lamp (CCFL) backlight driving system.Yet, will be appreciated that the present invention has wideer range of application.For example, the present invention can be applied to the integrated circuit (IC) system except that the CCFL backlight driving system.In another example, the present invention can be applied to the equipment except that integrated circuit.

According to one embodiment of present invention, a kind of oscilator system comprises: first voltage is to current converter, and it is configured to receive first voltage and generates first electric current based on the information that is associated with first voltage at least; And second voltage to current converter, it is configured to receive second voltage and generates second electric current based on the information that is associated with second voltage at least.In addition, this oscilator system also comprises current-mode N bit digital-to-analog converter, it is configured to receive at least second electric current and first clock signal, and is configured to generate the 3rd electric current based on the information that is associated with second electric current and first clock signal at least.N is first integer.First clock signal is associated with pairing first clock frequency of first clock cycle.In addition, this oscilator system also comprises current comparator, it is coupled to first voltage to current converter and current-mode N bit digital-to-analog converter, and is configured to generate the second clock signal based on the information that is associated with first electric current and the 3rd electric current at least.Pairing second clock frequency dependence connection of second clock signal and second clock cycle.Current comparator also is configured to: judge whether the 3rd electric current is equal to or greater than first electric current on magnitude (magnitude); And if the 3rd electric current is judged as is equal to or greater than first electric current on magnitude, so the second clock signal is changed to second voltage level from first voltage level on magnitude.Current-mode N bit digital-to-analog converter also is configured to receive the second clock signal.If the second clock signal does not change to second voltage level from first voltage level, the 3rd electric current begins to increase in magnitude from the predetermined current rank so.If the second clock signal changes to second voltage level from first voltage level, the 3rd electric current is reduced to the predetermined current rank on magnitude so.

According to another embodiment of the present invention, a kind of oscilator system comprises: first voltage is to current converter, and it is configured to receive first voltage and generates first electric current based on the information that is associated with first voltage at least; And second voltage to current converter, it is configured to receive second voltage and generates second electric current based on the information that is associated with second voltage at least.In addition, this oscilator system also comprises current-mode N bit digital-to-analog converter, it is configured to receive at least second electric current and first clock signal, and is configured to generate the 3rd electric current based on the information that is associated with second electric current and first clock signal at least.N is first integer.First clock signal is associated with pairing first clock frequency of first clock cycle.In addition, this oscilator system also comprises current comparator, it is coupled to first voltage to current converter and current-mode N bit digital-to-analog converter, and is configured to generate the second clock signal based on the information that is associated with first electric current and the 3rd electric current at least.Pairing second clock frequency dependence connection of second clock signal and second clock cycle.Current comparator also is configured to: judge whether the 3rd electric current is equal to or greater than first electric current on magnitude; And if the 3rd electric current is judged as is equal to or greater than first electric current on magnitude, so the second clock signal is changed to second voltage level from first voltage level on magnitude.First voltage comprises first resistor that is associated with first resistance at least to current converter.First electric current is directly proportional with first ratio between first voltage and first resistance.In addition, second voltage comprises second resistor that is associated with second resistance at least to current converter.Second electric current is directly proportional with second ratio between second voltage and second resistance.

According to another embodiment of the present invention, a kind of method that is used to generate clock signal may further comprise the steps: receive first voltage by first voltage to current converter; At least generate first electric current based on the information that is associated with first voltage; Receive second voltage by second voltage to current converter; At least generate second electric current based on the information that is associated with second voltage.In addition, this method also comprises by current-mode N bit digital-to-analog converter and receives second electric current and first clock signal at least.N is first integer.First clock signal is associated with pairing first clock frequency of first clock cycle.In addition, this method also comprises: generate the 3rd electric current based on the information that is associated with second electric current and first clock signal at least; Come the information that is associated with first electric current and the 3rd electric current is handled by current comparator; And generate the second clock signal based on the information that is associated with first electric current and the 3rd electric current at least.Pairing second clock frequency dependence connection of second clock signal and second clock cycle.The step that the information that is associated with first electric current and the 3rd electric current is handled comprises judges whether the 3rd electric current is equal to or greater than first electric current on magnitude; And the step that generates the second clock signal comprises if the 3rd electric current is judged as be equal to or greater than first electric current on magnitude, so the second clock signal is changed to second voltage level from first voltage level on magnitude.In addition, the step that receives second electric current and first clock signal at least comprises and receives the second clock signal.In addition, the step that generates the 3rd electric current comprises: if the second clock signal does not change to second voltage level from first voltage level, begin to increase the 3rd electric current in magnitude from the predetermined current rank so; And if the second clock signal changes to second voltage level from first voltage level, so the 3rd electric current is reduced to the predetermined current rank on magnitude.

Many advantages that are better than conventional art have been realized by the present invention.Some embodiment of the present invention provides the periodic signal with expected frequency in integrated circuit.For example, periodic signal is relevant with the burst mode brightness adjustment control in the CCFL backlight driving system.In another example, periodic signal need can be used to any application of low-frequency oscillator.Some embodiment of the present invention provides high-precision low-frequency oscillator, and does not need the sheet external capacitive body.

According to some embodiment of the present invention because clock signal HCLK and reference voltage signal (for example, Vref1 and Vref2) are fine-tuning (trimmable), so the tolerance limit of off chip resistor device generally be ± 1%.Therefore, for low-frequency periodic signal, satisfied tolerance limit demand less than ± 5% becomes in integrated circuit and is easy to realize.In addition, high-precision low-frequency clock signal can improve the burst mode brightness adjustment control in the LCD TVCCFL backlight driving system, and the CCFL backlight driving system is more suitable in batch process.

According to embodiment, can realize the one or more of these advantages.By with reference to following the detailed description and the accompanying drawings, can fully understand these advantages of the present invention and various attached purpose.

Description of drawings

Fig. 1 is the simplification diagrammatic sketch that traditional low frequency relaxation oscillator is shown.

Fig. 2 is the simplification tradition diagrammatic sketch that the waveform that is generated by the low frequency relaxation oscillator is shown.

Fig. 3 is the simplification diagrammatic sketch that illustrates according to the oscilator system of the embodiment of the invention.

Fig. 4 be illustrate according to the oscilator system of the embodiment of the invention, as the simplification diagrammatic sketch of some signal of the function of time.

Fig. 5 illustrates the simplification diagrammatic sketch of oscilator system according to another embodiment of the present invention.

Fig. 6 illustrates the simplification diagrammatic sketch of conduct according to the current-mode N bit digital-to-analog converter (DAC) of the part of the oscilator system of the embodiment of the invention.

Fig. 7 is the simplification diagrammatic sketch that illustrates according to the Converter Controlled by Current mode PWM device of the embodiment of the invention.

Fig. 8 be illustrate according to the Converter Controlled by Current mode PWM device of the embodiment of the invention, some simplification diagrammatic sketch as the signal of the function of time.

Fig. 9 illustrates the simplification diagrammatic sketch of conduct according to the latch (flip latch) of the part of the Converter Controlled by Current mode PWM device of the embodiment of the invention.

Embodiment

The present invention relates to oscillator.More particularly, the invention provides the oscillator that the periodic signal of low frequency can be provided with high accuracy.Only as example, the present invention has been applied to the burst mode brightness adjustment control at cold-cathode fluorescence lamp (CCFL) backlight driving system.Yet, will be appreciated that the present invention has wideer range of application.For example, the present invention can be applied to the integrated circuit (IC) system except that the CCFL backlight driving system.In another example, the present invention can be applied to the equipment except that integrated circuit.

Conventional art has significant disadvantages usually, and these shortcomings will influence the batch process of the precision and the CCFL drive system of clock signal unfriendly.For example, time capacitor C as shown in Figure 1_ExtCapacitor C_OMay change up to 20%.Big like this variation may cause the great changes of switching frequency to a great extent, and therefore influences the batch process of CCFL drive system.For example, in the LCDTV CCFL backlight driving system the required tolerance limit of burst light modulating frequency fall into usually ± 5% scope in.In order to realize such frequency accuracy, common or needs improve time capacitor C_ExtThe electric capacity precision, perhaps need in the production process more fine setting.Improve improvement and/or extra fine setting and cause higher cost usually.Therefore, need high-precision, cost-efficient low-frequency oscillator.

Fig. 3 is the simplification diagrammatic sketch that illustrates according to the oscilator system of the embodiment of the invention.This diagrammatic sketch only is an example, should exceedingly not limit the scope of claim.Those skilled in the art will expect many variants, substitutions andmodifications.Oscilator system 300 comprises that voltage is tocurrent converter 310 and 320, current-mode N bit digital-to-analog converter (DAC) 330 and current comparator 340.For example, N is a positive integer.

As shown in Figure 3, voltage receivesreference voltage signal 312 andvoltage signal 312 is converted tocurrent signal 314 to current converter 310.For example, use V_Ref1Representreference voltage signal 312, and use I_hRepresent current signal 314.In addition, voltage receivesreference voltage signal 322 andvoltage signal 322 is converted tocurrent signal 324 to current converter 320.For example, use V_Ref2Representreference voltage signal 322, and use I_RefRepresent current signal 324.Current signal 324 is received by current-modeN bit DAC 330, and this current-modeN bit DAC 330 is receivedsignal 332 also.For example,signal 332 is that frequency is f_HCLKClock signal HCLK.

According to an embodiment, electric current I_RefBe used to generate the unitary current of current-mode N bit DAC 330.Based on this unitary current, current-modeN bit DAC 330 generatescurrent signal 334 in response to clock signal HCLK.For example,current signal 334 is slope current signal I_Ramp, its magnitude began to increase from minimal level in a period of time.

Current signal 334 is received bycurrent comparator 340, and thiscurrent comparator 340 is gone back received current signal 314.Current comparator 340 is handled the information that is associated withcurrent signal 314 and 334, and generates signal 342.For example,signal 342 is that frequency is f_LCLKClock signal LCLK.As shown in Figure 3,signal 342 is output signals of oscilator system 300.In addition,signal 342 is also received as reset signal (Reset) by current-modeN bit DAC 330.

In one embodiment, be equal to or greater thancurrent signal 314 ifcurrent signal 334 becomes, clock signal LCLK jumps to logic low voltage level from logic high voltage level so.Such saltus step resets current-modeN bit DAC 330, thereby makes slope current signal I_RampFall back to the minimum current rank.

In another embodiment, clock signal LCLK and clock signal HCLK are synchronous.For example, the ratio between the frequency of the frequency of clock signal HCLK and clock signal LCLK is integer.In another example, the phase difference between clock signal HCLK and the clock signal LCLK is constant.In another embodiment, the precisely controlled clock signal LCLK ofoscilator system 300 generated frequencies.

Fig. 4 be illustrate according to the oscilator system of the embodiment of the invention, as the simplification diagrammatic sketch of some signal of the function of time.This diagrammatic sketch only is an example, should exceedingly not limit the scope of claim.Those skilled in the art will expect many variants, substitutions and modifications.For example, oscilator system is anoscilator system 300 as shown in Figure 3.

As shown in Figure 4,waveform 410 expressions are as the electric current I of the function of time_h, waveform 420 expressions are as the electric current I of the function of time_Ramp, waveform 430 expressions are as the voltage of the clock signal LCLK of the function of time.For example, if current-mode N bit digital-to-analog converter (DAC) 330 is activated, slope current signal I so_RampMagnitude from minimal level I_MinBeginning progressively increases, and each step all equals I on magnitude_Unit

In one embodiment, if slope current signal I_RampBecome and be equal to or greater than electric current I_h, clock signal LCLK is from logic high voltage level V so_HJump to logic low voltage level V_LSuch saltus step resets current-modeN bit DAC 330, thereby makes slope current signal I_RampFall back to the minimum current Grade I_MinSubsequently, slope current signal I_RampIn following one-period, tilt to rise once more (ramp up).Therefore, generated clock signal LCLK.For example, the frequency of signal LCLK is lower than the frequency of signal HCLK.

Fig. 5 illustrates the simplification diagrammatic sketch of oscilator system according to another embodiment of the present invention.This diagrammatic sketch only is an example, should exceedingly not limit the scope of claim.Those skilled in the art will expect many variants, substitutions andmodifications.Oscilator system 500 comprisesoperational amplifier 510 and 512, transistor 520,522,524,530,532 and 534,resistor 540 and 542,current comparator 550, and current-mode N bit digital-to-analog converter (DAC) 560.For example, N is a positive integer.In another example,oscilator system 500 is identical withoscilator system 300.

As shown in Figure 5,operational amplifier 510 receives reference voltage signal V_Ref1Operational amplifier 510 is coupled toresistor 540 and transistor 520.For example,resistor 540 is that resistance is R_BfThe off chip resistor device.Reference voltage signal V_Ref1Be converted to current signal byoperational amplifier 510,resistor 540 andtransistor 520 and 522.If the current ratio of mirroredtransistor 522 and 524 is 1, flow through the electric current I oftransistor 524 so_hBe:

$I_h=\frac{V_{\mathrm{ref}1}}{R_{\mathrm{bf}}}$(equation 4)

Therefore, according to an embodiment, voltage comprisesoperational amplifier 510 tocurrent converter 310, transistor 520,522 and 524, and resistor 540.In addition,operational amplifier 512 receives reference voltage signal V_Ref2Operational amplifier 512 is coupled toresistor 542 and transistor 530.For example,resistor 542 is that resistance is R_IThe off chip resistor device.Reference voltage signal V_Ref2Be converted to current signal byoperational amplifier 512,resistor 542 andtransistor 530 and 532.If the current ratio of mirroredtransistor 532 and 534 is 1, flow through the electric current I oftransistor 534 so_RefBe:

$I_{\mathrm{ref}}=\frac{V_{\mathrm{ref}2}}{R_I}$(equation 5)

Therefore, according to an embodiment, voltage comprisesoperational amplifier 512 tocurrent converter 320, transistor 530,532 and 534, andresistor 542.

As shown in Figure 5, electric current I_RefReceived by current-mode N bit digital-to-analog converter (DAC) 560, this current-modeN bit DAC 560 generates unitary current I according to following formula_Unit:

$I_{\mathrm{unit}}=\frac{V_{\mathrm{ref}2}}{2^N*R_I}$(equation 6)

Wherein N is the bit number of current-mode DAC 560.For example, N is a positive integer.In another example, current-mode DAC 560 is identical with current-mode DAC 330.

According to an embodiment, if current-mode DAC 560 is activated, slope current signal I so_RampMagnitude from minimal level I_MinBeginning progressively increases, and each step all equals I on magnitude_UnitFor example, slope current signal I_RampFrom minimal level I_MinIncrease to electric current I_hRank need spend K step.For example, if minimal level I_MinEqual zero, so:

$K=\frac{I_h}{I_{\mathrm{unit}}}=\frac{2^N*R_I*V_{\mathrm{ref}1}}{R_{\mathrm{bf}}*V_{\mathrm{ref}2}}$(equation 7)

Refer now to Fig. 5,current comparator 550 generates clock signal LCLK.For example,current comparator 550 is identical with current comparator 340.In one embodiment, if electric current I_hGreater than slope current I_Ramp, clock signal LCLK is in logic high voltage level V so_HIf, and electric current I_hBe equal to or less than slope current I_Ramp, clock signal LCLK is in logic low voltage level V so_L

In addition, clock signal LCLK is sent to current-mode N bit DAC 560.For example, if clock signal LCLK from logic high voltage level V_HJump to logic low voltage level V_L, so such saltus step resetsDAC 560, thereby makes slope current signal I_RampFall back to the minimum current Grade I_MinSubsequently, slope current signal I_RampIn following one-period, tilt to rise once more.

For example,$f_{\mathrm{LCLK}}=\frac{f_{\mathrm{HCLK}}}{K}$(equation 8)

F wherein_LCLKBe the frequency of clock signal LCLK, and f_HCLKIt is the frequency of clock signal HCLK.Merge equation 7 and 8, can obtain following expression formula:

$f_{\mathrm{LCLK}}=f_{\mathrm{HCLK}}\frac{R_{\mathrm{bf}}*V_{\mathrm{ref}2}}{2^N*R_I*V_{\mathrm{ref}1}}$(equation 9)

Fig. 6 illustrates the simplification diagrammatic sketch of conduct according to the current-mode N bit digital-to-analog converter (DAC) of the part of the oscilator system of the embodiment of the invention.This diagrammatic sketch only is an example, should exceedingly not limit the scope of claim.Those skilled in the art will expect many variants, substitutions and modifications.Current-mode N bit digital-to-analog converter (DAC) 600 comprisesN bit counter 610 and current mirror 620.For example, current-mode N bit digital-to-analog converter (DAC) 600 is identical with current-mode N bit DAC 330.In another example, current-modeN bit DAC 600 is identical with current-modeN bit DAC 560.

N bit counter 610 receive clock signal HCLK and LCLK.Signal HCLK is used to triggerN bit counter 610, and the signal LCLKN bit counter 610 that is used to reset.The output ofN bit counter 610 is N bit logic signal K_N(t), this signal K_N(t) received bycurrent mirror 620 and be used for conducting or stopcock S₁, S₂..., S_n..., S_N-1And S_NCurrent mirror 620 is gone back received current I_RefFor example, N is a positive integer, and the t express time.

According to an embodiment, N bit logic signal K_N(t) n bit conducting or stopcock S_nN is greater than 0 integer and less than N+1.According to another embodiment, by conducting or stopcock S₁, S₂..., S_n..., S_N-1And S_N, N bit logic signal K_N(t) can change slope current I_RampMagnitude.For example, in case activated current patternN bit DAC 600, N bit logic signal K_N(t) just increase 1 at all after dates of each of clock signal HCLK.N bit logic signal K_N(t) can be by clock signal LCLK reset-to-zero, perhaps at N bit logic signal K_N(t) arrive 2^NAfter be reset to zero.

Fig. 7 is the simplification diagrammatic sketch that illustrates according to the Converter Controlled by Current mode PWM device of the embodiment of the invention.This diagrammatic sketch only is an example, should exceedingly not limit the scope of claim.Those skilled in the art will expect many variants, substitutions and modifications.

Converter Controlled by Currentmode PWM device 700 receives voltage signal DIM.For example, voltage signal DIM is from external source.Voltage signal DIM is handled and is converted into the current signal Idim that flows through transistor M8 by voltage-current converter.In one embodiment, voltage-current converter comprises operational amplifier A 3, transistor M7, M8 and M9, and resistor R 1.If the current ratio of mirrored transistor M8 and M9 is 1, so

$\mathrm{I\; dim}=\frac{\mathrm{V\; dim}}{R1}$(equation 10)

Wherein Vdim is the magnitude of voltage signal DIM.In addition, Converter Controlled by Currentmode PWM device 700 receives reference voltage signal Vrefa.For example, reference voltage signal Vrefa represents the voltage level by the inside sources generation.Reference voltage signal Vrefa is handled and is converted into the current signal that flows through transistor M11 by another voltage-current converter.In one embodiment, voltage-current converter comprisesoperational amplifier A 4, transistor M10, M11 and M12, and resistor R 2.If the current ratio of mirrored transistor M11 and M12 is 1, so

$\mathrm{Irefa}=\frac{\mathrm{Vrefa}}{R2}$(equation 11)

Irefa is received by current-mode DAC 710.In addition, Converter Controlled by Currentmode PWM device 700 comprises latch F1.As shown in Figure 7, latch F1 receive clock signal LCLK and N bit logic signal K_NAnd output N bit logic signal K (t),_N(T_m).T_mM the cycle of expression clock signal LCLK.For example, clock signal LCLK is generated byoscilator system 300 and/or oscilator system 500.In another example, N bit logic signal K_N(t) generate by current-modeN bit DAC 600.

N bit logic signal K_N(T_m) received by current-mode DAC 710.N bit logic signal K_N(T_m) be used for Irefa is divided into K_N(T_m) individual current unit, each current unit equals Iunita.

$\mathrm{Iunita}=\frac{\mathrm{Irefa}}{K_N\left(T_m\right)}=\frac{\mathrm{Vrefa}}{K_N\left(T_m\right)\×R2}$(equation 12)

As shown in Figure 7, clock signal HCLK and LCLK are received by N bit counter 712, and this N bit counter 712 generates output signal p.For example, clock signal HCLK is received byoscilator system 300, and clock signal LCLK is generated byoscilator system 300, and the clock signal LCLK that is received byN bit counter 712 is identical with the clock signal LCLK that is received by latch F1.In another example, clock signal HCLK is received byoscilator system 500, and clock signal LCLK is generated byoscilator system 500, and the clock signal LCLK that is received byN bit counter 712 is identical with the clock signal LCLK that is received by latch F1.

Current-mode DAC 710 generates slope current Idac, and this slope current Idac begins progressively to increase from minimal level at each all after date of clock signal HCLK.Each step equals Iunita.At each all after date of clock signal LCLK, slope current Idac falls back to minimal level, and output signal p is reset to zero.

For example, if minimal level equals zero,

$\mathrm{Idac}=p\×\mathrm{Iunita}=\frac{p\×\mathrm{Vrefa}}{K_N\left(T_m\right)\×R2}$(equation 13)

Current comparator s1 compares the magnitude of Idac and the magnitude of Idim, and this current comparator s1 generates the LPWM signal.For example, the LPWM signal is used to the burst mode brightness adjustment control.

According to an embodiment, if electric current I dim greater than slope current Idac, the LPWM signal is in logic high voltage level so, and if electric current I dim be equal to or less than slope current Idac, the LPWM signal is in logic low voltage level so.

If Idac=I is dim (equation 14)

$\frac{p\×\mathrm{Vrefa}}{K_N\left(T_m\right)\×R2}=\frac{\mathrm{V\; dim}}{R1}$(equation 15)

Suppose R1=R2 (equation 16)

So$\mathrm{Duty}=\frac{p}{K_N\left(T_m\right)}=\frac{\mathrm{V\; dim}}{\mathrm{Vrefa}}$(equation 17)

According to an embodiment,$K_N\left(T_m\right)=\frac{f_{\mathrm{HCLK}}}{f_{\mathrm{LCLK}}}$(equation 18)

And f_LPWM=f_LCLK(equation 19)

F wherein_HCLK, f_LCLKAnd f_LPWMBe respectively the frequency of clock signal HCLK, the frequency of clock signal LCLK and the frequency of LPWM signal.For example, clock signal LCLK and LPWM signal are synchronous.

Fig. 8 be illustrate according to the Converter Controlled by Current mode PWM device of the embodiment of the invention, some simplification diagrammatic sketch as the signal of the function of time.This diagrammatic sketch only is an example, should exceedingly not limit the scope of claim.Those skilled in the art will expect many variants, substitutions and modifications.For example, the Converter Controlled by Current mode PWM device is a Converter Controlled by Currentmode PWM device 700 as shown in Figure 7.

As shown in Figure 8,waveform 810 expressions are as the electric current I dim of the function of time,waveform 820 expressions are as the electric current I dac of the function of time, andwaveform 830 expressions are as the voltage of the clock signal LCLK of the function of time, andwaveform 840 expressions are as the LPWM voltage of signals of the function of time.

Fig. 9 illustrates the simplification diagrammatic sketch of conduct according to the latch of the part of the Converter Controlled by Current mode PWM device of the embodiment of the invention.This diagrammatic sketch only is an example, should exceedingly not limit the scope of claim.Those skilled in the art will expect many variants, substitutions and modifications.For example,latch 900 is identical with as shown in Figure 7 latch F1.

As shown in the figure, latch 900 receive clock signal LCLK and N bit logic signal K_NAnd output N bit logic signal K (t),_N(T_m).T_mM the cycle of expression clock signal LCLK.For example, clock signal LCLK is generated byoscilator system 300 and/or oscilator system 500.In another example, N bit logic signal K_N(t) generate by current-mode N bit DAC600.According to an embodiment, once each cycle of oversampling clock signal LCLK, latch 900 just latchs N bit logic signal K_N(t).Output signal K_N(T_m) during the one-period of clock signal LCLK, remain unchanged.

The invention provides many advantages.Some embodiment of the present invention provides the periodic signal with expected frequency in integrated circuit.For example, this periodic signal is relevant with the burst mode brightness adjustment control in the CCFL backlight driving system.In another example, this periodic signal need can be used to any application of low-frequency oscillator.Some embodiment of the present invention provides high-precision low-frequency oscillator, and does not need the sheet external capacitive body.

According to some embodiment of the present invention because clock signal HCLK and reference voltage signal (for example, Vref1 and Vref2) are fine-tuning, so the tolerance limit of off chip resistor device generally be ± 1%.Therefore, for low-frequency periodic signal, satisfied tolerance limit demand less than ± 5% becomes in integrated circuit and is easy to realize.In addition, high-precision low-frequency clock signal can improve the burst mode brightness adjustment control in the LCD TV CCFL backlight driving system, and the CCFL backlight driving system is more suitable in batch process.

According to another embodiment of the present invention, a kind of oscilator system comprises: first voltage is to current converter, and it is configured to receive first voltage and generates first electric current based on the information that is associated with first voltage at least; And second voltage to current converter, it is configured to receive second voltage and generates second electric current based on the information that is associated with second voltage at least.In addition, this oscilator system also comprises current-mode N bit digital-to-analog converter, it is configured to receive at least second electric current and first clock signal, and is configured to generate the 3rd electric current based on the information that is associated with second electric current and first clock signal at least.N is first integer.First clock signal is associated with pairing first clock frequency of first clock cycle.In addition, this oscilator system also comprises current comparator, it is coupled to first voltage to current converter and current-mode N bit digital-to-analog converter, and is configured to generate the second clock signal based on the information that is associated with first electric current and the 3rd electric current at least.Pairing second clock frequency dependence connection of second clock signal and second clock cycle.Current comparator also is configured to: judge whether the 3rd electric current is equal to or greater than first electric current on magnitude; And if the 3rd electric current is judged as is equal to or greater than first electric current on magnitude, so the second clock signal is changed to second voltage level from first voltage level on magnitude.Current-mode N bit digital-to-analog converter also is configured to receive the second clock signal.If the second clock signal does not change to second voltage level from first voltage level, the 3rd electric current begins to increase in magnitude from the predetermined current rank so.If the second clock signal changes to second voltage level from first voltage level, the 3rd electric current is reduced to the predetermined current rank on magnitude so.For example, realize this oscilator system according to Fig. 3, Fig. 4, Fig. 5 and/or Fig. 6.

In another example, the ratio between first clock frequency and the second clock frequency equals second integer.In another example, first clock signal and second clock signal are synchronous.In another example, first voltage is different with second voltage.In another example, first voltage level is a logic high, and second voltage level is a logic low.In another example, current-mode N bit digital-to-analog converter also is configured to the information that is associated with second electric current is handled, and generates first magnitude based on the information that is associated with second electric current at least.In another example, if the second clock signal does not change to second voltage level from first voltage level, the 3rd electric current begins to increase step by step on magnitude as the function of time from the predetermined current rank so.The single step increase of second magnitude equals first magnitude, and the duration of single step equals the second clock cycle.In another example, current-mode N bit digital-to-analog converter also is configured to generate the N bit logic signal based on the information with first clock signal and second clock signal correction connection at least.In another example, current-mode N bit digital-to-analog converter comprises: the N bit counter, it is configured to receive first clock signal and second clock signal, and generates the N bit logic signal based on the information with first clock signal and second clock signal correction connection at least; And current mirror, it is configured to receive the N bit logic signal and second electric current, and generates the 3rd electric current based on the information that is associated with the N bit logic signal and second electric current at least.

According to another embodiment of the present invention, a kind of oscilator system comprises: first voltage is to current converter, and it is configured to receive first voltage and generates first electric current based on the information that is associated with first voltage at least; And second voltage to current converter, it is configured to receive second voltage and generates second electric current based on the information that is associated with second voltage at least.In addition, this oscilator system also comprises current-mode N bit digital-to-analog converter, it is configured to receive at least second electric current and first clock signal, and is configured to generate the 3rd electric current based on the information that is associated with second electric current and first clock signal at least.N is first integer.First clock signal is associated with pairing first clock frequency of first clock cycle.In addition, this oscilator system also comprises current comparator, it is coupled to first voltage to current converter and current-mode N bit digital-to-analog converter, and is configured to generate the second clock signal based on the information that is associated with first electric current and the 3rd electric current at least.Pairing second clock frequency dependence connection of second clock signal and second clock cycle.Current comparator also is configured to: judge whether the 3rd electric current is equal to or greater than first electric current on magnitude; And if the 3rd electric current is judged as is equal to or greater than first electric current on magnitude, so the second clock signal is changed to second voltage level from first voltage level on magnitude.First voltage comprises first resistor that is associated with first resistance at least to current converter.First electric current is directly proportional with first ratio between first voltage and first resistance.In addition, second voltage comprises second resistor that is associated with second resistance at least to current converter.Second electric current is directly proportional with second ratio between second voltage and second resistance.For example, realize this oscilator system according to Fig. 3, Fig. 4, Fig. 5 and/or Fig. 6.

In another example, current-mode N bit digital-to-analog converter also is configured to receive the second clock signal.If the second clock signal does not change to second voltage level from first voltage level, the 3rd electric current begins to increase in magnitude from the predetermined current rank so; And if the second clock signal changes to second voltage level from first voltage level, the 3rd electric current is reduced to the predetermined current rank on magnitude so.In another example, the 3rd ratio between first clock frequency and the second clock frequency equals second integer.In another example, first clock signal and second clock signal are synchronous.In another example, current-mode N bit digital-to-analog converter also is configured to the information that is associated with second electric current is handled, and generates first magnitude based on the information that is associated with second electric current at least.In another example, if the second clock signal does not change to second voltage level from first voltage level, the 3rd electric current begins to increase step by step on magnitude as the function of time from the predetermined current rank so.Second magnitude that single step increases equals first magnitude; And the duration of single step equals the second clock cycle.In another example, current-mode N bit digital-to-analog converter also is configured to generate the N bit logic signal based on the information with first clock signal and second clock signal correction connection at least.

According to another embodiment of the present invention, a kind of method that is used to generate clock signal may further comprise the steps: receive first voltage by first voltage to current converter; At least generate first electric current based on the information that is associated with first voltage; Receive second voltage by second voltage to current converter; At least generate second electric current based on the information that is associated with second voltage.In addition, this method also comprises by current-mode N bit digital-to-analog converter and receives second electric current and first clock signal at least.N is first integer.First clock signal is associated with pairing first clock frequency of first clock cycle.In addition, this method also comprises: generate the 3rd electric current based on the information that is associated with second electric current and first clock signal at least; Come the information that is associated with first electric current and the 3rd electric current is handled by current comparator; And generate the second clock signal based on the information that is associated with first electric current and the 3rd electric current at least.Pairing second clock frequency dependence connection of second clock signal and second clock cycle.The step that the information that is associated with first electric current and the 3rd electric current is handled comprises judges whether the 3rd electric current is equal to or greater than first electric current on magnitude; And the step that generates the second clock signal comprises if the 3rd electric current is judged as be equal to or greater than first electric current on magnitude, so the second clock signal is changed to second voltage level from first voltage level on magnitude.In addition, the step that receives second electric current and first clock signal at least comprises and receives the second clock signal.In addition, the step that generates the 3rd electric current comprises: if the second clock signal does not change to second voltage level from first voltage level, begin to increase the 3rd electric current in magnitude from the predetermined current rank so; And if the second clock signal changes to second voltage level from first voltage level, so the 3rd electric current is reduced to the predetermined current rank on magnitude.For example, realize being used to generate the method for clock signal according to Fig. 3, Fig. 4, Fig. 5 and/or Fig. 6.

In another example, the ratio between first clock frequency and the second clock frequency equals second integer.In another example, first clock signal and second clock signal are synchronous.In another example, first voltage level is a logic high; And second voltage level is a logic low.In another example, the step that generates the 3rd electric current comprises at least and generates first magnitude based on the information that is associated with second electric current.In another example, the step that generates the 3rd electric current also comprises: if the second clock signal does not change to second voltage level from first voltage level, begin to increase the 3rd electric current in magnitude step by step as the function of time from the predetermined current rank so.Second magnitude that single step increases equals first magnitude; And the duration of single step equals the second clock cycle.In another example, the method that is used to generate clock signal also comprises by current-mode N bit digital-to-analog converter to generate the N bit logic signal based on the information with first clock signal and second clock signal correction connection at least.

Though described specific embodiments of the invention, those skilled in the art should understand other embodiment that exist with described embodiment equivalence.Therefore, should understand the embodiment that the present invention is not limited to specifically illustrate, and only be subject to the scope of claim.

Claims (23)

1. oscilator system, described system comprises:

First voltage is to current converter, and it is configured to receive first voltage and generates first electric current based on the information that is associated with described first voltage at least;

Second voltage is to current converter, and it is configured to receive second voltage and generates second electric current based on the information that is associated with described second voltage at least;

Current-mode N bit digital-to-analog converter, it is configured to receive at least described second electric current and first clock signal, and be configured to generate the 3rd electric current based on the information that is associated with described second electric current and described first clock signal at least, N is first integer, and described first clock signal is associated with pairing first clock frequency of first clock cycle; And

Current comparator, it is coupled to described first voltage to current converter and described current-mode N bit digital-to-analog converter, and be configured to generate the second clock signal based on the information that is associated with described first electric current and described the 3rd electric current at least, pairing second clock frequency dependence connection of described second clock signal and second clock cycle

Wherein, described current comparator also is configured to:

Judge whether described the 3rd electric current is equal to or greater than described first electric current on magnitude; And

If described the 3rd electric current is judged as and is equal to or greater than described first electric current on magnitude, so described second clock signal is changed to second voltage level from first voltage level on magnitude,

Wherein:

Described current-mode N bit digital-to-analog converter also is configured to receive described second clock signal;

If described second clock signal does not change to described second voltage level from described first voltage level, so described the 3rd electric current begins to increase in magnitude from the predetermined current rank; And

If described second clock signal changes to described second voltage level from described first voltage level, so described the 3rd electric current is reduced to described predetermined current rank on magnitude.

2. oscilator system as claimed in claim 1, wherein, the ratio between described first clock frequency and the described second clock frequency equals second integer.

3. oscilator system as claimed in claim 1, wherein, described first clock signal and described second clock signal are synchronous.

4. oscilator system as claimed in claim 1, wherein, described first voltage is different with described second voltage.

5. oscilator system as claimed in claim 1, wherein:

Described first voltage level is a logic high; And

Described second voltage level is a logic low.

6. oscilator system as claimed in claim 1, wherein, described current-mode N bit digital-to-analog converter also is configured to the information that is associated with described second electric current is handled, and generates first magnitude based on the information that is associated with described second electric current at least.

7. oscilator system as claimed in claim 6, wherein:

If described second clock signal does not change to described second voltage level from described first voltage level, so described the 3rd electric current begins to increase step by step on magnitude as the function of time from described predetermined current rank;

Second magnitude that single step increases equals described first magnitude; And

The duration of described single step equals the described second clock cycle.

8. oscilator system as claimed in claim 1, wherein, described current-mode N bit digital-to-analog converter also is configured to generate the N bit logic signal based on the information with described first clock signal and described second clock signal correction connection at least.

9. oscilator system as claimed in claim 1, wherein said current-mode N bit digital-to-analog converter comprises:

The N bit counter, it is configured to receive described first clock signal and described second clock signal, and generates the N bit logic signal based on the information with described first clock signal and described second clock signal correction connection at least; And

Current mirror, it is configured to receive described N bit logic signal and described second electric current, and generates described the 3rd electric current based on the information that is associated with described N bit logic signal and described second electric current at least.

10. oscilator system, described system comprises:

First voltage is to current converter, and it is configured to receive first voltage and generates first electric current based on the information that is associated with described first voltage at least;

Second voltage is to current converter, and it is configured to receive second voltage and generates second electric current based on the information that is associated with described second voltage at least;

Current-mode N bit digital-to-analog converter, it is configured to receive at least described second electric current and first clock signal, and be configured to generate the 3rd electric current based on the information that is associated with described second electric current and described first clock signal at least, N is first integer, and described first clock signal is associated with pairing first clock frequency of first clock cycle; And

Current comparator, it is coupled to described first voltage to current converter and described current-mode N bit digital-to-analog converter, and be configured to generate the second clock signal based on the information that is associated with described first electric current and described the 3rd electric current at least, pairing second clock frequency dependence connection of described second clock signal and second clock cycle

Wherein, described current comparator also is configured to:

Judge whether described the 3rd electric current is equal to or greater than described first electric current on magnitude; And

If described the 3rd electric current is judged as and is equal to or greater than described first electric current on magnitude, so described second clock signal is changed to second voltage level from first voltage level on magnitude,

Wherein:

Described first voltage comprises first resistor that is associated with first resistance at least to current converter, and described first electric current is directly proportional with first ratio between described first voltage and described first resistance; And

Described second voltage comprises second resistor that is associated with second resistance at least to current converter, and described second electric current is directly proportional with second ratio between described second voltage and described second resistance.

11. oscilator system as claimed in claim 10, wherein:

Described current-mode N bit digital-to-analog converter also is configured to receive described second clock signal;

If described second clock signal does not change to described second voltage level from described first voltage level, so described the 3rd electric current begins to increase in magnitude from the predetermined current rank; And

If described second clock signal changes to described second voltage level from described first voltage level, so described the 3rd electric current is reduced to described predetermined current rank on magnitude.

12. oscilator system as claimed in claim 10, wherein, the 3rd ratio between described first clock frequency and the described second clock frequency equals second integer.

13. oscilator system as claimed in claim 10, wherein, described first clock signal and described second clock signal are synchronous.

14. oscilator system as claimed in claim 10, described current-mode N bit digital-to-analog converter also is configured to the information that is associated with described second electric current is handled, and generates first magnitude based on the information that is associated with described second electric current at least.

15. oscilator system as claimed in claim 14, wherein:

If described second clock signal does not change to described second voltage level from described first voltage level, the 3rd electric current begins to increase step by step on magnitude as the function of time from described predetermined current rank so;

Second magnitude that single step increases equals described first magnitude; And

The duration of described single step equals the described second clock cycle.

16. oscilator system as claimed in claim 10, wherein, described current-mode N bit digital-to-analog converter also is configured to generate the N bit logic signal based on the information with described first clock signal and described second clock signal correction connection at least.

17. a method that is used to generate clock signal said method comprising the steps of:

Receive first voltage by first voltage to current converter;

At least generate first electric current based on the information that is associated with described first voltage;

Receive second voltage by second voltage to current converter;

At least generate second electric current based on the information that is associated with described second voltage;

At least receive described second electric current and first clock signal by current-mode N bit digital-to-analog converter, N is first integer, and described first clock signal is associated with pairing first clock frequency of first clock cycle;

At least generate the 3rd electric current based on the information that is associated with described second electric current and described first clock signal;

Come the information that is associated with described first electric current and described the 3rd electric current is handled by current comparator; And

At least generate the second clock signal based on the information that is associated with described first electric current and described the 3rd electric current, pairing second clock frequency dependence connection of described second clock signal and second clock cycle,

Wherein:

The step that the information that is associated with described first electric current and described the 3rd electric current is handled comprises judges whether described the 3rd electric current is equal to or greater than described first electric current on magnitude;

The step that generates the second clock signal comprises if described the 3rd electric current is judged as be equal to or greater than described first electric current on magnitude, so described second clock signal is changed to second voltage level from first voltage level on magnitude;

At least the step that receives described second electric current and first clock signal comprises the described second clock signal of reception; And

The step that generates the 3rd electric current comprises:

If described second clock signal does not change to described second voltage level from described first voltage level, begin to increase described the 3rd electric current from the predetermined current rank so in magnitude; And

If described second clock signal changes to described second voltage level from described first voltage level, so described the 3rd electric current is reduced to described predetermined current rank on magnitude.

18. method as claimed in claim 17, wherein, the ratio between described first clock frequency and the described second clock frequency equals second integer.

19. method as claimed in claim 17, wherein, described first clock signal and described second clock signal are synchronous.

20. method as claimed in claim 17, wherein:

Described first voltage level is a logic high; And

Described second voltage level is a logic low.

21. method as claimed in claim 17, wherein, the step that generates the 3rd electric current comprises at least and generates first magnitude based on the information that is associated with described second electric current.

22. method as claimed in claim 21, wherein, the step that generates the 3rd electric current also comprises:

If described second clock signal does not change to described second voltage level from described first voltage level, begin to increase described the 3rd electric current in magnitude step by step from described predetermined current rank so as the function of time;

Second magnitude that single step increases equals described first magnitude; And

The duration of described single step equals the described second clock cycle.

23. method as claimed in claim 17 also comprises by described current-mode N bit digital-to-analog converter to generate the N bit logic signal based on the information with described first clock signal and described second clock signal correction connection at least.

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