		V_WL	V_BL	whether or not to program
					Programming	Select WL/select BL	V_pp	0V	Is that
	Select WL/unselect BL	V_pp	V_ppOr high resistance	Whether or not
						Unselected WL/selected BL	0V	0V	Whether or not
	Unselected WL/unselected BL	0V	V_ppOr high resistance	Whether or not
									Whether to detect sense amplifier current
Reading	Select WL/select BL	V_read	0V	Is that
						Select WL/unselect BL	V_read	V_dd	Whether or not
	Unselected WL/selected BL	0V	0V	Whether or not
						Unselected WL/unselected BL	0V	V_dd	Whether or not

TABLE 1

In Table 1, breakdown voltage V_ppAt least 2 times greater than the working voltage V_ddAnd is smaller than the breakdown voltage of the diode with smaller reverse breakdown voltage in the first diode and the second diode; read voltage V_readLess than or equal to working voltage V_dd。

And (3) programming process:

applying a breakdown voltage V on the word line WL_ppA voltage of 0V is applied to the bit line BL, thereby breaking down the diode having the smaller reverse breakdown voltage among the first diode and the second diode and turning on the diode having the larger reverse breakdown voltage among the first diode and the second diode in the forward direction. For unselected programmable memory cells, a breakdown voltage Vpp is applied to the bit line BL to prevent the first diode on the selected word line from being struckLeakage occurs through the other programmable memory cells.

Breakdown voltage V under 0.13um logic process_ppSelectable voltage value such as 6-10V, and working voltage V_ddSelectable voltage value, e.g. 1.3V, read voltage V_readA selectable voltage value such as 1V. Of course, the breakdown voltage V depends on the logic process_ppOperating voltage V_ddA read voltage V_readVariations are also possible.

And (3) reading:

applying a read voltage V to the word line WL_readApplying 0V voltage to a bit line BL (bit line), namely applying 0V voltage to an n-type lightly doped region), detecting whether the sense amplifier has current, if so, indicating that a diode with smaller reverse breakdown voltage in the first diode and the second diode is broken down to form a resistor, and if the diode with larger reverse breakdown voltage in the first diode and the second diode is conducted in the forward direction, outputting logic '1'; otherwise, it indicates that the diode with the smaller reverse breakdown voltage of the first diode and the second diode is not broken down, and a logic "0" is output.

FIG. 18A is a schematic diagram of an equivalent circuit of a one-time programmable memory cell with a dual-diode structure according to the first, second, third and sixth embodiments of the present invention; fig. 18A includes afirst diode 1801 and asecond diode 1802 connected in series, where thefirst diode 1801 is connected to the bit line WL and thesecond diode 1802 is connected to the word line BL.

FIG. 18B is a schematic diagram of an equivalent circuit of a one-time programmable memory cell with a dual-diode structure after program breakdown according to the first, second, third and sixth embodiments of the present invention; fig. 18B includes aresistor 1803 and asecond diode 1802 connected in series, wherein theresistor 1803 is formed when thefirst diode 1801 in fig. 18A is broken down by a programming voltage. The current I flows in the direction of the word line WL to the bit line BL.

FIG. 19 is a partial schematic diagram of a one-time programmable memory array with a dual diode structure according to a first, second, third and sixth embodiment of the invention; fig. 19 includes a plurality of one-time programmable memory cells of a two-diode structure, a word line WL1, a word line WL2, a word line WL3, a bit line BL1, a bit line BL2, and a bit line BL3, where each one-time programmable memory cell is connected to one word line and one bit line, respectively. The otp memory cell connected to the word line WL2 and the bit line BL2 at the center of fig. 19 has been programmed to break down, and therefore, the otp memory cell is represented by an equivalent circuit of aresistor 1903 connected in series with adiode 1902.

FIG. 20A is a schematic circuit diagram of a one-time programmable memory cell with a dual-diode structure according to a fourth, fifth, and seventh embodiments of the present invention; fig. 20A includes afirst diode 2001 and asecond diode 2002 connected in series, where thefirst diode 2001 is connected to a bit line WL and thesecond diode 2002 is connected to a word line BL.

FIG. 20B is a schematic diagram of an equivalent circuit of a one-time programmable memory cell with a dual-diode structure after program breakdown according to a fourth, fifth, and seventh embodiments of the present invention; fig. 20B includes aresistor 2003 and afirst diode 2001 connected in series, wherein aresistor 1803 is formed when thesecond diode 2002 of fig. 20A is broken down by a programming voltage. The current I flows in the direction of the word line WL to the bit line BL.

FIG. 21 is a partial schematic diagram of a OTP memory array with a dual diode structure according to a fourth, fifth and seventh embodiments of the invention; fig. 21 includes a plurality of one-time programmable memory cells of a two-diode structure, a word line WL1, a word line WL2, a word line WL3, a bit line BL1, a bit line BL2, and a bit line BL3, where each one-time programmable memory cell is connected to one word line and one bit line, respectively. The otp memory cell connected to word line WL2 and bit line BL2 at the center of fig. 21 has been programmed to break down, and is represented by the equivalent circuit ofdiode 2101series resistor 2103.

The one-time programmable memory, the manufacturing method and the programming reading method have the advantages that the one-time programmable memory unit is simple in structure, small in memory unit area and high in integration level due to the fact that the double-diode structure is adopted.

In addition, because the one-time programmable memory cell is manufactured based on the existing logic process, the one-time programmable memory cell can be scaled down along with the process characteristic size, and the integration level of the one-time programmable memory is further improved along with the development of the process.

In addition, the one-time programmable memory unit can be directly embedded into the SOC chip because no special process is needed to be added.

In addition, the doping concentration of the PN junctions of the two diodes in the diode structure is adjusted, so that only one diode in the double-diode structure is guaranteed to be broken down, and the reliability of the one-time programming memory is improved.

In addition, since the reverse breakdown voltage of the diode is related to the doping concentration of the PN junction of the diode, the breakdown voltage can be adjusted by adjusting the doping concentration of the PN junction of the diode, thereby flexibly designing a programming voltage for programming the memory cell.

In addition, the insulating layer is adopted to replace an inverted trap of the traditional bulk silicon process, and the ion implantation area is effectively isolated through the insulating layer and the isolation groove, so that the stability and the reliability of data storage are improved, and the area of a storage unit is further reduced.

In addition, the invention uses the mutually isolated wells formed by the insulating layer and the isolation trench of the SOI process as the anode of the diode, so that a memory cell with a small area can be manufactured without adding or changing any process step, and the disadvantages of the process performance of the common bulk silicon, such as the latch-up effect and the like, can be avoided.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention, and any modifications, alterations, combinations, equivalents, improvements and the like made to the embodiments of the present invention within the spirit and principle of the present invention should be included in the scope of the present invention.