CN101894281A - A multi-protocol UHF RFID reader baseband signal processing SOC chip - Google Patents

Abstract

The invention discloses a baseband signal processing SOC chip of a multi-protocol UHF RFID reader, comprising a CPU module, a bus in a chip, a storage interface, a DAC output channel, an ADC input channel, a multi-protocol processing unit of an UHF RFID hardware, a man-machine interface, a high-speed communication interface, a low-speed communication interface, a timer module, a JTAG interface module and a master clock module; a high-speed system bus and a low-speed peripheral bus are connected together through a DMA controller and a bus bridge, and each bus is provided with an address decoder and a bus arbitrator; the CPU module, the storage interface, the man-machine interface, the multi-protocol processing unit, the JTAG interface module and the high-speed communication interface are connected with the high-speed system bus; and the low-speed communication interface, the timer module and the master clock module are connected with the low speed peripheral bus. The invention can conveniently realize a handheld UHF RFID reader with high integrated level, low cost, low power consumption and high generality.

Description

Translated fromChinese

一种多协议UHF RFID读写器基带信号处理SOC芯片 A multi-protocol UHF RFID reader baseband signal processing SOC chip

技术领域technical field

本发明涉及一种超高频RFID读写器数字基带信号处理芯片，属于数字基带信号处理芯片技术领域。 The invention relates to a digital baseband signal processing chip for an ultra-high frequency RFID reader-writer, belonging to the technical field of digital baseband signal processing chips. the

背景技术Background technique

被动式超高频射频识别UHF RFID系统(工作频段为860MHz-960MHz)采用反向散射调制模式，工作于远场辐射区，具有读写距离远(可以达到3-10米)、非可视、读写速度快、标签无源等特点，使其广泛应用于仓储物流、停车场管理、资产管理、贵重物品防盗等领域。被动式超高频射频识别RFID系统由读写器、电子标签和后台应用系统构成，其中读写器和电子标签是整个系统的关键。电子标签内部无源而采用无源远端射频供电，内部资源有限，无法完成复杂的信号处理，因此，在RFID系统中读写器的设计性能便是整个系统性能的关键所在。 Passive ultra-high frequency radio frequency identification UHF RFID system (working frequency range is 860MHz-960MHz) adopts backscatter modulation mode, works in the far-field radiation area, has a long reading and writing distance (up to 3-10 meters), non-visual, reading The characteristics of fast writing speed and passive label make it widely used in warehousing logistics, parking lot management, asset management, valuables anti-theft and other fields. The passive UHF radio frequency identification RFID system consists of readers, electronic tags and background application systems, among which the readers and electronic tags are the key to the whole system. The electronic tag is internally passive and uses passive remote radio frequency power supply. The internal resources are limited and complex signal processing cannot be completed. Therefore, the design performance of the reader in the RFID system is the key to the performance of the entire system. the

超高频RFID读写器从结构上分为射频模块和基带控制模块两部分，如图1所示，图中虚线框所围的部分即读写器，其中射频模块主要由调制解调电路和天线组成，主要完成高频信号的调制和解调，发射与接收，是标签和读写器之间的空中无线接口。基带控制模块主要由协议控制模块、编解码模块、数据校验模块、接口模块等组成。其主要功能是控制射频系统，实现对高频信号的编解码功能，并实现类似于ISO18000-6B/6C的UHF RFID标准协议。同时，实现与外部设备或主机之间的应用接口，完成与上位机之间的数据通信。由此可见，基带控制模块是整个RFID读写器的核心，支撑着整个系统的工作。具体来讲，射频模块的主要任务是(1)发射915MHz高频信号，激活电子标签，并且为电子标签提供能量；(2)调制发射信号，将数据信号通过天线发送给电子标签；(3)接受并解调来自电子标签的信号。基带控制模块的主要任务是(1)与应用系统软件进行通信，并执行系统软件发过来的动作指令；(2)实现射频识别协议的编码和解码；(3)控制与射频标签的通信过程；(4)实现多卡的防碰撞冲突算法；(5)对读写器和电子标签之间传送的数据进行加密或解密；(6)实现CRC编码和解码。 The UHF RFID reader is structurally divided into two parts, the radio frequency module and the baseband control module. As shown in Figure 1, the part surrounded by the dotted line in the figure is the reader. Composed of antennas, it mainly completes the modulation and demodulation of high-frequency signals, transmission and reception, and is the air wireless interface between tags and readers. The baseband control module is mainly composed of a protocol control module, a codec module, a data verification module, and an interface module. Its main function is to control the radio frequency system, realize the codec function of high-frequency signals, and realize the UHF RFID standard protocol similar to ISO18000-6B/6C. At the same time, realize the application interface with the external device or the host computer, and complete the data communication with the upper computer. It can be seen that the baseband control module is the core of the entire RFID reader, supporting the work of the entire system. Specifically, the main task of the radio frequency module is (1) to transmit a 915MHz high-frequency signal, activate the electronic tag, and provide energy for the electronic tag; (2) modulate the transmitted signal, and send the data signal to the electronic tag through the antenna; (3) Receive and demodulate signals from electronic tags. The main tasks of the baseband control module are (1) to communicate with the application system software and execute the action instructions sent by the system software; (2) to realize the encoding and decoding of the radio frequency identification protocol; (3) to control the communication process with the radio frequency tag; (4) Realize multi-card anti-collision conflict algorithm; (5) Encrypt or decrypt the data transmitted between the reader and the electronic tag; (6) Realize CRC encoding and decoding. the

对于手持式RFID读写器，其基带控制模块除了完成上面的功能以外，往往还需要人机接口功能(如LCD显示、键盘、触摸屏等)和丰富的通信接口(如RS232、以太网、USB、WiFi等)。 For handheld RFID readers, in addition to the above functions, the baseband control module often requires man-machine interface functions (such as LCD display, keyboard, touch screen, etc.) and rich communication interfaces (such as RS232, Ethernet, USB, WiFi, etc.). the

目前，超高频手持式RFID读写器，一般采CPU+FPGA或CPU+RFID专用芯片(如AS3990)的方式来实现。这两种方法都有一定的缺陷。其中CPU+FPGA方案中，FPGA完成了基带处理功能，但用户接口和通信接口由CPU实现。读写器设计者需要将二者集成在一块电路板上，二者之间的通信速度往往成为提高读写器性能、降低读写器成本和功耗的制约条件。而CPU+RFID专用芯片(如AS3990)方案的优点是RFID专用芯片实现了RFID读写器基带处理、射频模拟前端处理、低量级的功率放大及增益控制等诸多功能，但是关于用户应用接口的功能仍然需要单独的CPU来实现，同样，CPU与RFID专用芯片之间也需要高速通信，读写器的制作成本也很高。 At present, UHF handheld RFID readers are generally realized by CPU+FPGA or CPU+RFID special chip (such as AS3990). Both methods have certain drawbacks. In the CPU+FPGA solution, the FPGA completes the baseband processing function, but the user interface and communication interface are implemented by the CPU. Reader designers need to integrate the two on a circuit board, and the communication speed between the two often becomes the constraint to improve the performance of the reader and reduce the cost and power consumption of the reader. The advantage of the CPU+RFID special chip (such as AS3990) solution is that the RFID special chip realizes many functions such as RFID reader baseband processing, RF analog front-end processing, low-level power amplification and gain control, but the user application interface The function still needs to be realized by a separate CPU. Similarly, high-speed communication is required between the CPU and the RFID dedicated chip, and the production cost of the reader is also very high. the

SOC(System on Chip)称为系统级芯片，是将系统所需要的各种CPU、片内外设、存储器、通信接口甚至A/D和D/A转换等功能模块集成在一块芯片上，即片上系统。SOC提高了 系统集成度，降低了设备成本，提高了可靠性，同时也便于实现低功耗。 SOC (System on Chip) is called a system-level chip, which integrates various CPUs, on-chip peripherals, memory, communication interfaces, and even A/D and D/A conversion functional modules required by the system on one chip, that is, on-chip system. SOC improves system integration, reduces equipment cost, improves reliability, and facilitates low power consumption. the

发明内容Contents of the invention

本发明针对现有RFID基带信号处理方式存在的不足，提供一种可靠性高、功耗低的多协议UHF RFID读写器基带信号处理SOC芯片。 Aiming at the shortcomings of existing RFID baseband signal processing methods, the present invention provides a multi-protocol UHF RFID reader baseband signal processing SOC chip with high reliability and low power consumption. the

本发明的多协议UHF RFID读写器基带信号处理SOC芯片采用以下技术解决方案： The multi-protocol UHF RFID reader baseband signal processing SOC chip of the present invention adopts the following technical solutions:

该基带信号处理SOC芯片包括CPU模块、片内总线、存储器接口、DAC输出通道、ADC输入通道、UHF RFID硬件多协议处理单元、人机接口、高速通信接口、低速通信接口、定时器模块、JTAG接口模块和主时钟模块；片内总线包括高速系统总线和低速外设总线，两条总线之间通过DMA控制器和总线桥连接在一起，每条总线都设有地址译码器和总线仲裁器；CPU模块、存储器接口、人机接口、UHF RFID硬件多协议处理单元、JTAG接口模块以及高速通信接口均与高速系统总线连接；低速通信接口、定时器模块和主时钟模块与低速外设总线连接；高速通信接口、DAC输出通道和ADC输入通道与DMA控制器连接；在CPU模块中包含有用来控制电源管理的低功耗控制模块。 The baseband signal processing SOC chip includes CPU module, on-chip bus, memory interface, DAC output channel, ADC input channel, UHF RFID hardware multi-protocol processing unit, man-machine interface, high-speed communication interface, low-speed communication interface, timer module, JTAG Interface module and master clock module; the on-chip bus includes a high-speed system bus and a low-speed peripheral bus, and the two buses are connected together through a DMA controller and a bus bridge, and each bus is equipped with an address decoder and a bus arbiter ; CPU module, memory interface, man-machine interface, UHF RFID hardware multi-protocol processing unit, JTAG interface module and high-speed communication interface are all connected to high-speed system bus; low-speed communication interface, timer module and main clock module are connected to low-speed peripheral bus ; The high-speed communication interface, the DAC output channel and the ADC input channel are connected to the DMA controller; the CPU module contains a low-power control module for controlling power management. the

DAC输出通道包括3路8位DAC输出通道，其中2路用于输出正交调制需要的I通道和Q通道基带数字信号，另外1路8位P通道DAC输出通道作为功率放大器PA的增益调整输出。 The DAC output channels include 3 8-bit DAC output channels, 2 of which are used to output the I-channel and Q-channel baseband digital signals required for quadrature modulation, and the other 1 8-bit P-channel DAC output channel is used as the gain adjustment output of the power amplifier PA . the

ADC输入通道包括2路8位ADC输入通道，用于输入正交解调后的I通道和Q通道的基带数字信号。 The ADC input channels include two 8-bit ADC input channels for inputting the baseband digital signals of the I channel and the Q channel after quadrature demodulation. the

UHF RFID硬件多协议处理单元：包括编码模块、解码模块、CRC校验模块以及时钟分频模块四部分。 UHF RFID hardware multi-protocol processing unit: including four parts: encoding module, decoding module, CRC check module and clock frequency division module. the

人机接口包括LCD控制器和触摸屏控制器； Man-machine interface includes LCD controller and touch screen controller;

高速通信接口配置有32位GPIO接口、PCI总线接口和USB1.1接口控制器。 The high-speed communication interface is equipped with 32-bit GPIO interface, PCI bus interface and USB1.1 interface controller. the

低速通信接口配置有UART接口、SPI接口模块和IIS音频控制器。 The low-speed communication interface is equipped with UART interface, SPI interface module and IIS audio controller. the

定时器模块配置有2个16位定时计数器计时器和实时时钟。 The timer module is configured with two 16-bit timing counter timers and a real-time clock. the

本发明将UHF RFID读写器所需的各种基带信号处理功能、协议实现功能、应用开发有关的CPU及片内总线功能、片外接口功能、射频电路的增益控制功能、低功耗控制功能集成在了一起。芯片内具有CPU(基于开源的OpenRISC1200即OR1200来实现)，可以嵌入操作系统(如Windows CE、Linux等)，可扩展4G Bytes容量的存储器，集成了ISO18000-6B/6C协议，并提供一种开放式软件接口以实现除ISO18000-6B/6C以外的其它UHF RFID协议、防碰撞算法、定位算法、甚至分布式数据库和中间件。可以非常方便地实现高集成度、低成本、低功耗、高通用性的手持式UHF RFID读写器。 The present invention integrates various baseband signal processing functions, protocol implementation functions, CPU and on-chip bus functions related to application development, off-chip interface functions, gain control functions of radio frequency circuits, and low power consumption control functions required by UHF RFID readers. integrated together. The chip has a CPU (based on the open source OpenRISC1200 or OR1200), which can be embedded in an operating system (such as Windows CE, Linux, etc.), can expand the memory of 4G Bytes capacity, integrates the ISO18000-6B/6C protocol, and provides an open Type software interface to realize other UHF RFID protocols except ISO18000-6B/6C, anti-collision algorithm, positioning algorithm, even distributed database and middleware. It is very convenient to realize a handheld UHF RFID reader with high integration, low cost, low power consumption and high versatility. the

附图说明Description of drawings

图1是现有RFID读写器的结构框图。 Fig. 1 is a structural block diagram of an existing RFID reader-writer. the

图2是本发明超高频RFID基带处理SOC芯片的结构原理框图。 Fig. 2 is a structural principle block diagram of the ultra-high frequency RFID baseband processing SOC chip of the present invention. the

图3是利用本发明的SOC芯片实现的手持式UHF RFID读写器的结构原理框图。 Fig. 3 is the structural principle block diagram of the hand-held UHF RFID reader-writer that utilizes SOC chip of the present invention to realize. the

图4是多协议处理单元的内部结构示意图。 Fig. 4 is a schematic diagram of the internal structure of the multi-protocol processing unit. the

图5是本发明超高频RFID基带处理SOC芯片的启动流程图。 Fig. 5 is a start-up flowchart of the UHF RFID baseband processing SOC chip of the present invention. the

具体实施方式Detailed ways

如图2所示，本发明的超高频RFID基带处理SOC芯片包括CPU模块、片内总线、存储器 接口、DAC输出通道、ADC输入通道、UHF RFID硬件多协议处理单元、人机接口、高速通信接口、低速通信接口、定时器模块、低功耗控制模块和其他模块， As shown in Figure 2, the UHF RFID baseband processing SOC chip of the present invention includes a CPU module, an on-chip bus, a memory interface, a DAC output channel, an ADC input channel, a UHF RFID hardware multi-protocol processing unit, a man-machine interface, and a high-speed communication interface, low-speed communication interface, timer module, low-power control module and other modules,

CPU模块：SOC芯片内置了32位CPU内核(基于OR1200)，该CPU内核利用指令可以完成对整个芯片内各组成模块的协调、配置和工作状态检测等功能。可以嵌入各种嵌入式操作系统(如Windows CE或者Linux等)，以便实现更加灵活的功能，并为用户提供良好的程序接口。另外，还可以通过CPU执行软件对基带信号进行数字滤波、加密、解码、编码、解码等处理。 CPU module: The SOC chip has a built-in 32-bit CPU core (based on OR1200). The CPU core can use instructions to complete functions such as coordination, configuration, and working status detection of each component module in the entire chip. Various embedded operating systems (such as Windows CE or Linux, etc.) can be embedded to achieve more flexible functions and provide users with a good program interface. In addition, the baseband signal can also be digitally filtered, encrypted, decoded, coded, decoded, etc. processed by executing software through the CPU. the

片内总线：SCO芯片内部配置了两条Wishbone总线，分别是高速的系统总线和低速的外设总线。CPU、存储控制器、LCD控制器、触摸屏控制器和多协议控制单元以及高速的通信接口USB和PCI和GPIO接口控制器都是挂在高速系统总线上的。而低速通信接口(如：SPI、PS/2、RS232、IIS和PWM等)和实时时钟RTC控制器是挂在低速外设总线上的。系统总线和外设总线之间通过DMA和总线桥连接在一起。每条总线都有自己的地址译码器，便于独立工作。高速通信接口(如USB和PCI和GPIO接口)和各AD/DA通道也可以在DMA控制器的控制之下完成数据通信。另外，Wishbone总线采用Master和Slaver控制模式，允许多Master，因此需要由总线仲裁器完成总线仲裁。 On-chip bus: Two Wishbone buses are configured inside the SCO chip, which are high-speed system bus and low-speed peripheral bus. CPU, storage controller, LCD controller, touch screen controller and multi-protocol control unit, as well as high-speed communication interface USB, PCI and GPIO interface controllers are all hung on the high-speed system bus. The low-speed communication interface (such as: SPI, PS/2, RS232, IIS and PWM, etc.) and the real-time clock RTC controller are hung on the low-speed peripheral bus. The system bus and the peripheral bus are connected together through DMA and bus bridge. Each bus has its own address decoder to facilitate independent work. High-speed communication interfaces (such as USB, PCI and GPIO interfaces) and each AD/DA channel can also complete data communication under the control of the DMA controller. In addition, the Wishbone bus adopts the Master and Slaver control modes and allows multiple Masters, so the bus arbitration must be completed by the bus arbiter. the

存储器接口：SOC芯片可以扩展多种存储器设备，包括EPROM、SRAM、DRAM、Flash等，利用PCI接口还可以扩展SD卡存储设备，扩展空间最大可以达到4GBytes。 Memory interface: The SOC chip can expand a variety of memory devices, including EPROM, SRAM, DRAM, Flash, etc. The PCI interface can also be used to expand SD card storage devices, and the maximum expansion space can reach 4GBytes. the

DAC输出通道：SOC芯片提供了3路8位DAC通道，其中2路用于输出正交调制需要的I通道和Q通道基带数字信号，另外1路8位P通道DAC通道作为功率放大器PA的增益调整输出。 DAC output channel: The SOC chip provides 3 8-bit DAC channels, 2 of which are used to output the I-channel and Q-channel baseband digital signals required for quadrature modulation, and the other 1 8-bit P-channel DAC channel is used as the gain of the power amplifier PA Adjust the output. the

ADC输入通道：SOC芯片提供了2路8位ADC通道，用于输入正交解调后的I通道和Q通道的基带数字信号。 ADC input channel: The SOC chip provides two 8-bit ADC channels for inputting the baseband digital signals of the I channel and Q channel after quadrature demodulation. the

UHF RFID硬件多协议处理单元：SOC芯片配置有硬件多协议处理单元，可以在ISO18000-6B、ISO18000-6C、EPC Global C1G2等多种UHF RFID协议标准之间的任意切换。通过该单元，可以完成基带信号的PIE编码，FMO编码、Miller解码、CRC校验、各通道信号强度的检测、防碰撞算法的执行，产生帧同步序列，执行协议要求的状态控制等功能。另外，本协议处理单元预留了开放式的软件协议接口，可利用CPU执行软件的方式使本SOC支持除ISO18000-6B、ISO18000-6C、EPC Global C1G2等协议之外的其它UHF RFID协议。 UHF RFID hardware multi-protocol processing unit: The SOC chip is equipped with a hardware multi-protocol processing unit, which can switch between various UHF RFID protocol standards such as ISO18000-6B, ISO18000-6C, and EPC Global C1G2. Through this unit, functions such as PIE encoding of baseband signals, FMO encoding, Miller decoding, CRC check, detection of signal strength of each channel, execution of anti-collision algorithm, generation of frame synchronization sequence, and state control required by the protocol can be completed. In addition, this protocol processing unit reserves an open software protocol interface, which can use the CPU to execute software to make this SOC support other UHF RFID protocols except ISO18000-6B, ISO18000-6C, EPC Global C1G2 and other protocols. the

人机接口：SOC芯片配置了LCD控制器和触摸屏控制器，可以实现友好的人机界面功能。 Man-machine interface: SOC chip is equipped with LCD controller and touch screen controller, which can realize friendly man-machine interface function. the

高速通信接口：SOC芯片配置了32位GPIO接口，便于扩展其它高速并行设备。配置了PCI总线接口，可以方便地扩展以太网，Wi-Fi、USB2.0等高速的通信设备和SD卡等大容量外部存储设备。配置了USB1.1接口控制器，可以提供USB主(Host)接口和USB从(Device)接口。 High-speed communication interface: The SOC chip is equipped with a 32-bit GPIO interface, which is convenient for expanding other high-speed parallel devices. Equipped with a PCI bus interface, it can easily expand Ethernet, Wi-Fi, USB2.0 and other high-speed communication devices and SD cards and other large-capacity external storage devices. Configured with a USB1.1 interface controller, it can provide a USB host (Host) interface and a USB slave (Device) interface. the

低速通信接口：SOC芯片配置了UART接口和SPI接口模块，可以实现一些近距离通信。配置了IIS音频控制器，可实现精彩音频播放和采集。 Low-speed communication interface: The SOC chip is equipped with UART interface and SPI interface module, which can realize some short-distance communication. The IIS audio controller is configured to realize wonderful audio playback and collection. the

定时器模块：SOC芯片配置了2个16位定时计数器计时器，可以提供看门狗定时器和PWM输出功能。配置了实时时钟，可为用户提供精确的时间和日历显示。 Timer module: The SOC chip is equipped with two 16-bit timing counter timers, which can provide watchdog timer and PWM output functions. Equipped with a real-time clock, it can provide users with accurate time and calendar display. the

低功耗控制模块：本芯片支持掉电、待机、工作、唤醒等多工作模式，并可以单独地对 每个接口模块的供电电源进行控制，便于实现灵活的低功耗控制能力。 Low-power control module: This chip supports multiple working modes such as power-down, standby, work, and wake-up, and can individually control the power supply of each interface module to facilitate flexible low-power control capabilities. the

另外还配置了JTAG接口，支持在线调试和程序下载。主时钟模块的外部晶振频率为27MHz，可以通过内部PLL使CPU工作主频率达到150MHz。整个芯片采用单5V供电。 In addition, a JTAG interface is configured to support online debugging and program download. The external crystal frequency of the main clock module is 27MHz, and the main frequency of the CPU can reach 150MHz through the internal PLL. The whole chip is powered by a single 5V. the

利用本发明SOC芯片可以非常方便地实现高集成度、低成本、低功耗、高通用性的手持式UHF RFID读写器，其结构如下图3所示，由图3可见，本发明的SOC芯片输出了正交调制所必须的I通道和Q通道的基带信号(该信号已根据协议要求完成了编码)，用于功率放大器增益调整P通道数字信号，这三路信号都需要外接8位DAC将输出的数字信号转换成模拟信号。I通道和Q通道的基带模拟信号经正交调制(如LT5568)，过带通滤波(BPF)和功率放大器之后，再经环形器送入天线，构成发射通道。对于接收通道，本芯片配置了输入I通道和Q通道接口，用于接收经过正交解调(如LT5516)并经低噪声放大(LNA)和低通滤波(LPF)，然后再经ADC后的基带输入信号。 Using the SOC chip of the present invention can very conveniently realize a handheld UHF RFID reader with high integration, low cost, low power consumption, and high versatility. Its structure is shown in Figure 3 below, as can be seen from Figure 3, the SOC of the present invention The chip outputs the baseband signals of the I channel and Q channel necessary for quadrature modulation (the signal has been encoded according to the protocol requirements), which is used to adjust the P channel digital signal of the power amplifier gain. These three signals need an external 8-bit DAC Convert the output digital signal to an analog signal. The baseband analog signals of the I channel and the Q channel are subjected to quadrature modulation (such as LT5568), passed through a band-pass filter (BPF) and a power amplifier, and then sent to the antenna through a circulator to form a transmission channel. For the receiving channel, the chip is configured with input I channel and Q channel interface, used to receive quadrature demodulation (such as LT5516), low noise amplification (LNA) and low pass filter (LPF), and then ADC Baseband input signal. the

UHF RFID硬件多协议处理单元的功能结构如图4所示，包含了编码模块，解码模块，CRC校验模块以及时钟分频模块四部分。该多协议处理单元模块的工作过程为：时钟分频信号输入后： The functional structure of the UHF RFID hardware multi-protocol processing unit is shown in Figure 4, which includes four parts: encoding module, decoding module, CRC verification module and clock frequency division module. The working process of the multi-protocol processing unit module is: after the clock frequency division signal is input:

(1)编码过程：计算机主机(HOST)给OR1200处理器指令和信息数据后，OR1200处理器发送给编码模块和CRC校验模块启动指令，编码模块接收到启动指令后会返还给OR1200处理器一个应答信号，随后，OR1200处理器会把数据信息传入编码模块和CRC校验模块。当编码数据完成后，将产生的CRC校验值发送给编码器，然后通过输出通道发送出去。 (1) Encoding process: After the host computer (HOST) gives instructions and information data to the OR1200 processor, the OR1200 processor sends a start command to the encoding module and the CRC check module, and the encoding module will return one to the OR1200 processor after receiving the start command. After the response signal, the OR1200 processor will transmit the data information to the encoding module and the CRC verification module. When the encoded data is completed, the generated CRC check value is sent to the encoder, and then sent out through the output channel. the

(2)解码过程：OR1200处理器检测到电子标签发送过来的信息后，会分别发送给解码模块和CRC校验模块启动指令，解码模块接收到启动指令后会返还给OR1200处理器一个应答信号，随之，解码数据信息完成后，会将数据信息及校验值发送给OR1200处理器，数据信息经过OR1200处理器一定处理后，会将结果送往计算机主机(HOST)，LCD显示器或存储器。 (2) Decoding process: After the OR1200 processor detects the information sent by the electronic tag, it will send the start command to the decoding module and the CRC verification module respectively. After receiving the start command, the decoding module will return a response signal to the OR1200 processor. Then, after decoding the data information, the data information and check value will be sent to the OR1200 processor. After the data information is processed by the OR1200 processor, the result will be sent to the host computer (HOST), LCD display or memory. the

本发明的超高频RFID读写器基带处理SOC芯片的工作过程分为启动过程和正常工作过程。其中启动过程的流程如图5所示： The working process of the UHF RFID reader-writer baseband processing SOC chip of the present invention is divided into a starting process and a normal working process. The flow of the startup process is shown in Figure 5:

上电之后，首先完成CPU OR1200和各功能模块的复位功能，然后从固定地址开始读取并执行系统初始化(Bootloader)程序，完成对各功能模块(包括：时钟模块、中断和电源管理模块、存储器控制模块、LCD控制模块和触摸屏控制模块、多协议处理单元模块和AD/DA控制模块、DMA控制模块、各种通信接口模块等)的参数配置，并在LCD上输出初始化界面。从指定位置程序存储器读取用户程序，显示用户界面。加载本地数据库管理程序。从I/Q通道DAC输出载波输出信号，并使输出信号强度最大(即P通道ADC输出最大)，打开I/Q通道ADC，启动多协议处理模块，检查是否有标签存在。如果有标签则显示标签数据，并将其信息计入数据库。如果没有标签，则连续发射载波并读取ADC通道数据，如果连续5s钟都没有标签响应数据则转入低功耗模式，至此，启动过程完毕。 After power on, first complete the reset function of the CPU OR1200 and each functional module, then read and execute the system initialization (Bootloader) program from a fixed address, and complete the reset of each functional module (including: clock module, interrupt and power management module, memory Control module, LCD control module and touch screen control module, multi-protocol processing unit module and AD/DA control module, DMA control module, various communication interface modules, etc.), and output initialization interface on LCD. Read the user program from the specified location program memory and display the user interface. Load the local database management program. Output the carrier output signal from the I/Q channel DAC, and maximize the output signal strength (that is, the P channel ADC output is the maximum), turn on the I/Q channel ADC, start the multi-protocol processing module, and check whether there is a tag. If there is a label, the label data is displayed, and its information is counted into the database. If there is no tag, the carrier will be continuously transmitted and the ADC channel data will be read. If there is no tag response data for 5 seconds, it will enter the low power consumption mode. So far, the startup process is complete. the

在正常工作过程中，由应用程序调用读写器操作程序完成标签数据的读写，和上位机的数据交互和数据库同步、多媒体播放以及其它的用户指定功能，具体操作内容与用户应用程序有关。 In the normal working process, the application program calls the reader operating program to complete the reading and writing of tag data, data interaction with the host computer, database synchronization, multimedia playback and other user-specified functions. The specific operation content is related to the user application program. the

Claims (8)

1. a multi-protocol UHF rfid interrogator baseband signal processing SOC chip comprises CPU module, bus on chip, memory interface, DAC output channel, ADC input channel, UHF RFID hardware multi-protocols processing unit, man-machine interface, high-speed communication interface, low-speed communication interface, timer module, jtag interface module and major clock module; It is characterized in that: bus on chip comprises high speed system bus and low speed peripheral bus, links together by dma controller and bus bridge between two buses, and every bus all is provided with address decoder and bus arbiter; CPU module, memory interface, man-machine interface, UHF RFID hardware multi-protocols processing unit, jtag interface module and high-speed communication interface all are connected with high speed system bus; Low-speed communication interface, timer module and major clock module are connected with the low speed peripheral bus; High-speed communication interface, DAC output channel and ADC input channel are connected with dma controller; In the CPU module, include the low power consumption control module.

2. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1, it is characterized in that, described DAC output channel comprises 3 tunnel 8 DAC output channels, wherein 2 the tunnel are used for I passage and the Q passage baseband digital signal that output orthogonal is modulated needs, and other 1 tunnel 8 P passage DAC output channel is exported as the gain adjustment of power amplifier PA.

3. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that, described ADC input channel comprises 2 tunnel 8 ADC input channels, is used to import the I passage after the quadrature demodulation and the baseband digital signal of Q passage.

4. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1, it is characterized in that described UHF RFID hardware multi-protocols processing unit: comprise coding module, decoder module, CRC check module and clock frequency division module four parts.

5. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that described man-machine interface comprises lcd controller and touch screen controller.

6. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that described high-speed communication interface disposes 32 GPIO interfaces, pci bus interface and USB1.1 interface controller.

7. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that described low-speed communication interface configuration has UART interface, SPI interface module and IIS Audio Controller.

8. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that, described timer module disposes 2 16 bit timing counter timers and real-time clock.

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