CN101888181A - Feedback Based Charge Pump Circuit - Google Patents

Abstract

Translated fromChinese

本发明涉及一种电荷泵电路，它包括一个高压产生单元、一个降压单元和一个反馈控制单元。本发明在传统电荷泵电路基础上增加了一个降压单元和一个反馈控制单元，高压产生单元的电荷泵增益与MOS管阈值电压无关，使增压效率提高了20％以上；电荷泵采用两个充电通路交替向负载充电的方式，使电荷泵充电速度提高到2倍以上，电荷泵采用反馈方式得到一定范围内的连续输出电压值，且输出电压值大于电源电压。本发明兼具增压效率高、充电速度快、输出电压值连续的优点，有效地克服了传统电荷泵电路增压效率低、充电速度慢、输出电压值离散的缺点。本发明可广泛应用于数模混合电路领域。

The invention relates to a charge pump circuit, which includes a high-voltage generating unit, a step-down unit and a feedback control unit. The present invention adds a step-down unit and a feedback control unit on the basis of the traditional charge pump circuit. The charge pump gain of the high-voltage generation unit has nothing to do with the threshold voltage of the MOS tube, which increases the boosting efficiency by more than 20%. The charge pump adopts two The way that the charging path alternately charges the load increases the charging speed of the charge pump to more than 2 times. The charge pump adopts a feedback method to obtain a continuous output voltage value within a certain range, and the output voltage value is greater than the power supply voltage. The invention has the advantages of high boosting efficiency, fast charging speed and continuous output voltage value, and effectively overcomes the shortcomings of low boosting efficiency, slow charging speed and discrete output voltage value of the traditional charge pump circuit. The invention can be widely used in the field of digital-analog hybrid circuits.

Description

Translated fromChinese

基于反馈的电荷泵电路Feedback Based Charge Pump Circuit

技术领域technical field

本发明涉及一种电荷泵电路，特别涉及一种基于反馈的电荷泵电路。它直接应用的领域是大于电源电压的高电压驱动的数字模拟混合电路。The invention relates to a charge pump circuit, in particular to a charge pump circuit based on feedback. Its direct application field is a digital-analog hybrid circuit driven by a high voltage greater than the power supply voltage.

背景技术Background technique

在数字模拟混合电路中，随着电源电压的进一步降低，一些模拟开关在正常的电源电压范围内不能充分导通，甚至不导通。因此，需要有能够产生高电压(大于电源电压)的电荷泵电路，用于驱动有高电压需求的模拟开关。In the digital-analog hybrid circuit, with the further reduction of the power supply voltage, some analog switches cannot be fully turned on or even not turned on in the normal power supply voltage range. Therefore, there is a need for a charge pump circuit capable of generating a high voltage (greater than the supply voltage) for driving an analog switch with a high voltage requirement.

目前，传统的电荷泵电路是基于Dickson提出的电荷泵电路，这类电荷泵电路的增益为：At present, the traditional charge pump circuit is based on the charge pump circuit proposed by Dickson. The gain of this type of charge pump circuit is:

$\mathrm{<span><span>\&Delta;V</span>\&Delta;V</span>}<span><span>=</span>=</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>DD</span>DD</span>}}<span><span>\&times;</span>\&times;</span>\frac{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>pump</span>the\; pump</span>}}}{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>pump</span>the\; pump</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>parasitic</span>parasitic</span>}}}<span><span>-</span>-</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>thn</span>thn</span>}}<span><span>-</span>-</span><span><span>-</span>-</span><span><span>-</span>-</span><span><span>(</span>(</span>\mathrm{<span><span>1</span>1</span>}<span><span>)</span>)</span>$

电荷泵增益为每个电荷泵级增加的电压值，式中，ΔV为电荷泵增益，V_DD为泵节点的电压变化(此时等于电源电压)，C_pump为泵电容，C_parasitic为寄生电容，V_thn为NMOS晶体管的阈值电压。The charge pump gain is the voltage value added by each charge pump stage. In the formula, ΔV is the charge pump gain, V_DD is the voltage change of the pump node (equal to the power supply voltage at this time), C_pump is the pump capacitance, and C_parasitic is the parasitic capacitance , V_thn is the threshold voltage of the NMOS transistor.

电荷泵电路的输出电压为：The output voltage of the charge pump circuit is:

V_OUT＝V_DD+n·ΔV           (2)V_OUT =V_DD +n·ΔV (2)

式中，V_OUT为输出电压，n为电荷泵的级数。In the formula, V_OUT is the output voltage, and n is the number of stages of the charge pump.

由(1)式可知，电荷泵增益是泵节点的电压变化分压减去NMOS管的阈值电压的差值，若采用的V_DD为3.3V，V_thn为0.8V，C_pump远大于C_parasitic，则电荷泵增益仅为泵节点电压变化的75％左右，因此传统的电荷泵电路的增压效率不高；由(2)式可知，增大或减小V_OUT只能增加或减小电荷泵的级数n，由于V_OUT只能增大或减小ΔV的整数倍，导致传统电荷泵电路的输出电压不能连续调节；另外，传统电荷泵电路是以单通道方式向负载充电，因此，充电速度也较慢。It can be known from formula (1) that the charge pump gain is the difference between the voltage change of the pump node and the threshold voltage of the NMOS transistor. If V_DD is 3.3V and V_thn is 0.8V, C_pump is much larger than C_parasitic , then the charge pump gain is only about 75% of the change in the pump node voltage, so the boosting efficiency of the traditional charge pump circuit is not high; it can be seen from (2) that increasing or decreasing V_OUT can only increase or decrease the charge The number of stages n of the pump, because V_OUT can only increase or decrease an integer multiple of ΔV, the output voltage of the traditional charge pump circuit cannot be continuously adjusted; in addition, the traditional charge pump circuit charges the load in a single channel, therefore, Charging is also slower.

发明内容Contents of the invention

为克服传统电荷泵电路的增压效率不高、输出电压不能连续调节、充电速度慢的问题，本发明提供一种能够提供高电压(大于电源电压)的基于反馈的电荷泵电路。In order to overcome the problems of low boosting efficiency, non-continuous adjustment of output voltage and slow charging speed of traditional charge pump circuits, the present invention provides a feedback-based charge pump circuit capable of providing high voltage (greater than power supply voltage).

为实现上述目的，本发明解决上述技术问题所采取的技术方案在于：一种基于反馈的电荷泵电路，它含有：In order to achieve the above object, the technical solution adopted by the present invention to solve the above technical problem is: a charge pump circuit based on feedback, which contains:

一个高电压产生单元，包括：A high voltage generating unit comprising:

PMOS管P₁～P₅、NMOS管N₁～N₈、电容C₁～C₄，其中，P₁的栅极接此高电压产生单元的输入端V_J，P₁的源极接电源V_DD，P₁的漏极与P₂的源极及衬底、P₃的源极及衬底相接，并与C₁的上极板连接在一起，C₁的下极板接地V_SS，P₂、N₁的栅极接第一时钟端CLK₁，P₃、N₂的栅极接第二时钟端CLK₂，P₂、N₁的漏极与C₃的下极板相接，P₃、N₂的漏极与C₂的下极板相接，N₁、N₂的源极接地V_SS，N₃的源极与N₅的源极、N₆的栅极、P₄的栅极、P₅的漏极、N₈的漏极相接，并与C₂的上极板连接在一起，N₄的源极与N₆的源极、N₅的栅极、P₅的栅极、P₄的漏极、N₇的漏极相接，并与C₃的上极板连接在一起，N₃的栅极、N₃的漏极、N₄的栅极、N4的漏极、N₅的漏极、N₆的漏极都接电源V_DD，N₇的栅极接第二时钟端CLK₂，N₈的栅极接第一时钟端CLK₁，N₇的源极与P₄的源极、P₄的衬底、P₅的源极、P₅的衬底、N₈的源极相接，并与C₄的上极板连接在一起，其连接点为此高电压产生单元的输出端，即整个电荷泵电路的输出端V_OUT，C₄的下极板接地V_SS；和PMOS transistors P₁ to P₅ , NMOS transistors N₁ to N₈ , and capacitors C₁ to C₄ , where the gate of P₁ is connected to the input terminal V_J of the high voltage generating unit, and the source of P₁ is connected to the power supply V_DD , the drain of P₁ is connected to the source and substrate of P₂ , the source and substrate of P₃ , and connected to the upper plate of C₁ , the lower plate of C₁ is grounded V_SS , The gates of P₂ and N₁ are connected to the first clock terminal CLK₁ , the gates of P₃ and N₂ are connected to the second clock terminal CLK₂ , the drains of P₂ and N₁ are connected to the lower plate of C₃ , The drains of P₃ and N₂ are connected to the lower plate of C₂ , the sources of N₁ and N₂ are grounded to V_SS , the source of N₃ is connected to the source of N₅ , the gate of N₆ , and the gate of P₄ The gate of N4, the drain of_P5 , and the drain of_N8 are connected together, and connected with the upper plate of_C2 , the source of_N4 is connected with the source of_N6 , the gate of_N5 ,_P5 The gate of_P4 , the drain of_N7 , and the upper plate of_C3 are connected together, the gate of_N3 , the drain of_N3 , the gate of_N4 , the gate of N4 The drain, the drain of N₅ and the drain of N₆ are all connected to the power supply V_DD , the gate of N₇ is connected to the second clock terminal CLK₂ , the gate of N₈ is connected to the first clock terminal CLK₁ , and the source of N₇ The pole is connected to the source of_P4 , the substrate of_P4 , the source of_P5 , the substrate of_P5 , and the source of_N8 , and is connected with the upper plate of_C4 , and its connection point is The output terminal of this high voltage generating unit, that is, the output terminal V_OUT of the entire charge pump circuit, the lower plate of C₄ is grounded V_SS ; and

一个降压单元，包括：A step-down unit consisting of:

PMOS管P₆～P₇、NMOS管N₉～N₁₄、电容C₅～C₇，其中，N₉的源极、P₆的源极、P₆的衬底、P₇的源极、P₇的衬底、N₁₀的源极都与此降压单元的输入端，即高压产生单元的输出端V_OUT相接，N₉的漏极与P₆的漏极、N₁₁的漏极、N₁₂的漏极、P₇的栅极、N₁₃的栅极相接，并与C₅的上极板连接在一起，N₁₀的漏极与P₇的漏极、N₁₃的漏极、N₁₄的漏极、P₆的栅极、N₁₂的栅极相接，并与C₆的上极板连接在一起，N₉的栅极与C₅的下极板、N₁₄的栅极与第二时钟端CLK₂相接，N₁₀的栅极、C₆的下极板、N₁₁的栅极与第一时钟端CLK₁相接，N₁₁的源极与N₁₂的源极、N₁₃的源极、N₁₄的源极相接，并与C₇的上极板连接在一起，其连接点为此降压单元的输出端V_FB，C₇的下极板接地V_SS；和PMOS transistors P₆ to P₇ , NMOS transistors N₉ to N₁₄ , and capacitors C₅ to C₇ , among which, the source of N₉ , the source of P₆ , the substrate of P₆ , the source of P₇ , and the The substrate of₇ and the source of N₁₀ are all connected to the input end of the step-down unit, that is, the output end V_OUT of the high-voltage generating unit, and the drain of N₉ is connected to the drain of P₆ , the drain of N₁₁ , The drain of N₁₂ , the gate of P₇ , and the gate of N₁₃ are connected, and connected with the upper plate of C₅ , the drain of N₁₀ is connected with the drain of P₇ , the drain of N₁₃ , The drain of N₁₄ , the gate of P₆ , and the gate of N₁₂ are connected, and connected with the upper plate of C₆ , the gate of N₉ is connected with the lower plate of C₅ , and the gate of N₁₄ It is connected to the second clock terminal CLK₂ , the gate of N₁₀ , the lower plate of C₆ , the gate of N₁₁ is connected to the first clock terminal CLK₁ , the source of N₁₁ is connected to the source of N₁₂ , The source of N₁₃ and the source of N₁₄ are connected, and connected together with the upper plate of C₇ , the connection point is the output terminal V_FB of the step-down unit, and the lower plate of C₇ is grounded V_SS ; and

一个反馈控制单元，包括：A feedback control unit comprising:

PMOS管P₈～P₉、NMOS管N₁₅～N₁₈，其中，P₈的源极、P₉的源极接电源V_DD，P₈的栅极及漏极、P₉的栅极与N₅的漏极相接，P₉的漏极与N₁₆的漏极相接，其接点为此反馈控制单元的输出端V_J，即高压产生单元的输入端V_J，N₁₅的栅极接此反馈控制单元的输入端，即降压单元的输出端V_FB，N₁₆的栅极接此反馈控制单元的输入V_REF，N₁₅的源极、N₁₆的源极与N₁₇的漏极相接，N₁₇的栅极、N₁₈的栅极、N₁₈的漏极都与此反馈控制单元的输入端I_BIAS相接，N₁₇的源极、N₁₈的源极均接地V_SS。PMOS transistors P₈ to P₉ , NMOS transistors N₁₅ to N₁₈ , wherein the source of P₈ and the source of P₉ are connected to the power supply V_DD , the gate and drain of P₈ , the gate of P₉ are connected to the N The drain of P₉ is connected to the drain of N₁₆ , and its contact point is the output terminal V_J of the feedback control unit, that is, the_input terminal V_J of the high-voltage generating unit, and the gate of N₁₅ is connected to The input terminal of this feedback control unit, that is, the output terminal V_FB of the step-down unit, the gate of_N16 is connected to the input V_REF of this feedback control unit, the source of_N15 , the source of_N16 and the drain of_N17 The gate of N₁₇ , the gate of N₁₈ , and the drain of N₁₈ are all connected to the input terminal I_BIAS of the feedback control unit, and the source of N₁₇ and N₁₈ are both grounded to V_SS .

所述电荷泵电路能够产生连续变化的输出电压值，且输出电压大于电源电压。The charge pump circuit can generate a continuously variable output voltage value, and the output voltage is greater than the power supply voltage.

所述电荷泵电路能够利用反馈功能来调节电荷泵的输出电压，使输出电压随输入电压的变化而变化。The charge pump circuit can use the feedback function to adjust the output voltage of the charge pump, so that the output voltage changes with the change of the input voltage.

所述电荷泵电路的电荷泵增益与MOS管的阈值电压无关。The charge pump gain of the charge pump circuit has nothing to do with the threshold voltage of the MOS tube.

所述电荷泵电路包含两个充电通路，在时钟的控制下，交替向负载充电。The charge pump circuit includes two charging paths, which alternately charge the load under the control of the clock.

有益效果：Beneficial effect:

本发明的基于反馈的电荷泵电路包括一个高电压产生单元、一个降压单元和一个反馈控制单元，与传统电荷泵电路相比，它具有以下特点：The charge pump circuit based on feedback of the present invention includes a high voltage generation unit, a step-down unit and a feedback control unit, compared with the traditional charge pump circuit, it has the following characteristics:

1.传统电荷泵电路只包含一个高压产生单元，而本发明的电荷泵电路在传统电荷泵电路基础上增加了一个降压单元和一个反馈控制单元，充分利用反馈的功能来调节电荷泵的输出电压。1. The traditional charge pump circuit only includes a high-voltage generating unit, but the charge pump circuit of the present invention adds a step-down unit and a feedback control unit on the basis of the traditional charge pump circuit, and makes full use of the feedback function to adjust the output of the charge pump Voltage.

2.传统电荷泵电路的电荷泵增益受阈值电压影响，导致其增压效率低，而本发明的电荷泵电路，其电荷泵增益与MOS管的阈值电压无关，能使增压效率提高20％以上。2. The charge pump gain of the traditional charge pump circuit is affected by the threshold voltage, resulting in low boosting efficiency, while the charge pump circuit of the present invention has nothing to do with the threshold voltage of the MOS tube, which can increase the boosting efficiency by 20% above.

3.传统电荷泵电路仅有一个充电通路，在时钟控制下，泵电容需要半个时钟周期预充电，再用半个时钟周期向负载充电，因此充电速度较慢，而本发明的电荷泵电路采用两个充电通路，交替向负载充电方式，使泵电容在整个时钟周期内都在向负载充电，再加上增压效率的提高，因此充电速度提高到两倍以上。3. The traditional charge pump circuit has only one charging path. Under clock control, the pump capacitor needs half a clock cycle to precharge, and then uses half a clock cycle to charge the load, so the charging speed is relatively slow, while the charge pump circuit of the present invention Two charging channels are used to charge the load alternately, so that the pump capacitor is charging the load during the entire clock cycle. In addition, the boosting efficiency is improved, so the charging speed is more than doubled.

4.传统电荷泵电路中，改变输出电压值通过改变电荷泵的级数实现，每级电荷泵增益固定，只能得到一些离散的电压值，因此其输出电压值不连续，而本发明的电荷泵电路，通过连续改变反馈控制单元的输入电压即可实现电荷泵输出电压的连续调节，因此可以得到一定范围内的任意输出电压值。4. In the traditional charge pump circuit, changing the output voltage value is achieved by changing the number of stages of the charge pump. The gain of each stage charge pump is fixed, and only some discrete voltage values can be obtained, so the output voltage value is discontinuous, and the charge pump of the present invention The pump circuit can continuously adjust the output voltage of the charge pump by continuously changing the input voltage of the feedback control unit, so any output voltage value within a certain range can be obtained.

综上所述，本发明的基于反馈的电荷泵电路同时具增压效率高、充电速度快、输出电压值连续的优点，有效克服了传统电荷泵电路的增压效率低、输出电压值离散、充电速度慢的缺点。In summary, the feedback-based charge pump circuit of the present invention has the advantages of high boosting efficiency, fast charging speed, and continuous output voltage value at the same time, effectively overcoming the low boosting efficiency, discrete output voltage value, and The disadvantage of slow charging.

附图说明Description of drawings

图1是本发明的基于反馈的电荷泵电路的总体电路框图；Fig. 1 is the general circuit block diagram of the charge pump circuit based on feedback of the present invention;

图2是本发明图1中的高电压产生单元的电路图；Fig. 2 is the circuit diagram of the high voltage generating unit in Fig. 1 of the present invention;

图3是本发明图1中的降压单元的电路图；Fig. 3 is a circuit diagram of the step-down unit in Fig. 1 of the present invention;

图4是本发明图1中的反馈控制单元的电路图。FIG. 4 is a circuit diagram of the feedback control unit in FIG. 1 of the present invention.

具体实施方式Detailed ways

本发明的具体实施方式不仅限于下面的描述，现结合附图加以进一步说明。The specific implementation manners of the present invention are not limited to the following description, and are now further described in conjunction with the accompanying drawings.

本发明具体实施的一种基于反馈的电荷泵电路总体结构如图1所示。它由一个高压产生单元、一个降压单元和一个反馈控制单元组成。其中，高压产生单元的电路图如图2所示，包括：PMOS管P₁～P₅、NMOS管N₁～N₈、电容C₁～C₄，高压产生单元用于产生大于电源电压的高电压。降压单元的电路图如图3所示，包括：PMOS管P₆～P₇、NMOS管N₉～N₁₄、电容C₅～C₇，降压单元将高电压降低到电源电压范围内，以便于反馈控制单元进行比较反馈。反馈控制单元的电路图如图4所示，包括PMOS管P₈～P₉、NMOS管N₁₅～N₁₈，反馈控制单元将输出电压经降压后的值与输入电压进行比较，比较的结果用于控制高压产生电路，实现对电荷泵电路输出高电压的反馈控制。The overall structure of a feedback-based charge pump circuit implemented in the present invention is shown in FIG. 1 . It consists of a high-voltage generating unit, a step-down unit and a feedback control unit. Among them, the circuit diagram of the high-voltage generating unit is shown in Figure 2, including: PMOS transistors P₁ to P₅ , NMOS transistors N₁ to N₈ , capacitors C₁ to C₄ , and the high-voltage generating unit is used to generate a high voltage greater than the power supply voltage . The circuit diagram of the step-down unit is shown in Figure 3, including: PMOS transistors P₆ to P₇ , NMOS transistors N₉ to N₁₄ , capacitors C₅ to C₇ , and the step-down unit reduces the high voltage to the power supply voltage range, so that The comparative feedback is carried out in the feedback control unit. The circuit diagram of the feedback control unit is shown in Figure 4, including PMOS transistors P₈ to P₉ and NMOS transistors N₁₅ to N₁₈ . The feedback control unit compares the output voltage after step-down with the input voltage, and the comparison result is used It is used to control the high-voltage generating circuit and realize the feedback control of the output high voltage of the charge pump circuit.

图2中的具体连接关系与本说明书的发明内容部分相同，此处不再重复。它的工作原理如下：The specific connection relationship in FIG. 2 is the same as the content of the invention in this specification, and will not be repeated here. It works like this:

时钟CLK₁和CLK₂为两相非交叠时钟，当CLK₁为高电平、CLK₂为低电平时，N₁导通，C₃底极板接地，N₄或N₆为C₃充电(初态时N₄为C₃充电，稳态时，N₆为C₃充电)，稳态时C₃上极板充电到V_DD  当CLK₁为低电平、CLK₂为高电平时，P₂导通，C₃底极板与C₁上极板相连(C₁上极板电压稳态时为V₁)，因此由C₃上极板节点电荷守恒，可得稳态时C₃上极板电压被举高到：Clocks CLK₁ and CLK₂ are two-phase non-overlapping clocks. When CLK₁ is high and CLK₂ is low, N₁ is turned on, the bottom plate of C₃ is grounded, and N₄ or N₆ charges C₃ (N₄ charges C₃ in the initial state, and N₆ charges C₃ in the steady state). In the steady state, the upper plate of C₃ is charged to V_DD . When CLK₁ is low and CLK₂ is high, P₂ is turned on, and the bottom plate of C₃ is connected to the upper plate of C₁ (the voltage of the upper plate of C₁ is V₁ in a steady state), so the charge conservation of the upper plate node of C₃ can get C₃ in a steady state The upper plate voltage is raised to:

${\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>3</span>3</span>}}<span><span>=</span>=</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>1</span>1</span>}}<span><span>\&times;</span>\&times;</span>\frac{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>3</span>3</span>}}}{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>3</span>3</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>p</span>p</span>}\mathrm{<span><span>3</span>3</span>}}}<span><span>+</span>+</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>DD</span>DD</span>}}<span><span>-</span>-</span><span><span>-</span>-</span><span><span>-</span>-</span><span><span>(</span>(</span>\mathrm{<span><span>3</span>3</span>}<span><span>)</span>)</span>$

式中，C_P3为C₃上极板节点的寄生电容。In the formula, C_P3 is the parasitic capacitance of the plate node on C₃ .

同理，当CLK₁为低电平、CLK₂为高电平时，稳态时C₂上极板充电到V_DD；当CLK₁为高电平、CLK₂为低电平时，稳态时C₂上极板电压被举高到：Similarly, when CLK₁ is low level and CLK₂ is high level, the upper plate of C₂ is charged to V_DD in steady state; when CLK₁ is high level and CLK₂ is low level, C₂ The upper plate voltage is raised to:

${\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>2</span>2</span>}}<span><span>=</span>=</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>1</span>1</span>}}<span><span>\&times;</span>\&times;</span>\frac{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>2</span>2</span>}}}{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>2</span>2</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>p</span>p</span>}\mathrm{<span><span>2</span>2</span>}}}<span><span>+</span>+</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>DD</span>DD</span>}}<span><span>-</span>-</span><span><span>-</span>-</span><span><span>-</span>-</span><span><span>(</span>(</span>\mathrm{<span><span>4</span>4</span>}<span><span>)</span>)</span>$

式中，C_P2为C₂上极板节点的寄生电容。In the formula, C_P2 is the parasitic capacitance of the plate node on C₂ .

由于电路采用对称设计，因此Due to the symmetrical design of the circuit, the

C₂＝C₃＝C_2，3                (5)C₂ =C₃ =C_2,3 (5)

C_p2＝C_p3＝C_p2，3             (6)C_p2 =C_p3 =C_p2,3 (6)

有(3)～(6)式可得：There are formulas (3)~(6) to get:

V₃＝V₂＝V_DD+ΔV₁             (7)V₃ =V₂ =V_DD +ΔV₁ (7)

其中，${\mathrm{\&Delta;V}}_1=V_1\&times;\frac{C_3}{C_3+C_{p3}}=V_1\&times;\frac{C_2}{C_2+C_{p2}}=V_1\&times;\frac{C_{\mathrm{2,3}}}{C_{\mathrm{2,3}}+C_{p\mathrm{2,3}}}---\left(8\right)$in,${\mathrm{\&Delta;V}}_1=V_1\&times;\frac{C_3}{C_3+C_{p3}}=V_1\&times;\frac{C_2}{C_2+C_{p2}}=V_1\&times;\frac{C_{\mathrm{2,3}}}{C_{\mathrm{2,3}}+C_{p\mathrm{2,3}}}---\left(8\right)$

若like

ΔV₁＞|V_thp|                 (9)ΔV₁ > |V_thp | (9)

式中，V_thp为PMOS晶体管的阈值电压。Where, V_thp is the threshold voltage of the PMOS transistor.

当CLK₁为高电平、CLK₂为低电平时，初态时，P₄、P₅、N₇截止，N₈导通，C₂向C₄充电；稳态时，由于C₂上极板电压被举高到(V_DD+ΔV₁)，C₃上极板电压为V_DD，由(9)式可知，P₄、N₇、N₈截止，P₅导通，C₂将C₄上极板充电到(V_DD+ΔV₁)。当CLK₁为低电平、CLK₂为高电平时，初态时，P₄、P₅、N₈截止，N₇导通，C₃向C₄充电；稳态时，由于C₃上极板电压被举高到(V_DD+ΔV₁)，C₂上极板电压为V_DD，由(9)式可知，P₅、N₇、N₈截止，P₄导通，C₃将C₄上极板充电到(V_DD+ΔV₁)。可见，在时钟CLK₁和CLK₂的控制下，C₂和C₃交替的向C₄充电，最终使C₄上极板电压，即输出电压达到以下稳定值：When CLK₁ is at high level and CLK₂ is at low level, in the initial state, P₄ , P₅ , and N₇ are turned off, N₈ is turned on, and C₂ charges to C₄ ; in steady state, due to the upper pole of C₂ The plate voltage is raised to (V_DD +ΔV₁ ), and the plate voltage on C₃ is V_DD . It can be seen from formula (9) that P₄ , N₇ , and N₈ are cut off, P₅ is turned on, and C₂ turns C₄ The upper plate is charged to (V_DD +ΔV₁ ). When CLK₁ is at low level and CLK₂ is at high level, in the initial state, P₄ , P₅ , and N₈ are turned off, N₇ is turned on, and C₃ charges to C₄ ; in steady state, due to the upper pole of C₃ The plate voltage is raised to (V_DD +ΔV₁ ), and the plate voltage on C₂ is V_DD . It can be seen from formula (9) that P₅ , N₇ , and N₈ are off, P₄ is on, and C₃ turns C₄ The upper plate is charged to (V_DD +ΔV₁ ). It can be seen that under the control of clock CLK₁ and CLK₂ , C₂ and C₃ charge C₄ alternately, and finally make the upper plate voltage of C₄ , that is, the output voltage reach the following stable value:

V_OUT＝V_DD+ΔV₁                 (10)V_OUT =V_DD +ΔV₁ (10)

图3中的具体连接关系与本说明书的发明内容部分相同，此处不再重复。它的工作原理如下：The specific connection relationship in FIG. 3 is the same as the content of the invention in this specification, and will not be repeated here. It works like this:

当CLK₁为高电平、CLK₂为低电平时，初态时，P₆、P₇、N₉截止，N₁₀导通，V_OUT向C₆充电，N₁₂、N₁₃、N₁₄截止，N₁₁导通，C₅向C₇充电；稳态时，P₆、N₉、N₁₀截止，P₇导通，N₁₁、N₁₃、N₁₄截止，N₁₂导通。此时，C₆上极板电压为V_OUT，由C₅上极板节点电荷守恒，可得C₅上极板电压为：When CLK₁ is at high level and CLK₂ is at low level, in the initial state, P₆ , P₇ , and N₉ are off, N₁₀ is on, V_OUT charges C₆ , and N₁₂ , N₁₃ , and N₁₄ are off , N₁₁ is turned on, C₅ charges C₇ ; in steady state, P₆ , N₉ , N₁₀ are turned off, P₇ is turned on, N₁₁ , N₁₃ , N₁₄ are turned off, and N₁₂ is turned on. At this time, the voltage of the upper plate of C₆ is V_OUT , and the charge conservation of the node of the upper plate of C₅ can obtain the voltage of the upper plate of C₅ as:

${\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>5</span>5</span>}}<span><span>=</span>=</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>OUT</span>out</span>}}<span><span>-</span>-</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>DD</span>DD</span>}}<span><span>\&times;</span>\&times;</span>\frac{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>5</span>5</span>}}}{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>5</span>5</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>p</span>p</span>}\mathrm{<span><span>5</span>5</span>}}}<span><span>-</span>-</span><span><span>-</span>-</span><span><span>-</span>-</span><span><span>(</span>(</span>\mathrm{<span><span>11</span>11</span>}<span><span>)</span>)</span>$

式中，C_P5为C₅上极板节点的寄生电容，此时，C₅将C₇上极板充电到V₅。In the formula, C_P5 is the parasitic capacitance of the upper plate node of C₅ , at this time, C₅ charges the upper plate of C₇ to V₅ .

当CLK₁为低电平、CLK₂为高电平时，初态时，P₆、P₇、N₁₀截止，N₉导通，V_OUT向C₅充电，N₁₁、N₁₂、N₁₃截止，N₁₄导通，C₆向C₇充电；稳态时，P₇、N₉、N₁₀截止，P₆导通，N₁₁、N₁₂、N₁₄截止，N₁₃导通。此时，C₅上极板电压为V_OUT，由C₆上极板节点电荷守恒，可得C₆上极板电压为：When CLK₁ is at low level and CLK₂ is at high level, in the initial state, P₆ , P₇ , and N₁₀ are off, N₉ is on, V_OUT charges C₅ , and N₁₁ , N₁₂ , and N₁₃ are off , N₁₄ is turned on, C₆ charges to C₇ ; in steady state, P₇ , N₉ , N₁₀ are turned off, P₆ is turned on, N₁₁ , N₁₂ , N₁₄ are turned off, and N₁₃ is turned on. At this time, the voltage of the upper plate of C₅ is V_OUT , and the charge conservation of the upper plate node of C₆ can obtain the voltage of the upper plate of C₆ as:

${\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>6</span>6</span>}}<span><span>=</span>=</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>OUT</span>out</span>}}<span><span>-</span>-</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>DD</span>DD</span>}}<span><span>\&times;</span>\&times;</span>\frac{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>6</span>6</span>}}}{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>6</span>6</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>p</span>p</span>}\mathrm{<span><span>6</span>6</span>}}}<span><span>-</span>-</span><span><span>-</span>-</span><span><span>-</span>-</span><span><span>(</span>(</span>\mathrm{<span><span>12</span>12</span>}<span><span>)</span>)</span>$

式中，C_P6为C₆上极板节点的寄生电容，此时，C₆将C₇上极板充电到V₆。In the formula, C_P6 is the parasitic capacitance of the upper plate node of C₆ , at this time, C₆ charges the upper plate of C₇ to V₆ .

由于电路采用对称设计，因此有：Since the circuit is designed symmetrically, there are:

C₅＝C₆＝C_5，6            (13)C₅ =C₆ =C_5,6 (13)

C_p5＝C_p6＝C_p5，6         (14)C_p5 =C_p6 =C_p5,6 (14)

由(11)～(14)式，可得：From formulas (11) to (14), we can get:

V₅＝V₆＝V_OUT-ΔV₂        (15)V₅ =V₆ =V_OUT -ΔV₂ (15)

式中，${\mathrm{\&Delta;V}}_2=V_{\mathrm{DD}}\&times;\frac{C_5}{C_5+C_{p5}}=V_{\mathrm{DD}}\&times;\frac{C_6}{C_6+C_{p6}}=V_{\mathrm{DD}}\&times;\frac{C_{\mathrm{5,6}}}{C_{\mathrm{5,6}}+C_{p\mathrm{5,6}}}---\left(16\right)$In the formula,${\mathrm{\&Delta;V}}_2=V_{\mathrm{DD}}\&times;\frac{C_5}{C_5+C_{p5}}=V_{\mathrm{DD}}\&times;\frac{C_6}{C_6+C_{p6}}=V_{\mathrm{DD}}\&times;\frac{C_{\mathrm{5,6}}}{C_{\mathrm{5,6}}+C_{p\mathrm{5,6}}}---\left(16\right)$

可见，C₅与C₆在时钟控制下，交替的被V_OUT充电，并向C₇充电，得到V_OUT经降压后的值：It can be seen that under clock control, C₅ and C₆ are alternately charged by V_OUT and charged to C₇ to obtain the value of V_OUT after step-down:

V_FB＝V₅＝V₆＝V_OUT-ΔV₂            (17)V_FB ＝V₅ ＝V₆ ＝V_OUT -ΔV₂ (17)

图4中的具体连接关系与本说明书的发明内容部分相同，此处不再重复。它的工作原理如下：The specific connection relationship in FIG. 4 is the same as the content of the invention in this specification, and will not be repeated here. It works like this:

I_BIAS为偏置电流输入端，通过N₁₈向N₁₇的镜像，为运放提供偏置，V_REF为输入电压。当V_FB小于V_REF时，V_J减小，使图2中V₁升高，由(8)和(10)式可知，稳态时，V_OUT将升高；当V_FB大于V_REF时，V_J增大，使图2中V₁降低，由(8)和式(10)式可知，稳态时V_OUT将降低；直到V_FB等于V_REF时，V_OUT达到稳态平衡，由(16)和(17)式可知，此时，I_BIAS is the input terminal of the bias current, through the mirror image of N₁₈ to N₁₇ , it provides bias for the operational amplifier, and V_REF is the input voltage. When V_FB is less than V_REF , V_J decreases, which increases V₁ in Figure 2. It can be seen from (8) and (10) that in steady state, V_OUT will increase; when V_FB is greater than V_REF , V_J increases, so that V₁ in Figure 2 decreases. It can be seen from (8) and (10) that V_OUT will decrease in the steady state; until V_FB is equal to V_REF , V_OUT will reach a steady state balance. (16) and (17), it can be seen that at this time,

${\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>OUT</span>out</span>}}<span><span>=</span>=</span>{\mathrm{<span><span>\&Delta;V</span>\&Delta;V</span>}}_{\mathrm{<span><span>2</span>2</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>FB</span>Facebook</span>}}<span><span>=</span>=</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>DD</span>DD</span>}}<span><span>\&times;</span>\&times;</span>\frac{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>5.6</span>5.6</span>}}}{{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>5.6</span>5.6</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>C</span>C</span>}}_{\mathrm{<span><span>p</span>p</span>}\mathrm{<span><span>5,6</span>5,6</span>}}}<span><span>+</span>+</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>REF</span>REF</span>}}<span><span>-</span>-</span><span><span>-</span>-</span><span><span>-</span>-</span><span><span>(</span>(</span>\mathrm{<span><span>18</span>18</span>}<span><span>)</span>)</span>$

综上所述，首先，对比(1)式和(8)式可知，电荷泵增益ΔV₁与NMOS管的阈值电压无关，且当泵节点的电压变化V₁＝V_DD时，本发明电路的电荷泵增益ΔV₁较之传统电荷泵电路的电荷泵增益ΔV，增大了一个阈值电压值V_thn，若C_2，3远大于C_p2，3，则电荷泵增益约为泵节点电压变化的100％；其次，由式(18)可知，由于引入了反馈，使得连续改变V_REF可使V_OUT随之连续改变，因此，本发明电路的电路结构避免了传统电荷泵电路的输出电压不能连续调节的问题；同时，本发明电路采用了双通路交替的方式，满时钟周期连续地向负载充电，再加上电荷泵增益的提高，充电速度提高到传统电荷泵电路的2倍以上。In summary, first of all, comparing formula (1) and formula (8), it can be seen that the charge pump gain ΔV₁ has nothing to do with the threshold voltage of the NMOS transistor, and when the voltage change of the pump node V₁ =V_DD , the circuit of the present invention Compared with the charge pump gain ΔV of the traditional charge pump circuit, the charge pump gain ΔV₁ increases a threshold voltage value V_thn , if C_2,3 is much larger than C_p2,3 , then the charge pump gain is about 100%; secondly, by the formula (18), it can be known that due to the introduction of feedback, continuously changing V_REF can make V_OUT continuously change thereupon, therefore, the circuit structure of the circuit of the present invention has avoided the output voltage of the traditional charge pump circuit can not be continuous The problem of regulation; at the same time, the circuit of the present invention adopts the dual-channel alternate mode, and the full clock cycle continuously charges the load, coupled with the improvement of the charge pump gain, the charging speed is increased to more than 2 times that of the traditional charge pump circuit.

另外，为了进一步提高工作速度，本发明的充放电通路上的MOS管，即P₂～P₇，N₁～N₁₄都采用最小的栅长。为实现对输出电压V_OUT的连续充电和连续采样反馈，使C₂、C₃对C₄的交替充电，C₅、C₆对V_OUT的交替采样和降压，本发明电路采用对称设计，即P₂、P₃几何尺寸完全相同，N₁、N₂几何尺寸完全相同，C₂、C₃几何尺寸完全相同，N₃、N₄几何尺寸完全相同，N₅、N₆几何尺寸完全相同，N₇、N₈几何尺寸完全相同，P₄、P₅几何尺寸完全相同，N₉、N₁₀几何尺寸完全相同，P₆、P₇几何尺寸完全相同，N₁₁、N₁₄几何尺寸完全相同，N₁₂、N₁₃几何尺寸完全相同，P₈、P₉几何尺寸完全相同，N₁₅、N₁₆几何尺寸完全相同，N₁₇和N₁₈沟道长度相同，宽度成比例。In addition, in order to further increase the working speed, the MOS transistors on the charging and discharging path of the present invention, that is, P₂ -P₇ , N₁ -N₁₄ all adopt the minimum gate length. In order to realize the continuous charging and continuous sampling feedback of the output voltage V_OUT , so that C₂ and C₃ can charge C₄ alternately, and C₅ and C₆ can alternately sample and step down V_OUT , the circuit of the present invention adopts a symmetrical design, That is, the geometric dimensions of P₂ and P₃ are identical, the geometric dimensions of N₁ and N₂ are identical, the geometric dimensions of C₂ and C₃ are identical, the geometric dimensions of N₃ and N₄ are identical, and the geometric dimensions of N₅ and N₆ are identical , the geometric dimensions of N₇ and N₈ are identical, the geometric dimensions of P₄ and P₅ are identical, the geometric dimensions of N₉ and N₁₀ are identical, the geometric dimensions of P₆ and P₇ are identical, and the geometric dimensions of N₁₁ and N₁₄ are identical , N₁₂ and N₁₃ have the same geometric dimensions, P₈ and P₉ have the same geometric dimensions, N₁₅ and N₁₆ have the same geometric dimensions, N₁₇ and N₁₈ have the same channel length and proportional width.

本发明的制造工艺为通用的硅栅N阱CMOS工艺。The manufacturing process of the present invention is a common silicon gate N well CMOS process.

本发明电路中的PMOS、NMOS管的基本参数为：The basic parameters of PMOS and NMOS tubes in the circuit of the present invention are:

NMOS管的阈值电压V_thn：0.6～0.8V；Threshold voltage V_thn of NMOS transistor: 0.6～0.8V;

PMOS管的阈值电压V_thp：-0.6～-0.8V；Threshold voltage V_thp of PMOS transistor: -0.6～-0.8V;

输入电压V_REF＞1V。The input voltage V_REF >1V.

Claims (5)

Translated fromChinese

1.一种基于反馈的电荷泵电路，其特征在于，它含有：1. A charge pump circuit based on feedback, characterized in that it contains:一个高电压产生单元，包括：A high voltage generating unit comprising:PMOS管P₁～P₅、NMOS管N₁～N₈、电容C₁～C₄，其中，P₁的栅极接此高电压产生单元的输入端V_J，P₁的源极接电源V_DD，P₁的漏极与P₂的源极及衬底、P₃的源极及衬底相接，并与C₁的上极板连接在一起，C₁的下极板接地V_SS，P₂、N₁的栅极接第一时钟端CLK₁，P₃、N₂的栅极接第二时钟端CLK₂，P₂、N₁的漏极与C₃的下极板相接，P₃、N₂的漏极与C₂的下极板相接，N₁、N₂的源极接地V_SS，N₃的源极与N₅的源极、N₆的栅极、P₄的栅极、P₅的漏极、N₈的漏极相接，并与C₂的上极板连接在一起，N₄的源极与N₆的源极、N₅的栅极、P₅的栅极、P₄的漏极、N₇的漏极相接，并与C₃的上极板连接在一起，N₃的栅极、N₃的漏极、N₄的栅极、N4的漏极、N₅的漏极、N₆的漏极都接电源V_DD，N₇的栅极接第二时钟端CLK₂，N₈的栅极接第一时钟端CLK₁，N₇的源极与P₄的源极、P₄的衬底、P₅的源极、P₅的衬底、N₈的源极相接，并与C₄的上极板连接在一起，其连接点为此高电压产生单元的输出端，即整个电荷泵电路的输出端V_OUT，C₄的下极板接地V_SS；和PMOS transistors P₁ to P₅ , NMOS transistors N₁ to N₈ , and capacitors C₁ to C₄ , where the gate of P₁ is connected to the input terminal V_J of the high voltage generating unit, and the source of P₁ is connected to the power supply V_DD , the drain of P₁ is connected to the source and substrate of P₂ , the source and substrate of P₃ , and connected to the upper plate of C₁ , the lower plate of C₁ is grounded V_SS , The gates of P₂ and N₁ are connected to the first clock terminal CLK₁ , the gates of P₃ and N₂ are connected to the second clock terminal CLK₂ , the drains of P₂ and N₁ are connected to the lower plate of C₃ , The drains of P₃ and N₂ are connected to the lower plate of C₂ , the sources of N₁ and N₂ are grounded to V_SS , the source of N₃ is connected to the source of N₅ , the gate of N₆ , and the gate of P₄ The gate of N4, the drain of_P5 , and the drain of_N8 are connected together, and are connected with the upper plate of_C2 , the source of_N4 is connected with the source of_N6 , the gate of_N5 ,_P5 The gate of N3, the drain of_P4 , and the drain of_N7 are connected together, and connected with the upper plate of_C3 , the gate of_N3 , the drain of_N3 , the gate of_N4 , the gate of N4 The drain, the drain of N₅ and the drain of N₆ are all connected to the power supply V_DD , the gate of N₇ is connected to the second clock terminal CLK₂ , the gate of N₈ is connected to the first clock terminal CLK₁ , and the source of N₇ The pole is connected to the source of_P4 , the substrate of_P4 , the source of_P5 , the substrate of_P5 , and the source of_N8 , and is connected with the upper plate of_C4 , and its connection point is The output terminal of this high voltage generating unit, that is, the output terminal V_OUT of the entire charge pump circuit, the lower plate of C₄ is grounded V_SS ; and一个降压单元，包括：A step-down unit consisting of:PMOS管P₆～P₇、NMOS管N₉～N₁₄、电容C₅～C₇，其中，N₉的源极、P₆的源极、P₆的衬底、P₇的源极、P₇的衬底、N₁₀的源极都与此降压单元的输入端，即高压产生单元的输出端V_OUT相接，N₉的漏极与P₆的漏极、N₁₁的漏极、N₁₂的漏极、P₇的栅极、N₁₃的栅极相接，并与C₅的上极板连接在一起，N₁₀的漏极与P₇的漏极、N₁₃的漏极、N₁₄的漏极、P₆的栅极、N₁₂的栅极相接，并与C₆的上极板连接在一起，N₉的栅极与C₅的下极板、N₁₄的栅极与第二时钟端CLK₂相接，N₁₀的栅极、C₆的下极板、N₁₁的栅极与第一时钟端CLK₁相接，N₁₁的源极与N₁₂的源极、N₁₃的源极、N₁₄的源极相接，并与C₇的上极板连接在一起，其连接点为此降压单元的输出端V_FB，C₇的下极板接地V_SS；和PMOS transistors P₆ to P₇ , NMOS transistors N₉ to N₁₄ , and capacitors C₅ to C₇ , among which, the source of N₉ , the source of P₆ , the substrate of P₆ , the source of P₇ , and the The substrate of₇ and the source of N₁₀ are all connected to the input end of the step-down unit, that is, the output end V_OUT of the high-voltage generating unit, and the drain of N₉ is connected to the drain of P₆ , the drain of N₁₁ , The drain of N₁₂ , the gate of P₇ , and the gate of N₁₃ are connected, and connected with the upper plate of C₅ , the drain of N₁₀ is connected with the drain of P₇ , the drain of N₁₃ , The drain of N₁₄ , the gate of P₆ , and the gate of N₁₂ are connected, and connected with the upper plate of C₆ , the gate of N₉ is connected with the lower plate of C₅ , and the gate of N₁₄ It is connected to the second clock terminal CLK₂ , the gate of N₁₀ , the lower plate of C₆ , the gate of N₁₁ is connected to the first clock terminal CLK₁ , the source of N₁₁ is connected to the source of N₁₂ , The source of N₁₃ and the source of N₁₄ are connected, and connected together with the upper plate of C₇ , the connection point is the output terminal V_FB of the step-down unit, and the lower plate of C₇ is grounded V_SS ; and一个反馈控制单元，包括：A feedback control unit comprising:PMOS管P₈～P₉、NMOS管N₁₅～N₁₈，其中，P₈的源极、P₉的源极接电源V_DD，P₈的栅极及漏极、P₉的栅极与N₅的漏极相接，P₉的漏极与N₁₆的漏极相接，其接点为此反馈控制单元的输出端V_J，即高压产生单元的输入端V_J，N₁₅的栅极接此反馈控制单元的输入端，即降压单元的输出端V_FB，N₁₆的栅极接此反馈控制单元的输入V_REF，N₁₅的源极、N₁₆的源极与N₁₇的漏极相接，N₁₇的栅极、N₁₈的栅极、N₁₈的漏极都与此反馈控制单元的输入端I_BIAS相接，N₁₇的源极、N₁₈的源极均接地V_SS。PMOS transistors P₈ to P₉ , NMOS transistors N₁₅ to N₁₈ , wherein the source of P₈ and the source of P₉ are connected to the power supply V_DD , the gate and drain of P₈ , the gate of P₉ are connected to the N The drain of P₉ is connected to the drain of N₁₆ , and its contact point is the output terminal V_J of the feedback control unit, that is, the_input terminal V_J of the high-voltage generating unit, and the gate of N₁₅ is connected to The input terminal of this feedback control unit, that is, the output terminal V_FB of the step-down unit, the gate of_N16 is connected to the input V_REF of this feedback control unit, the source of_N15 , the source of_N16 and the drain of_N17 The gate of N₁₇ , the gate of N₁₈ , and the drain of N₁₈ are all connected to the input terminal I_BIAS of the feedback control unit, and the source of N₁₇ and N₁₈ are both grounded to V_SS .2.根据权利要求1所述的一种基于反馈的电荷泵电路，其特征在于：所述电荷泵电路能够产生连续变化的输出电压值，且输出电压大于电源电压。2. A charge pump circuit based on feedback according to claim 1, characterized in that: the charge pump circuit can generate a continuously variable output voltage value, and the output voltage is greater than the power supply voltage.3.根据权利要求1所述的一种基于反馈的电荷泵电路，其特征在于：所述电荷泵电路能够利用反馈功能来调节电荷泵的输出电压，使输出电压随输入电压的变化而变化。3. A charge pump circuit based on feedback according to claim 1, characterized in that: the charge pump circuit can use the feedback function to adjust the output voltage of the charge pump, so that the output voltage changes with the change of the input voltage.4.根据权利要求1所述的一种基于反馈的电荷泵电路，其特征在于：所述电荷泵电路的电荷泵增益与MOS管的阈值电压无关。4. A feedback-based charge pump circuit according to claim 1, characterized in that: the charge pump gain of the charge pump circuit has nothing to do with the threshold voltage of the MOS transistor.5.根据权利要求1所述的一种基于反馈的电荷泵电路，其特征在于：所述电荷泵电路包含两个充电通路，在时钟的控制下，交替向负载充电。5. A feedback-based charge pump circuit according to claim 1, characterized in that: said charge pump circuit comprises two charging paths, which alternately charge the load under the control of the clock.

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