CN101872377B - Method for restraining integrated circuit electricity supply network noise by using decoupling capacitance - Google Patents

Abstract

The invention discloses a method for restraining integrated circuit electricity supply network transient voltage drop noise by using decoupling capacitance, belonging to the physical design field of superlarge-scale integrated circuit, in particular to the technical category of optimizing network noise of transient power wire earth wires, which is characterized in that the creation points lie in that: (1) proposing a rapid method for estimating a decoupling capacitance demand in a layout stage; proposing a two-dimensional function showing the decoupling capacitance demand in a chip; (3) establishing a supply and demand system for the demand of the decoupling capacitance by utilizing the two-dimensional function to guide that the layout process is performed toward the direction being beneficial for reducing the demand of the decoupling capacity; and (4) proposing a layout algorithm for adding the decoupling capacitance through integrating the above model and the method into a force direction layout. Experiments prove that the method of the invention is effective, and can achieve the layout result that the total amount of the decoupling capacity is decreased by about 35% with the cost that the on-line length is increased by about 0.5%.

Description

Use decoupling capacitance to suppress the method for integrated circuit electricity supply network noise

Technical field

The method of using decoupling capacitance to suppress integrated circuit electricity supply network noise belongs to the technology category of transient state power lead earth cord network noise optimization in VLSI (very large scale integrated circuit) (VLSI) physical Design field, especially the physical Design field.

Background technology

The supply network of integrated circuit comprises power-line network and earth cord network (being collectively referred to as the power ground network).The power ground Network Design belongs to the distinct line screen cloth line in the integrated circuit physical Design.Mainly need to solve supply voltage noise reduction sound problem in the power ground network design.Along with the continuous progress of integrated circuit technology, the chip feature size is constantly dwindled, and the integrated level and the frequency of operation of chip increase substantially, and the operating voltage of chip constantly reduces.These all cause the power ground network noise to increase and noise margin reduces, thereby make power ground network noise reduction problem become the major issue of VLSI (very large scale integrated circuit) (VLSI) in designing.Unsuitable power ground network design can produce excessive voltage drop and voltage fluctuation, greatly influences the performance of circuit, even causes circuit malfunction, and chip can't operate as normal.Therefore, the power ground network is analyzed accurately and optimization is very important.

The voltage drop noise mainly comprises two types on the ic power earth cord network: a kind of static state or dc voltage drop (IR Drop) of being called, this voltage drop are caused by the dead resistance of power supply gauze on the power ground network.Another is called transient voltage and falls (Transient Voltage Drop), and this voltage drop is caused by stray inductance on transistorized transient current variation and the power ground network.When the elimination quiescent voltage falls, usually can adopt power ground topology optimization (Singh J., SapatnekarS.S., Topology optimization of structured power/ground networks.Proceedings of International Symposium on Physical Design, 2004.116-123.), live width optimization (Wu Xiaohai. VLSI (very large scale integrated circuit) power ground network design and optimized Algorithm research: [PhD dissertation]. Beijing: Computer Science and Technology Department of Tsing-Hua University, 2001) etc. method solve.When problem fell in transient voltage on solving the power ground network, effective method was to add decoupling capacitance the most.Along with the modern integrated circuits design becomes increasingly complex, in order to eliminate more and more serious transient voltage noise reduction sound, the decoupling capacitance amount that need add on chip is more and more.And too much decoupling capacitance can produce many adverse influences to the performance of integrated circuit (IC) chip and stability: the transistor that (1) is used for making decoupling capacitance can produce leakage current, thereby adds the quiescent dissipation that decoupling capacitance can increase entire chip significantly too much; (2) too much decoupling capacitance causes chip yield to descend cost up; (3) too much decoupling capacitance can take a large amount of chip areas, produces resource contention with other device.For a long time, the research and design personnel are seeking a kind ofly to place decoupling capacitance less as far as possible and solve the method for transient voltage noise reduction sound always.

In traditional design cycle, decoupling capacitance is generally after layout finishes, determined after the position of each module or unit, again design result is carried out the transient analysis of power ground network, as the transient voltage noise reduction sound of finding not meet design requirement, adopt method noise reduction (the Dharchoudhury A that adds decoupling capacitance, Panda R, Blaauw D, et al.Design and analysis ofpower distribution networks in PowerPC microprocessors.Proceedingsof Design Automation Conference, 1998.738-743.).In the process of adding decoupling capacitance, for fear of the adverse effect of a large amount of decoupling capacitances, need the placement location of decoupling capacitance be optimized chip performance, use minimum decoupling capacitance to solve transient voltage noise reduction sound problem as far as possible.In order to obtain optimum decoupling capacitance laying method, the researchist has carried out deep research to this problem: document (Fu J, Luo Z, Hong X, et al.A fast decoupling capacitorbudgeting algorithm for robust on-chip power delivery.Proceedings ofAsia and South Pacific Design Automation Conference, 2004.505-510.) utilization is carried out the optimization of decoupling capacitance based on the mathematic programming methods of sensitivity.But this often more consuming time based on sensitivity of method, can not be applied to larger circuit.Therefore, more new algorithm is suggested to improve the efficient of decoupling capacitance optimized Algorithm.For example, document (Li H, Fan J, QiZ, et al.Partitioning-Based Approach to Fast On-Chip DecouplingCapacitor Budgeting and Minimization.IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, 2006,25 (11): 2402-2412.) algorithm that has proposed a kind of circuit piecemeal comes huge circuit is carried out decoupling capacitance optimization; And document (Kang L, Cai Y, Zou Y, et al.Fast DecouplingCapacitor Budgeting for Power/Ground Network Using Random WalkApproach.Proceedings of Asia and South Pacific Design AutomationConference 2007.751-756.) has further improved the efficient of algorithm by the method (Random Walk) of using random walk.Document (Zhao M, Panda R, Sundareswaran S, et al.A fast on-chip decoupling capacitance budgeting algorithm usingmacromodeling and linear programming.Proceedings of Design AutomationConference 2006.217-222.) has proposed the algorithm of finding the solution the decoupling capacitance optimization problem with macro model (Macro-model) and linear programming method.In addition, also be used to quicken process (the Fan J that decoupling capacitance is optimized based on the convex programming algorithm, Liao I F, Tan S X D, et al.Localizedon-chip power delivery network optimization via sequence of linearprogramming.Proceedings of 7th International Symposium on QualityElectronic Design, 2006.6pp.-277.).

It is pointed out that it all is after layout is finished that the inhibition method falls in above-mentioned various transient voltage, found by the power ground network simulation that transient voltage falls and do not satisfied after the power requirement, just carry out decoupling capacitance and place and optimize.Yet,,, all be difficult to the situation of the excessive transient voltage noise reduction sound of elimination in any case add decoupling capacitance after tending to appear at layout along with receiving electric current constantly to increase in the chip and supply voltage constantly reduces.At this moment, can only return layout stage even floor planning stage, the layout of chip is adjusted, repeat the transient analysis of power ground network and the process of adding decoupling capacitance then, expectation solves the problem that transient voltage falls by this design iteration.Such design iteration often will carry out several times repeatedly, has increased the design cost and the design time of chip greatly.

The reason that this design iteration occurs does not consider that just because of above-mentioned decoupling capacitance optimized Algorithm different layout result (being the different putting position in module or unit) is to power ground network power supply Effect on Performance.Module on the chip or unit need receive electric current, are the loads of power ground network.Their different putting positions obviously can cause tangible influence to the power supply performance of power ground network.Recently the researchist has had realized that this point, and has proposed some solutions.Document (Zhao S, Roy K, Koh C K.Decoupling capacitance allocation and its applicationto power supply noise-aware floorplanning.IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, 2002,21 (1): 81-92.) proposed in floor planning, to consider the method that decoupling capacitance is placed, to reduce the total area of floor planning and decoupling capacitance.And document (Kahng A B, Liu B, Wang Q.Supplyvoltage degradation aware analytical placement.Proceedings of IEEEInternational Conference on Computer Design, 2005.437-443.) in, quiescent voltage on the supply network falls of being used as in the layout stage optimization aim function and is integrated in the process of whole layout, falls littler layout in order to obtain quiescent voltage.But, also do not consider that at layout stage problem falls in the transient voltage of power ground network at present, and the research of decoupling capacitance optimization problem report.

The present invention proposes a kind of method that suppresses the voltage drop of power ground network transients at layout stage with decoupling capacitance.Use the layout result that this method produces, can use minimum decoupling capacitance to eliminate transient voltage noise reduction sound on the power ground network.In the present invention, at first, decoupling capacitance placement problem is converted into a linear programming problem (Zhao M by macro model (Macro-model), PandaR, Sundareswaran S, et al.A fast on-chip decoupling capacitancebudgeting algorithm using macromodeling and linear programming.Proceedings of Design Automation Conference, 2006.217-222.), in order to determine the demand of different layout result to decoupling capacitance.Secondly, the linear programming problem of placing by the research decoupling capacitance is shown one " electric density " (" Electric Density ") function on the chip with the demand schedule of decoupling capacitance.In fact, " electric density " function representation the size of the power supply capacity of diverse location on the chip.In general, when excessive, just illustrate that this zone needs to use decoupling capacitance further strengthen power supply capacity as " the electric density " in certain zone on the fruit chip.Therefore, " electric density " function can represent that zones of different is to the decoupling capacitance demand on the chip.And balance " electric density " function will help placing decoupling capacitance still less.Next further set up one " supply and demand system " (" Supply and Demand System ") for " electric density " function, be used for producing the power of mobile module in the layout or mobile unit, make the unit move towards the direction that helps reducing decoupling capacitance.This power and original power are pointed to layout device (Spindler P, Schlichtmann U, JohannesF M.Kraftwerk2-A Fast Force-Directed Quadratic Placement ApproachUsing an Accurate Net Model.IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems, 2008,27 (8): other power is taken all factors into consideration together 1398-1411.), just can obtain existing optimized line length, can reduce layout result again the decoupling capacitance demand.So-called power is pointed to the layout device, and its basic thought is to be the equivalence of the interconnection line between any two unit or the module spring, and each unit (or module) is subjected to the effect of the attractive force that other interconnecting unit (or module) applies by spring; According to Hooke's law as can be known, the size of this attractive force is directly proportional with distance between unit (or module), and the stiffness factor of spring then is the direct weight sum of phase connecting diagram between the unit (or module); Under the effect of attractive force, all interconnecting units (or module) will move along the direction of power, reach the state of energy minimum up to total system, i.e. equilibrium state, and the size of making a concerted effort that each unit this moment (or module) is subjected to is zero; And power sensing layout device allows unit (or module) move along its suffered resultant direction exactly, makes a concerted effort to reduce to till zero up to this; The placement algorithm that points to principle based on power is through for a long time development, and one is pointed to the placement algorithm flow process as shown in Figure 9 than complete modern power.Generally speaking, the present invention can produce rational layout, and need not to place too much decoupling capacitance and just can eliminate transient voltage noise reduction sound on the power ground network, reduces design iteration, reduces design cost and shortens the purpose of design time thereby reach.

We adopt the actual design example of industry member that the inventive method is tested, and table with test results is understood validity of the present invention: the present invention can make the decoupling capacitance total amount reduce about 35% under total line length only increases cost about 0.5%.And the present invention only needs short working time, can be used as the practical approach that the layout stage decoupling capacitance is optimized.

Summary of the invention

The present invention has designed a kind of method of using decoupling capacitance to suppress ic power earth cord network transient voltage noise reduction sound efficiently, in layout process, consider the placement of conventional in layout performance index (line length) and decoupling capacitance simultaneously, can obtain to help improving the layout result of power supply performance effectively.Application macro model (Macro-model) is converted into a linear programming problem with the decoupling capacitance optimization problem, thereby can determine the different demands of different layout result to decoupling capacitance apace; Use the power supply capacity of diverse location on " electric density " (" Electric Density ") function representation layout process chips, thereby the power supply load reasonably can be distributed according to power supply capacity; " supply and demand system " (" Supply and Demand System ") is used for producing the power of adjusting unit in the layout or module position, thereby makes the power supply load to move to the position of setting effectively; Power is pointed to layout device (Force-Directed Placer) and is used for traditional layout index (line length), unit or module is overlapping and the decoupling capacitance placement integrates and is optimized, thereby can keep reducing the use amount of decoupling capacitance effectively under line length and unit or the non-overlapping prerequisite of module.The decoupling capacitance that the present invention is based on these four kinds of methods realizations suppresses ic power earth cord network transient voltage noise reduction sound and has obtained good effect.

Below " electric density " function of decoupling capacitance and " supply and demand system " are illustrated.To help the layout result that decoupling capacitance is placed in order accessing, must in layout process, to produce a power of representing the decoupling capacitance demand.And, just must in the iteration each time of layout process, can both estimate the demand of decoupling capacitance in order to produce this power.The basic step of the method for quick estimating of the decoupling capacitance total amount of Ti Chuing is in the present invention:

1) method (the Zhao M of use macro model, Panda R, Sundareswaran S, et al.A faston-chip decoupling capacitance budgeting algorithm usingmacromodeling and linear programming.Proceedings of Design AutomationConference, 2006.217-222.), earlier the decoupling capacitance problem of placing is converted into linear programming problem by a nonlinear optimal problem; By with the circuit equation in the decoupling capacitance optimization problem

With voltage drop constraint V 〉=V_Thre(wherein: C represents supply network node capacitor matrix, and G represents the node conductance matrix, and V represents the node voltage matrix, and J represents that node receives current matrix, V to carry out linearization_ThreThe voltage drop threshold value of expression user appointment), thus the decoupling capacitance optimization problem is converted into a linear programming problem.This distortion mainly comprises following three steps: at first, and note V_2sBe the voltage vector on the violation area sampling point, and [t₀, t₁] for violating the time window of voltage drop constraint, so, can be with improved nodal voltage equation piecemeal

And it is carried out integration obtains:

$\left(\begin{array}{cc}{G}_{11}& G_{12}\\ G_{12}^T& G_{22}\end{array}\right)\&CenterDot;\left(\begin{array}{c}{\&Integral;}_{t_0}^{t_1}{V}_{1s}\mathrm{dt}\\ {\&Integral;}_{t_0}^{t_1}{V}_{2s}\mathrm{dt}\end{array}\right)=\left(\begin{array}{c}{\&Integral;}_{t_0}^{{\mathrm{<figure-callout\; label="t"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">t</figure-callout>}}_1}\mathrm{Jdt}\\ {\&Integral;}_{t_0}^{t_1}{\mathrm{<figure-callout\; label="J"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">J</figure-callout>}}_2\mathrm{dt}+{\&Integral;}_{t_0}^{{\mathrm{<figure-callout\; label="t"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">t</figure-callout>}}_1}\mathrm{Idt}\end{array}\right)$

Wherein: V_1sBe power supply network internal node voltages vector, J₁For the power supply network internal node receives current vector, J₂Be the current vector that receives of power supply network fringe node, I is the supply current vector of power pad Pad, G₁₁Be the electric derived vector of power supply network internal node, G₁₂Be the conductance matrix between power supply network internal node and the power pad Pad, G₂₂Conductance matrix for power pad Pad.

Secondly, use macro model to obtain the electric weight equation of transfer to above-mentioned formula

Q＝H·W+B

Wherein:Be the electric weight that need provide from decoupling capacitance,

Be admittance matrix, W is the voltage waveform integration

AndEquivalent electric quantity for load current source; At last, transient voltage is fallen constraint V 〉=V_ThreBe converted into linear restriction by integration about voltage waveform integration W.As shown in Figure 1, the transient voltage waveform that falls constraint requirements voltage after having added decoupling capacitance can not be lower than voltage drop threshold value V_ThreAccordingly, voltage waveform integration W should be less than the area of dash area among the figure.The trapezoidal area of the area of dash area under by a dotted line is similar among the figure.This is because before adding optimum decoupling capacitance, can't know the voltage curve that surrounds the dash area area.So constraint V 〉=V falls in transient voltage_ThreJust be converted into the voltage waveform integral constraint, thereby decoupling capacitance optimization is converted into a following linear optimization problem;

$\min \underset{i\&Element;S}{\mathrm{\&Sigma;}}{c}_i$

s.t. ------(1)

$M^{\&prime;}\&CircleTimes;C\&GreaterEqual;H\&CenterDot;W+B$

W≥L

0≤c_i≤c_max，i

Wherein: S is the sampling set of node in violation of rules and regulations, and m=|S| represents the element number in the S set, vectorial C=[c₁, c₂..., c_m], c_iBe illustrated in decoupling capacitor and stray capacitance sum that i sampling node adds, c_{Max, i}Be illustrated near the maximum decoupling capacitor value that is allowed i the sampling node, symbol

Expression is multiplied each other item by item, and a T=(t clocks₁-t₀)/2, M ' in the following formula and L can be calculated by following formula:

$M^{\&prime;}=\left(\begin{array}{c}{V}_1\left(t_0\right)-V_1\left(t_1\right)\\ V_2\left(t_0\right)-V_2\left(t_1\right)\\ .\\ .\\ .\\ V_m\left(t_0\right)-V_m\left(t_1\right)\end{array}\right),$$L=\left(\begin{array}{c}(V_{\mathrm{thre}}+V_1\left(t_0\right))\&CenterDot;T\\ (V_{\mathrm{thre}}+V_2\left(t_0\right))\&CenterDot;T\\ .\\ .\\ .\\ (V_{\mathrm{thre}}+V_m\left(t_0\right))\&CenterDot;T\end{array}\right)---\left(2\right)$

2) linear programming problem of above-mentioned decoupling capacitance is converted into its dual problem (DualProblem).Because though the decoupling capacitance optimization problem so far has been converted into a linear programming problem, obtained simplifying greatly,, it is still unclear to produce what kind of influence to the decoupling capacitance total amount when chip upper module or unit are in diverse location actually.Cause the reason of this situation be module or unit on chip the position directly influence be the equivalent electric quantity B of load current source, and in the Linear Programming Problem (1), the equivalent electric quantity B of load current source has appeared at intrafascicular approximately, causes being difficult to setting up contacting directly between the position of module or unit and the decoupling capacitance total amount.For the position and the relation between the decoupling capacitance total amount that can make chip upper module or unit is more clear, the linear programming problem (1) of decoupling capacitance is converted into its dual problem

$\max {(L-W)}^T\&CenterDot;C^{\&prime;}-C_{\max }^T\&CenterDot;C^{\&prime;\&prime;}$

s.t.

$M^{\&prime;}\&CircleTimes;(H^{-1}\&CenterDot;C^{\&prime;})-C^{\&prime;\&prime;}\&le;E---\left(3\right)$

H^-1·C′≥0

C′≥0，C″≥0

Wherein: W=-B^TH^-1, C ' and C " and represent the dual variable of C respectively,The maximum decoupling capacitor vector that allows adding of expression, constant vector E=[1,1 ..., 1]^TDuality principle according to linear programming knows that dual problem (3) has identical separating with the former linear programming problem (1) that decoupling capacitance is optimized, and has all represented the decoupling capacitance total amount of needs.And from the objective function of dual problem (3), can see that the total amount of decoupling capacitance is proportional to norm || L-W||₁In fact, vectorial L-W has represented the integration of the gap between voltage waveform in violation of rules and regulations and the legal voltage waveform in the physical sense just, as shown in Figure 2.

3) the decoupling capacitance electric weight that need provide can be used as a standard weighing the decoupling capacitance demand, and the demand of decoupling capacitance is modeled as " electric density function " on the chip.In fact, with the supply and demand system class of chip upper module or cell distribution seemingly, it is the integration of the required voltage waveform of module or unit that L and W have also represented the supply and demand of supply voltage: W; L is the integration of the power ground network voltage waveform that can provide; And the decoupling capacitance part that will remedy just of the gap between the two.And can be further by respectively to W and L interpolation obtain on entire chip " electric density function " W (x, y) and L (x, y).By paired observation, can find " electric density function " and " cell density function "

Between similarity

$W(x,y)\&LeftRightArrow;D_{\mathrm{mod}}^{\mathrm{dem}}(x,y)$

$L(x,y)\&LeftRightArrow;D_{\mathrm{mod}}^{\sup }(x,y)$

4) set up corresponding supply and demand system by " electric density function " for the demand of decoupling capacitance at last.This supply and demand system by Poisson equation (shape asOval partial differential equation) define potential-energy function Ψ (x, y) expression:

$(\frac{{\&PartialD;}^2}{\&PartialD;x^2}+\frac{{\&PartialD;}^2}{\&PartialD;y^2})\mathrm{\&Psi;}(x,y)=L(x,y)-W(x,y)$

Satisfy the Newman boundary condition$\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;n}=0$

Use decoupling capacitance to suppress in the method for integrated circuit electricity supply network noise, comprise and produce the standard cell placement step that helps improving power supply performance, minimizing decoupling capacitance placement total amount, it be with the area of decoupling capacitance and conventional in layout index (line length, module or cells overlap) simultaneously as optimization aim, effective method for solving that power ground network noise and layout line length are optimized is simultaneously come in the position of adopting the method for iteration constantly to adjust module in the layout or unit.It gets up method synthesis such as macro model, electric density function, supply and demand system, power sensing layout, produces to help using a small amount of decoupling capacitance to suppress the layout result of integrated circuit electricity supply network noise, obtains good optimization effect.Specifically may further comprise the steps:

Step (1), computing machine are read in the file that comprises power ground network design parameter and cell layout's design parameter, and power ground network design parameter comprises: the position of power ground network and line width, the position of energization pins Pin; Determine the relational structure between the node on it, initial resistivity value, capacitance and cell current source model between the node according to the position of power ground network and width, promptly the time dependent current waveform that receives of each unit correspondence is represented with PWL; In computing machine, set up the circuit model of power ground network in view of the above; Described cell layout design parameter comprises: whether the initial position that the side-play amount of pin, unit are placed on the size of each unit, the unit, the direction of unit, the zone of layout, the position and the unit of cell row can move;

Step (2), the power ground network is carried out static analysis, if falling, quiescent voltage do not meet the demands, then the power ground network is carried out whole live width adjustment, make dc voltage drop meet design requirement, add decoupling capacitance with this as next step and carry out the pacing items that elimination falls in transient voltage;

Step (3) is carried out initialization to layout, at first all transportable unit is placed into the center of layout areas, repeats following initialization step (3.1)-(3.3) five times then;

Step (3.1), use the bounding box linear model to obtain the quadratic expression of line length:

${\mathrm{\&Gamma;}}_x=\frac{1}{2}{x}^T{C}_{x}x+d_x^{T}x+\mathrm{<figure-callout\; label="const"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">const</figure-callout>}1$

${\mathrm{\&Gamma;}}_y=\frac{1}{2}{y}^T{C}_{y}y+d_y^{T}y+\mathrm{const}2$

Wherein:

Γ_xAnd Γ_yBe respectively the semi-perimeter line length of X-direction and Y direction,

X represents the vector that each unit center constitutes in the cartesian coordinate system on X-direction,

Y represents the vector that each unit center constitutes in the cartesian coordinate system on X-direction,

(x, y) expression residing position, unit,

d_xBe a vector, represent the annexation on X-direction between removable unit and the fixed cell, if they have annexation, then they are at d_xThe element of middle relevant position is 1, otherwise is 0,

d_yBe a vector, represent the annexation on Y direction between removable unit and the fixed cell, if they have annexation, then they are at d_yThe element of middle relevant position is 1, otherwise is 0,

C_xBe a positive semi-definite symmetric matrix, be used for representing the annexation on X-direction between the removable unit, if between two removable unit annexation is arranged, then they are at C_xThe element of middle relevant position is 1, otherwise is 0,

C_yBe a positive semi-definite symmetric matrix, be used for representing the annexation on Y direction between the removable unit, if between two removable unit annexation is arranged, then they are at C_yThe element of middle relevant position is 1, otherwise is 0,

Const1 represents the line length constant term of directions X,

Const2 represents the line length constant term of Y direction,

The bounding box linear model is meant a minimum rectangle that comprises all summits of gauze, and its girth can be expressed as

L_n＝2(x_max-x_min+y_max-y_min)

(x wherein_Min, y_Min) be the apex coordinate in this rectangle frame lower left corner, (x_Max, y_Max) be the apex coordinate in its upper right corner;

Step (3.2), find the solution system of linear equations respectively about x and y:

C_xx＝d_x

C_yy＝d_y

This equation is two systems of linear equations, and that matrix of coefficients has is sparse, the character of positive definite, symmetry, uses the method for ICCG to find the solution, and obtains x and y;

Step (3.3), x and y according to step (3.2) obtains make x '=x and y '=y, and the reposition that changes the unit is (x ', y ');

Step (4) is added the total arrangement of decoupling capacitance;

Step (4.1), initializes weights parameter and weight matrix:

Step (4.1.1), the initializes weights parameter beta

$\mathrm{\&beta;}=\frac{2}{V_{\mathrm{dd}}-V_{\mathrm{thre}}}$

V wherein_DdBe supply voltage, V_ThreIt is the voltage drop threshold value of user's appointment;

Step (4.1.2), the initializes weights matrix

Wherein

Be layout quality control weight parameter matrix, by the area parameters A of each unit_iCalculate, m represents the total quantity of unit, i=1, and 2 ..., m;

Step (4.1.3), initialization electric weight weight matrix

Wherein

Be electric weight weight coefficient matrix in the time t, receive electric weight J by each unit₁Integral and calculating to time t obtains;

Step (4.2), the Duplication Ω of computing unit, overlapping unit overlapping and the unit of comprising overlaps two kinds of situations, the implication of Duplication is the number percent that the element number that overlaps accounts for total element number, if Duplication is less than 10%, then layout finishes, otherwise repeats following steps;

Step (4.3), the distribution density function of computing unit

With

Step (4.3.1) is calculated the object element distribution density function

$D_{\mathrm{mod}}^{\sup }(x,y)=\frac{\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}{A}_i}{A_{\mathrm{chip}}}$

The object element distribution density function

The i.e. cell distribution density function that obtains of expectation after finishing layout, wherein: A_ChipThe area of expression entire chip, A_iThe area of representing each unit;

Step (4.3.2) is calculated the density function of cell distribution in the current layout

In order to calculate

Here introduce a rectangular window function

Represented whether select active cell, wherein (x, y) expression active cell position, (x_Ll, y_Ll) coordinate on summit, the lower left corner of expression rectangle, (w h) is the width and the height of this rectangle; If note active cell center be (x '_i, y '_i), the width of active cell and highly be (w_i, h_i), then set up corresponding to above-mentioned rectangular window function following formula:

$x_{\mathrm{ll}}=x_i^{\&prime;}-\frac{{\mathrm{<figure-callout\; label="w\; i"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">w</figure-callout>}}_i}{2}$

$y_{\mathrm{ll}}=y_i^{\&prime;}-\frac{{\mathrm{<figure-callout\; label="h\; i"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">h</figure-callout>}}_i}{2}$

At this moment the density function of cell distribution

Can calculate by following formula:

$D_{\mathrm{mod}}^{\mathrm{dem}}(x,y)=\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}{d}_{\mathrm{mod},i}\&CenterDot;R(x,y,x_i^{\&prime;}-\frac{{\mathrm{<figure-callout\; label="w\; i"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">w</figure-callout>}}_i}{2},y_i^{\&prime;}-\frac{{\mathrm{<figure-callout\; label="h\; i"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">h</figure-callout>}}_i}{2},w_i,h_i)$

D wherein_{Mod, i}The density of expression unit i is set to 1 under the simple scenario;

Step (4.4), the Poisson equation of finding the solution the supply and demand system that description unit distributes, obtain potential-energy function Φ (x, y), Poisson equation be shape asOval partial differential equation, it is as follows that the supply and demand system is described as Poisson equation:

$(\frac{{\&PartialD;}^2}{\&PartialD;x^2}+\frac{{\&PartialD;}^2}{\&PartialD;y^2})\mathrm{\&Phi;}(x,y)=D_{\mathrm{mod}}^{\sup }(x,y)-D_{\mathrm{mod}}^{\mathrm{dem}}(x,y)$

Satisfy the Newman boundary condition$\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;n}=0$

Wherein n represents the borderline normal vector of field of definition;

Step (4.5), computing chip power on density function W (x, y) and L (x, y)

Step (4.5.1) is utilized the method for macro model, with power ground lattice network equation

Change into following form:

$\left(\begin{array}{cc}{G}_{11}& G_{12}\\ G_{12}^T& G_{22}\end{array}\right)\&CenterDot;\left(\begin{array}{c}{\&Integral;}_{t_0}^{t_1}{V}_{1s}\mathrm{dt}\\ {\&Integral;}_{t_0}^{t_1}{V}_{2s}\mathrm{dt}\end{array}\right)=\left(\begin{array}{c}{\&Integral;}_{t_0}^{{\mathrm{<figure-callout\; label="t"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">t</figure-callout>}}_1}\mathrm{Jdt}\\ {\&Integral;}_{t_0}^{t_1}{\mathrm{<figure-callout\; label="J"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">J</figure-callout>}}_2\mathrm{dt}+{\&Integral;}_{t_0}^{{\mathrm{<figure-callout\; label="t"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">t</figure-callout>}}_1}\mathrm{Idt}\end{array}\right)$

Wherein:

C represents supply network node capacitor matrix,

G represents the node conductance matrix,

V represents the node voltage matrix,

J represents that node receives current matrix,

V_2sBe the node voltage vector that needs to add decoupling capacitance,

V_1sBe supply network internal node voltages vector,

J₁For the supply network internal node receives current vector,

J₂Be the current vector that receives of supply network fringe node,

I is the supply current vector of power pad Pad,

G₁₁Be the electric derived vector of supply network internal node,

G₁₂Be the conductance matrix between supply network internal node and the power pad Pad,

G₂₂Conductance matrix for power pad Pad;

Step (4.5.2), according to following steps, calculate power consumption density function W (x, y) and power density function L (x, y):

Step (4.5.2.1), the calculating voltage integral of pulse shapeThere is following formula to set up simultaneously

W＝-B^T·H^-1

Wherein

The admittance matrix of expression power ground network,

$B=G_{12}^T{G}_{11}^{-1}{\&Integral;}_{t_0}^{t_1}{\mathrm{<figure-callout\; label="J"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">J</figure-callout>}}_1\mathrm{dt}-{\&Integral;}_{t_0}^{t_1}{\mathrm{<figure-callout\; label="J"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">J</figure-callout>}}_2\mathrm{dt}$The equivalent electric quantity of expression load current source;

Step (4.5.2.2) is at T=(t₁-t₀Calculate power density function L in the time of)/2

$L=\left(\begin{array}{c}(V_{\mathrm{thre}}+V_1\left(t_0\right))\&CenterDot;T\\ (V_{\mathrm{thre}}+V_2\left(t_0\right))\&CenterDot;T\\ .\\ .\\ .\\ (V_{\mathrm{thre}}+V_m\left(t_0\right))\&CenterDot;T\end{array}\right)$

V wherein_i(t₀) be t₀The voltage vector of moment unit i;

Step (4.5.2.3), utilize step (4.5.2.1) and (4.5.2.2) in the W and the L that obtain, the method that adopts Lagrange's interpolation is at the enterprising row interpolation in layout plane, obtain power consumption density function W (x, y) and power density function L (x, y);

Step (4.6) is found the solution by adding the Poisson equation that decoupling capacitance reaches the supply and demand system balancing, obtain potential-energy function Ψ (x, y)

$(\frac{{\&PartialD;}^2}{\&PartialD;x^2}+\frac{{\&PartialD;}^2}{\&PartialD;y^2})\mathrm{\&Psi;}(x,y)=L(x,y)-W(x,y)$

Satisfy the Newman boundary condition$\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;n}=0$

In above-mentioned Poisson equation, contract of supply L (x, y) generally can not with demand function W (x, y) complete equipilibrium, this point are that the self character by electric power system is determined, exactly because the supply and demand function can not complete equipilibrium, carry out the equilibrium of supply and demand as a supplement just need to add decoupling capacitance, and, in order to make above-mentioned Poisson equation to separate, need carry out orthogonalization to the supply and demand function

Represent orthogonalized power density function,

Represent orthogonalized power consumption density function

$\tilde{L}(x,y)=L(x,y)-\&Integral;\&Integral;\mathrm{Ldxdy}$

$\tilde{W}(x,y)=W(x,y)-\&Integral;\&Integral;\mathrm{Wdxdy}$

Step (4.7), according to the result of step (3.3), use the bounding box linear model to obtain the quadratic expression of current line length:

${\mathrm{\&Gamma;}}_x=\frac{1}{2}{x}^T{C}_x{x}^{\&prime;}+d_x^T{x}^{\&prime;}+\mathrm{<figure-callout\; label="const"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">const</figure-callout>}1$

${\mathrm{\&Gamma;}}_y=\frac{1}{2}{y}^T{C}_y{y}^{\&prime;}+d_y^T{y}^{\&prime;}+\mathrm{<figure-callout\; label="const"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">const</figure-callout>}2$

Step (4.8) is utilized difference method, the continuous variable problem is converted into the discrete variable problem so that numerical solution, obtain potential-energy function Φ (x, y) and Ψ (x, gradient function y):

${\mathrm{\&Phi;}}_x=\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;x},$${\mathrm{\&Phi;}}_y=\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;y}$

${\mathrm{\&Psi;}}_x=\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;x},$${\mathrm{\&Psi;}}_y=\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;y}$

And to Ψ_x, Ψ_yCalculate its corresponding zoom factor γ to guarantee that cells overlap can be eliminated effectively:

${\mathrm{\&gamma;}}_i=\min (\mathrm{1,0.9}\&times;\frac{<\&dtri;{\mathrm{\&Phi;}}_i\&CenterDot;\&dtri;{\mathrm{\&Phi;}}_i>}{<\&dtri;{\mathrm{\&Phi;}}_i\&CenterDot;\&dtri;{\mathrm{\&Psi;}}_i>})$

Wherein i is an element number,

For potential-energy function Φ (x, y) and Ψ (x, y) at the Grad of this unit center position, operational symbol＜expression asks the inner product of two vectors;

Step (4.9), the power pointing method of utilization is adjusted placement position, sets up equilibrium equation

$F_x^{\mathrm{net}}+F_x^{\mathrm{hold}}+(F_x^{\mathrm{move}}+F_x^{\mathrm{decap}})=0$------(4)

$F_y^{\mathrm{net}}+F_y^{\mathrm{hold}}+(F_y^{\mathrm{move}}+F_y^{\mathrm{decap}})=0$

Wherein

The pulling force of corresponding line length on the expression X-direction,

The pulling force of corresponding line length on the expression Y direction,

$F_x^{\mathrm{net}}=C_x\&CenterDot;x^{\&prime;}+d_x$

$F_y^{\mathrm{net}}=C_y\&CenterDot;y^{\&prime;}+d_y$

Expression makes the power that layout remains unchanged on the X-direction under the situation of the power of not scattering,

Expression makes the power that layout remains unchanged on the Y direction under the situation of the power of not scattering,

$F_x^{\mathrm{hold}}=-(C_x\&CenterDot;x^{\&prime;}+d_x)$

$F_y^{\mathrm{hold}}=-(C_y\&CenterDot;y^{\&prime;}+d_y)$

The center of unit in x and the y ' expression layout wherein,

Eliminate the power of scattering of cells overlap on the expression X-direction,

Eliminate the power of scattering of cells overlap on the expression Y direction,

$F_x^{\mathrm{move}}={\stackrel{\&CenterDot;}{C}}_x(\mathrm{\&Delta;x}+{\mathrm{\&Phi;}}_x)$

$F_y^{\mathrm{move}}={\stackrel{\&CenterDot;}{C}}_y(\mathrm{\&Delta;y}+{\mathrm{\&Phi;}}_y)$

Be a diagonal matrix, its diagonal element is represented gauze to the tension coefficient of unit on X-direction,

Be a diagonal matrix, its diagonal element is represented gauze to the tension coefficient of unit on Y direction,

The power of scattering on the expression X-direction under the decoupling capacitance influence,

The power of scattering on the expression Y direction under the decoupling capacitance influence,

$F_x^{\mathrm{decap}}=\stackrel{\&CenterDot;}{Q}(\mathrm{\&Delta;x}+\mathrm{\&beta;}\&CenterDot;\mathrm{\&gamma;}\&CenterDot;{\mathrm{\&Psi;}}_x)$

$F_y^{\mathrm{decap}}=\stackrel{\&CenterDot;}{Q}(\mathrm{\&Delta;y}+\mathrm{\&beta;}\&CenterDot;\mathrm{\&gamma;}\&CenterDot;{\mathrm{\&Psi;}}_y)$

Δ x=x-x ' wherein, Δ y=y-y ' is the adjustment amount of cell position, the computing formula substitution equation (4) above-mentioned power obtains:

$(C_x+{\stackrel{\&CenterDot;}{C}}_x+{\stackrel{\&CenterDot;}{Q}}_x)\mathrm{\&Delta;x}=-({\stackrel{\&CenterDot;}{C}}_x{\mathrm{\&Phi;}}_x+\mathrm{\&beta;}\&CenterDot;\mathrm{\&gamma;}\&CenterDot;{\mathrm{\&Psi;}}_x)$

$(C_y+{\stackrel{\&CenterDot;}{C}}_y+{\stackrel{\&CenterDot;}{Q}}_y)\mathrm{\&Delta;y}=-({\stackrel{\&CenterDot;}{C}}_y{\mathrm{\&Phi;}}_y+\mathrm{\&beta;}\&CenterDot;\mathrm{\&gamma;}\&CenterDot;{\mathrm{\&Psi;}}_y)$

In the following formula

Expression

Component on X-direction,

Expression

Component on Y direction,

Find the solution the reposition that obtains each unit center after the above-mentioned equilibrium equation;

Step (4.10) is calculated adjustment factor κ and is adjusted parameter matrix

$\stackrel{\&CenterDot;}{P}\&LeftArrow;\mathrm{\&kappa;}\left(\mathrm{\&mu;}\right)\&CenterDot;\stackrel{\&CenterDot;}{P}$

------(5)

$\stackrel{\&CenterDot;}{Q}\&LeftArrow;\mathrm{\&kappa;}\left(\mathrm{\&mu;}\right)\&CenterDot;\stackrel{\&CenterDot;}{Q}$

κ(μ)＝1+tanh(ln(μ_T/μ))

$\mathrm{\&mu;}=\frac{1}{m}\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}\sqrt{{\mathrm{\&Delta;x}}^2+\mathrm{\&Delta;}{\mathrm{<figure-callout\; label="y"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">y</figure-callout>}}^2}$

Wherein μ is the average amount of movement of all unit, μ_TCell position adjustment amount for the expectation of user's appointment;

Step (5) legalizes to the result of total arrangement

The layout of utilize the resolving method that legalizes is eliminated overlapping between the unit, and is eliminated the dislocation of unit on cell row and since in this process cell position change little, very little to the influence of power ground network performance, therefore need not to do again special processing;

Step (6) is carried out decoupling capacitance to the result after legalizing and is placed

Utilization is the final layout result coupling capacitance of adding up based on sensitivity of method, sensitivity is to consider that circuit node voltage is along with the sensitivity of receiving electric current to change, the adding decoupling capacitor can improve the sensitivity of circuit, make that the variation of receiving electric current is littler to the node voltage influence of supply network, finally obtain better power supply performance.

Experiment showed, that method optimal speed proposed by the invention is fast, it is effective to optimize, the internal memory of saving computing machine, have the ability of optimizing large-scale circuit.

Description of drawings:

Fig. 1: do not add decoupling capacitance and add decoupling capacitance voltage waveform afterwards.

Fig. 2: the gap between voltage waveform and the legal voltage waveform in violation of rules and regulations.

Fig. 3: the piecewise linearity in time-dependent current source was represented when the unit received electric current.

Fig. 4: unit in the power ground network of mesh network and the layout.

Fig. 5: the initialization layout result of example daiTest1 only being considered line length.

Fig. 6: to the 15 iteration result of example daiTest1 layout.

Fig. 7: to the total arrangement result of example daiTest1.

Fig. 8: the result after the layout of example daiTest1 legalized.

Fig. 9: traditional power is pointed to the algorithm flow of layout device and is described.

Figure 10: consider to add the power sensing placement algorithm flow process description of decoupling capacitance.

Embodiment:

The test circuit example daiTest1 of the Bookshelf form that provides with industry member does example and uses decoupling capacitance to suppress the optimization of integrated circuit electricity supply network noise with method of the present invention, now in conjunction with Figure 10 it is described in detail:

Step (1) is read in the circuit information file, makes up circuit structure

This is an input process, and the topology file of test use Bookshelf form (daiTest1.aux, daiTest1.nets, daiTes1.nodes, daiTest1.pl, daiTest1.scl, daiTest1.wts); The file daiTest1_pg.mat that receives current source of power ground network physical design parameter and unit correspondence is described, the current source that becomes when wherein receiving current source to be, in the current source library file, use and receive the piecewise linearity of current source waveform to represent (PWL), as shown in Figure 3; And set up corresponding circuit model and current source model, here the power ground network using mesh network, the model of whole power supply/network and lower floor unit is as shown in Figure 4.

Step (2) is carried out STATIC SIMULATION to the power ground network

According to the circuit topological structure of setting up in the step (1), set up STATIC SIMULATION equation GV=J according to Kirchhoff's law, wherein G is a conductance matrix, and is only relevant with electric conductivity value and circuit structure in the circuit, V is a supply node voltage vector to be asked, and J is the current vector that receives of node.Because the matrix of coefficients G of this system of equations has character sparse, symmetrical, positive definite, colleges and universities' derivation algorithm of at present existing many maturations, we adopt is a kind of method of conjugate gradient ICCG (IncompleteCholesky Conjugate Gradient) that decomposes pre-excellent matrix based on incomplete Qiao Laisiji in the pre-excellent method of conjugate gradient (PCG, Precondition Conjugate Gradient).Find the solution finish after, obtain this magnitude of voltage of each node constantly, note is made vectorial V.The voltage of note power ground network power supply pad Pad is V_Dd, V during test_DdBe set at 1.5, then to fall be exactly V to the quiescent voltage of its internal node_Dd-V_ThreSetting quiescent voltage during test, to fall threshold value be V_Thre=1.4, if falling, this quiescent voltage surpasses 0.1, then emulation finishes; Otherwise proceed the integral layout that following steps are added decoupling capacitance.

Step (3) is carried out the layout initialization

Comprise removable unit and can not mobile unit in the layout constraint file, removable unit is exactly the unit that can change its coordinate in following layout process, can not mobile unit be exactly the unit of immutable coordinate in following layout process.Comprised 1511 unit (m=1511) in the daiTest1 topology file, 1309 of wherein removable unit place it in the center of layout areas, can not mobile unit 202, place it in assigned address according to the constraint condition in the topology file.Repeating step (3.1)-(3.3) is five times then.

Step (3.1) obtains the expression formula of secondary line length according to following formula

${\mathrm{\&Gamma;}}_x=\frac{1}{2}{x}^T{C}_{x}x+d_x^{T}x+\mathrm{<figure-callout\; label="const"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">const</figure-callout>}1$

${\mathrm{\&Gamma;}}_y=\frac{1}{2}{y}^T{C}_{y}y+d_y^{T}y+\mathrm{<figure-callout\; label="const"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">const</figure-callout>}2$

Step (3.2) is found the solution system of linear equations

C_xx＝d_x

C_yy＝d_y

This equation is two systems of linear equations, and that matrix of coefficients has is sparse, the character of positive definite, symmetry, uses the method for ICCG to find the solution, and obtains x and y;

Step (3.3), x and y according to step (3.2) obtains make x '=x and y '=y, and the reposition that changes the unit is (x ', y ');

As initialization layout of the present invention, the initialization layout result as shown in Figure 5 with the above-mentioned layout result that obtains.

Step (4) is added the total arrangement of decoupling capacitance.The Duplication of regulation unit finishes less than 10% o'clock total arrangement, allows iteration at most 200 times.

Step (4.1), according to above 4.1 saving described formula initializes weights parameter:

$\mathrm{\&beta;}=\frac{2}{V_{\mathrm{dd}}-V_{\mathrm{thre}}}=\frac{2}{1.5-1.4}=20$

The cellar area parameter that provides according to following formula and Bookshelf file and receive current parameters initiation parameter matrix

Step (4.2), the Duplication Ω of computing unit.The implication of Duplication is the number percent that the element number that overlaps accounts for total element number, if Ω＜10%, then layout finishes, otherwise carries out following process.

Step (4.3) is according to the distribution density function of following formula computing unit

With

$D_{\mathrm{mod}}^{\sup }(x,y)=\frac{\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}{A}_i}{A_{\mathrm{chip}}}$

$D_{\mathrm{mod}}^{\mathrm{dem}}(x,y)=\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}{d}_{\mathrm{mod},i}\&CenterDot;R(x,y,x_i^{\&prime;}-\frac{{\mathrm{<figure-callout\; label="w\; i"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">w</figure-callout>}}_i}{2},y_i^{\&prime;}-\frac{{\mathrm{<figure-callout\; label="h\; i"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">h</figure-callout>}}_i}{2},w_i,h_i)$

$R(x,y,x_{\mathrm{ll}},y_{\mathrm{ll}},w,h)=\left\{\begin{array}{ccc}1,& \mathrm{if}& 0\&le;x-x_{\mathrm{ll}}\&le;w^0\&le;y-y_{\mathrm{ll}}\&le;\mathrm{<figure-callout\; label="h"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">h</figure-callout>}\\ 0,& \mathrm{else}& \end{array}\right.$

Step (4.4) is set up the supply and demand system of unit according to following formula, and solve potential-energy function Φ (x, y)

$(\frac{{\&PartialD;}^2}{\&PartialD;x^2}+\frac{{\&PartialD;}^2}{\&PartialD;y^2})\mathrm{\&Phi;}(x,y)=D_{\mathrm{mod}}^{\sup }(x,y)-D_{\mathrm{mod}}^{\mathrm{dem}}(x,y)$

Satisfy the Newman boundary condition$\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;n}=0$

This is a Poisson equation, the method of finding the solution is a lot, here use a kind of many grids of geometry solver DiMEPACK (M.Kowarschik and C.Wei β, " DiMEPACK-A cache-optimizedmultigrid library; " in Proc.Int.Conf.Parallel Distrib.Process.Techn.Appl., H.Arabnia, Ed., pp.425-430, Jun.2001).

Step (4.5), corresponding decoupling capacitance are set up electric density function and supply and demand system

Computing chip power on density function W (x, y) and L (x y), obtains its corresponding supply and demand function.To the power ground lattice network equation that obtains with the improved nodal method of analysis

Carry out transient analysis, obtain power ground network node voltage vector V, and the voltage vector of note voltage drop node in violation of rules and regulations is V_2s, the voltage vector that satisfies the node of voltage drop constraint is V_1s, need be V therefore to node voltage_2sThe node at place adds decoupling capacitance.Utilize the macro model method, the equation of circuit correspondence is turned to

$\left(\begin{array}{cc}{G}_{11}& G_{12}\\ G_{12}^T& G_{22}\end{array}\right)\&CenterDot;\left(\begin{array}{c}{\&Integral;}_{t_0}^{t_1}{V}_{1s}\mathrm{dt}\\ {\&Integral;}_{t_0}^{t_1}{V}_{2s}\mathrm{dt}\end{array}\right)=\left(\begin{array}{c}{\&Integral;}_{t_0}^{{\mathrm{<figure-callout\; label="t"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">t</figure-callout>}}_1}\mathrm{Jdt}\\ {\&Integral;}_{t_0}^{t_1}{\mathrm{<figure-callout\; label="J"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">J</figure-callout>}}_2\mathrm{dt}+{\&Integral;}_{t_0}^{{\mathrm{<figure-callout\; label="t"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">t</figure-callout>}}_1}\mathrm{Idt}\end{array}\right)$

According to following formula, calculate power consumption density function W and power density function L:

W＝-B^T·H^-1

$L=\left(\begin{array}{c}(V_{\mathrm{thre}}+V_1\left(t_0\right))\&CenterDot;T\\ (V_{\mathrm{thre}}+V_2\left(t_0\right))\&CenterDot;T\\ .\\ .\\ .\\ (V_{\mathrm{thre}}+V_m\left(t_0\right))\&CenterDot;T\end{array}\right)$

T=(t wherein₁-t₀)/2, the method that adopts Lagrange's interpolation are at the enterprising row interpolation in layout plane, obtain power consumption density function W (x, y) and power density function L (x, y).

Step (4.6), the Poisson equation of finding the solution electric density supply and demand system, obtain potential-energy function Ψ (x, y)

$(\frac{{\&PartialD;}^2}{\&PartialD;x^2}+\frac{{\&PartialD;}^2}{\&PartialD;y^2})\mathrm{\&Psi;}(x,y)=L(x,y)-W(x,y)$

Satisfy the Newman boundary condition$\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;n}=0$

Equally, this is a Poisson equation, also the potential-energy function Ψ that obtains electric density that finds the solution with the DiMEPACK solver (x, y).

In order to make above-mentioned Poisson equation to separate, need carry out orthogonalization to the supply and demand function,

Represent orthogonalized power density function,

Represent orthogonalized power consumption density function

$\tilde{L}(x,y)=L(x,y)-\&Integral;\&Integral;\mathrm{Ldxdy}$

$\tilde{W}(x,y)=W(x,y)-\&Integral;\&Integral;\mathrm{Wdxdy}$

Step (4.7), utilize difference method obtain potential-energy function Φ (x, y) and Ψ (x, gradient function y):

${\mathrm{\&Phi;}}_x=\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;x},$${\mathrm{\&Phi;}}_y=\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;y}$

${\mathrm{\&Psi;}}_x=\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;x},$${\mathrm{\&Psi;}}_y=\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;y}$

And to Ψ_x, Ψ_yCalculate its corresponding zoom factor γ to guarantee that cells overlap can be eliminated effectively:

${\mathrm{\&gamma;}}_i=\min (\mathrm{1,0.9}\&times;\frac{<\&dtri;{\mathrm{\&Phi;}}_i\&CenterDot;\&dtri;{\mathrm{\&Phi;}}_i>}{<{\&dtri;\mathrm{\&Phi;}}_i\&CenterDot;\&dtri;{\mathrm{\&Psi;}}_i>})$

Step (4.8), solving equation:

(C_x+C_x+Q_x)Δx＝-(C_xΦ_x+β·γ·Ψ_x)

(C_y+C_y+Q_y)Δy＝-(C_yΦ_y+β·γ·Ψ_y)

Obtain new position, unit.Above-mentioned equation remains a system of linear equations, and that matrix of coefficients has equally is sparse, the character of positive definite, symmetry, therefore uses the method for ICCG to find the solution.Layout result when Figure 6 shows that the 15 iteration, figure blue arrow is represented the displacing force that the unit is suffered.

Step (4.9), parameter control:

At first calculate adjustment factor κ and (get μ according to following formula_T=1)

κ(μ)＝1+tanh(ln(μ_T/μ))

$\mathrm{\&mu;}=\frac{1}{m}\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}\sqrt{\mathrm{\&Delta;}{x}^2+\mathrm{\&Delta;}{\mathrm{<figure-callout\; label="y"\; filenames="HSA00000165093800031.png,HSA00000165093800041.png"\; state="\{\{state\}\}">y</figure-callout>}}^2}$

New parameter matrix is set then

$\stackrel{\&CenterDot;}{P}\&LeftArrow;\mathrm{\&kappa;}\left(\mathrm{\&mu;}\right)\&CenterDot;\stackrel{\&CenterDot;}{P}$------(5)

$\stackrel{\&CenterDot;}{Q}\&LeftArrow;\mathrm{\&kappa;}\left(\mathrm{\&mu;}\right)\stackrel{\&CenterDot;}{Q}$

Repeating step (4.1)-(4.9) are no more than 10% up to Duplication, and the result after total arrangement finishes as shown in Figure 7.

Step (5) is carried out layout and is legalized

The process that legalizes mainly is each unit is corresponded to the cell row at its place, eliminates the small dislocation on the vertical direction, simultaneously overlapping the and blank on the elimination of level direction.Here (METHOD FOR LEGALIZING THE PLACEMENT OF CELLS IN ANINTEGRATED CIRCUIT LAYOUT, 2006.8.8) the middle algorithm of describing is realized to use patent US7089521B2.After layout legalizes, export the geometric position of each unit.Result after layout legalizes as shown in Figure 8.

Step (6) is added decoupling capacitance to the layout after legalizing

Add decoupling capacitor at the supply node place of power ground network, this is one of the main target that will optimize of the present invention.According to article (Dharchoudhury A, Panda R, Blaauw D, et al.Designand analysis of power distribution networks in PowerPC microprocessors.Proceedings of Design Automation Conference, 1998.738-743.) in method, carry out the interpolation of decoupling capacitor, till satisfying the voltage drop constraint, the total amount of decoupling capacitance is added in output.

The algorithm application that the present invention is proposed is in the daiTest1 circuit layout, and the decoupling capacitance total amount that needs at last to add is 358.287pf, and to the layout result of classic method, needing to add the decoupling capacitance total amount be 639.977pf.By contrast, the layout result that the present invention produced has reduced by 44.02% decoupling capacitance amount.Simultaneously, the layout result line length that produces among the present invention is that the line length 0.0860957m of 0.0858811m and conventional in layout method is more or less the same.

This algorithm realizes on the Linux server of internal memory 8G and operation that at CPU 2.33G all code utilizes C Plus Plus and Matlab hybrid programming to realize.

Claims (1)

1. use decoupling capacitance to suppress the method for integrated circuit electricity supply network noise, it is characterized in that, in computing machine, realize as follows successively:

Step (1), computing machine are read in the file that comprises power ground network design parameter and cell layout's design parameter, and power ground network design parameter comprises: the position of power ground network and line width, the position of energization pins Pin; Determine the relational structure between the node on it, initial resistivity value, capacitance and cell current source model between the node according to the position of power ground network and width, promptly the time dependent current waveform that receives of each unit correspondence is represented with PWL; In computing machine, set up the circuit model of power ground network in view of the above; Described cell layout design parameter comprises: whether the initial position that the side-play amount of pin, unit are placed on the size of each unit, the unit, the direction of unit, the zone of layout, the position and the unit of cell row can move;

Step (2), the power ground network is carried out static analysis, if falling, quiescent voltage do not meet the demands, then the power ground network is carried out whole live width adjustment, make dc voltage drop meet design requirement, add decoupling capacitance with this as next step and carry out the pacing items that elimination falls in transient voltage;

Step (3) is carried out initialization to layout, at first all transportable unit is placed into the center of layout areas, repeats following initialization step (3.1)-(3.3) five times then;

Step (3.1), use the bounding box linear model to obtain the quadratic expression of line length:

${\mathrm{\&Gamma;}}_x=\frac{1}{2}{x}^T{C}_{x}x+d_x^{T}x+\mathrm{const}1$

${\mathrm{\&Gamma;}}_y=\frac{1}{2}{y}^T{C}_{y}y+d_y^{T}y+\mathrm{const}2$

Wherein:

Γ_xAnd Γ_yBe respectively the semi-perimeter line length of X-direction and Y direction,

X represents the vector that each unit center constitutes in the cartesian coordinate system on X-direction,

Y represents the vector that each unit center constitutes in the cartesian coordinate system on X-direction,

(x, y) expression residing position, unit,

d_xBe a vector, represent the annexation on X-direction between removable unit and the fixed cell, if they have annexation, then they are at d_xThe element of middle relevant position is 1, otherwise is 0,

d_yBe a vector, represent the annexation on Y direction between removable unit and the fixed cell, if they have annexation, then they are at d_yThe element of middle relevant position is 1, otherwise is 0,

C_xBe a positive semi-definite symmetric matrix, be used for representing the annexation on X-direction between the removable unit, if between two removable unit annexation is arranged, then they are at C_xThe element of middle relevant position is 1, otherwise is 0,

C_yBe a positive semi-definite symmetric matrix, be used for representing the annexation on Y direction between the removable unit, if between two removable unit annexation is arranged, then they are at C_yThe element of middle relevant position is 1, otherwise is 0,

Const1 represents the line length constant term of directions X,

Const2 represents the line length constant term of Y direction,

The bounding box linear model is meant a minimum rectangle that comprises all summits of gauze, and its girth can be expressed as

L_n＝2(x_max-x_min+y_max-y_min)

(x wherein_Min, y_Min) be the apex coordinate in this rectangle frame lower left corner, (x_Max, y_Max) be the apex coordinate in its upper right corner;

Step (3.2), find the solution system of linear equations respectively about x and y:

C_xx＝d_x

C_yy＝d_y

This equation is two systems of linear equations, and that matrix of coefficients has is sparse, the character of positive definite, symmetry, uses the method for ICCG to find the solution, and obtains x and y;

Step (4.3.1) is calculated the object element distribution density function

$D_{\mathrm{mod}}^{\sup }(x,y)=\frac{\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}{A}_i}{A_{\mathrm{chip}}}$

The object element distribution density function

The i.e. cell distribution density function that obtains of expectation after finishing layout, wherein: A_ChipThe area of expression entire chip, A_iThe area of representing each unit;

Step (4.3.2) is calculated the density function of cell distribution in the current layout

In order to calculateHere introduce a rectangular window function

$R(x,y,x_{\mathrm{ll}},y_{\mathrm{ll}},w,h)=\begin{array}{}\end{array}\left\{\begin{array}{ccc}1,& \mathrm{if}& 0\&le;x-x_{\mathrm{ll}}\&le;w^0\&le;y-y_{\mathrm{ll}}\&le;h\\ 0,& \mathrm{else}& \end{array}\right.$

Represented whether select active cell, wherein (x, y) expression active cell position, (x_Ll, y_Ll) coordinate on summit, the lower left corner of expression rectangle, (w h) is the width and the height of this rectangle; If note active cell center be (x '_i, y '_i), the width of active cell and highly be (w_i, h_i), then set up corresponding to above-mentioned rectangular window function following formula:

$x_{\mathrm{ll}}=x_i^{\&prime;}-\frac{w_i}{2}$

$y_{\mathrm{ll}}=y_i^{\&prime;}-\frac{h_i}{2}$

At this moment the density function of cell distribution

Can calculate by following formula:

$D_{\mathrm{mod}}^{\mathrm{dem}}(x,y)=\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}{d}_{\mathrm{mod},i}\&CenterDot;R(x,y,x_i^{\&prime;}-\frac{w_i}{2},y_i^{\&prime;}-\frac{h_i}{2},w_i,h_i)$

D wherein_{Mod, i}The density of expression unit i is set to 1 under the simple scenario;

Step (4.4), the Poisson equation of finding the solution the supply and demand system that description unit distributes, obtain potential-energy function Φ (x, y), Poisson equation be shape as

Oval partial differential equation, it is as follows that the supply and demand system is described as Poisson equation:

Step (3.3), x and y according to step (3.2) obtains make x '=x and y '=y, and the reposition that changes the unit is (x ', y ');

Step (4) is added the total arrangement of decoupling capacitance;

Step (4.1), initializes weights parameter and weight matrix:

Step (4.1.1), the initializes weights parameter beta

$\mathrm{\&beta;}=\frac{2}{V_{\mathrm{dd}}-V_{\mathrm{thre}}}$

V wherein_DdBe supply voltage, V_ThreIt is the voltage drop threshold value of user's appointment;

Step (4.1.2), the initializes weights matrix

Wherein

Be layout quality control weight parameter matrix, by the area parameters A of each unit_iCalculate, m represents the total quantity of unit, i=1, and 2 ..., m;

Step (4.1.3), initialization electric weight weight matrix

Wherein

Be electric weight weight coefficient matrix in the time t, receive electric weight J by each unit_iIntegral and calculating to time t obtains;

Step (4.2), the Duplication Ω of computing unit, overlapping unit overlapping and the unit of comprising overlaps two kinds of situations, the implication of Duplication is the number percent that the element number that overlaps accounts for total element number, if Duplication is less than 10%, then layout finishes, otherwise repeats following steps;

Step (4.3), the distribution density function of computing unit

With

$(\frac{{\&PartialD;}^2}{\&PartialD;x^2}+\frac{{\&PartialD;}^2}{\&PartialD;y^2})\mathrm{\&Phi;}(x,y)=D_{\mathrm{mod}}^{\sup }(x,y)-D_{\mathrm{mod}}^{\mathrm{dem}}(x,y)$

Satisfy the Newman boundary condition$\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;n}=0$

Wherein n represents the borderline normal vector of field of definition;

Step (4.5), computing chip power on density function W (x, y) and L (x, y)

Step (4.5.1) is utilized the method for macro model, with power ground lattice network equation

Change into following form:

$\left(\begin{array}{cc}{G}_{11}& G_{12}\\ G_{12}^T& G_{22}\end{array}\right)\&CenterDot;\left(\begin{array}{c}{\&Integral;}_{t_0}^{t_1}{V}_{1s}\mathrm{dt}\\ {\&Integral;}_{t_0{V}_{2s}\mathrm{dt}}^{t_1}\end{array}\right)=\left(\begin{array}{c}{\&Integral;}_{t_0}^{t_1}{J}_1\mathrm{dt}\\ {\&Integral;}_{t_0}^{t_1}{J}_2\mathrm{dt}+{\&Integral;}_{t_0}^{t_1}\mathrm{Idt}\end{array}\right)$

Wherein:

C represents supply network node capacitor matrix,

G represents the node conductance matrix,

V represents the node voltage matrix,

J represents that node receives current matrix,

V_2sBe the node voltage vector that needs to add decoupling capacitance,

V_1sBe supply network internal node voltages vector,

J₁For the supply network internal node receives current vector,

J₂Be the current vector that receives of supply network fringe node,

I is the supply current vector of power pad Pad,

G₁₁Be the electric derived vector of supply network internal node,

G₁₂Be the conductance matrix between supply network internal node and the power pad Pad,

G₂₂Conductance matrix for power pad Pad;

Step (4.5.2), according to following steps, calculate power consumption density function W (x, y) and power density function L (x, y):

Step (4.5.2.1), the calculating voltage integral of pulse shape

There is following formula to set up simultaneously

W＝-B^T·H^-1

Wherein

The admittance matrix of expression power ground network,

$B=G_{12}^T{G}_{11}^{-1}{\&Integral;}_{t_0}^{t_1}{J}_1\mathrm{dt}-{\&Integral;}_{t_0}^{t_1}{J}_2\mathrm{dt}$The equivalent electric quantity of expression load current source;

Step (4.5.2.2) is at T=(t₁-t₀Calculate power density function L in the time of)/2

$L=\left(\begin{array}{c}(V_{\mathrm{thre}}+V_1\left(t_0\right))\&CenterDot;T\\ (V_{\mathrm{thre}}+V_2\left(t_0\right))\&CenterDot;T\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ (V_{\mathrm{thre}}+V_m\left(t_0\right))\&CenterDot;T\end{array}\right)$

V wherein_i(t₀) be t₀The voltage vector of moment unit i;

Step (4.5.2.3), utilize step (4.5.2.1) and (4.5.2.2) in the W and the L that obtain, the method that adopts Lagrange's interpolation is at the enterprising row interpolation in layout plane, obtain power consumption density function W (x, y) and power density function L (x, y);

Step (4.6) is found the solution by adding the Poisson equation that decoupling capacitance reaches the supply and demand system balancing, obtain potential-energy function Ψ (x, y)

$(\frac{{\&PartialD;}^2}{\&PartialD;x^2}+\frac{{\&PartialD;}^2}{\&PartialD;y^2})\mathrm{\&Psi;}(x,y)=L(x,y)-W(x,y)$

Satisfy the Newman boundary condition$\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;n}=0$

The supply and demand function is carried out the Poisson equation that orthogonalization is found the solution the supply and demand system afterwards, makes the supply and demand system reach balance so that add decoupling capacitance,

Represent orthogonalized power density function,

Represent orthogonalized power consumption density function

$\tilde{L}(x,y)=L(x,y)-\&Integral;\&Integral;\mathrm{Ldxdy}$

$\tilde{W}(x,y)=W(x,y)-\&Integral;\&Integral;\mathrm{Wdxdy}$

Step (4.7), according to the result of step (3.3), use the bounding box linear model to obtain the quadratic expression of current line length:

${\mathrm{\&Gamma;}}_x=\frac{1}{2}{x}^T{C}_x{x}^{\&prime;}+d_x^T{x}^{\&prime;}+\mathrm{const}1$

${\mathrm{\&Gamma;}}_y=\frac{1}{2}{y}^T{C}_y{y}^{\&prime;}+d_y^T{y}^{\&prime;}+\mathrm{const}2$

Step (4.8) is utilized difference method, the continuous variable problem is converted into the discrete variable problem so that numerical solution, obtain potential-energy function Φ (x, y) and Ψ (x, gradient function y):

${\mathrm{\&Phi;}}_x=\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;x},$${\mathrm{\&Phi;}}_y=\frac{\&PartialD;\mathrm{\&Phi;}(x,y)}{\&PartialD;y}$

${\mathrm{\&Psi;}}_x=\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;x},$${\mathrm{\&Psi;}}_y=\frac{\&PartialD;\mathrm{\&Psi;}(x,y)}{\&PartialD;y}$

And to Ψ_x, Ψ_yCalculate its corresponding zoom factor γ to guarantee that cells overlap can be eliminated effectively:

${\mathrm{\&gamma;}}_i=\min (\mathrm{1,0.9}\&times;\frac{<\&dtri;{\mathrm{\&Phi;}}_i\&CenterDot;\&dtri;{\mathrm{\&Phi;}}_i>}{<\&dtri;{\mathrm{\&Phi;}}_i\&CenterDot;\&dtri;{\mathrm{\&Psi;}}_i>})$

Wherein i is an element number,

For potential-energy function Φ (x, y) and Ψ (x, y) at the Grad of this unit center position, operational symbol＜expression asks the inner product of two vectors;

Step (4.9), the power pointing method of utilization is adjusted placement position, sets up equilibrium equation

$F_x^{\mathrm{net}}+F_x^{\mathrm{hold}}+(F_x^{\mathrm{move}}+F_x^{\mathrm{decap}})=0$------(4)

$F_y^{\mathrm{net}}+F_y^{\mathrm{hold}}+(F_y^{\mathrm{move}}+F_y^{\mathrm{decap}})=0$

Wherein

The pulling force of corresponding line length on the expression X-direction,

The pulling force of corresponding line length on the expression Y direction,

$F_x^{\mathrm{net}}=C_x\&CenterDot;x^{\&prime;}+d_x$

$F_y^{\mathrm{net}}=C_y\&CenterDot;y^{\&prime;}+d_y$

Expression makes the power that layout remains unchanged on the X-direction under the situation of the power of not scattering,

Expression makes the power that layout remains unchanged on the Y direction under the situation of the power of not scattering,

$F_x^{\mathrm{hold}}=-(C_x\&CenterDot;x^{\&prime;}+d_x)$

$F_y^{\mathrm{hold}}=-(C_y\&CenterDot;y^{\&prime;}+d_y)$

The center of unit in x ' and the y ' expression layout wherein,

Eliminate the power of scattering of cells overlap on the expression X-direction,

Eliminate the power of scattering of cells overlap on the expression Y direction,

$F_x^{\mathrm{move}}={\stackrel{\&CenterDot;}{C}}_x(\mathrm{\&Delta;x}+{\mathrm{\&Phi;}}_x)$

$F_y^{\mathrm{move}}={\stackrel{\&CenterDot;}{C}}_y(\mathrm{\&Delta;y}+{\mathrm{\&Phi;}}_y)$

Be a diagonal matrix, its diagonal element is represented gauze to the tension coefficient of unit on X-direction,

Be a diagonal matrix, its diagonal element is represented gauze to the tension coefficient of unit on Y direction,

The power of scattering on the expression X-direction under the decoupling capacitance influence,

The power of scattering on the expression Y direction under the decoupling capacitance influence,

$F_x^{\mathrm{decap}}=\stackrel{\&CenterDot;}{Q}(\mathrm{\&Delta;x}+\mathrm{\&beta;}\&CenterDot;\mathrm{\&gamma;}\&CenterDot;{\mathrm{\&Psi;}}_x)$

$F_y^{\mathrm{decap}}=\stackrel{\&CenterDot;}{Q}(\mathrm{\&Delta;y}+\mathrm{\&beta;}\&CenterDot;\mathrm{\&gamma;}\&CenterDot;{\mathrm{\&Psi;}}_y)$

Δ x=x-x ' wherein, Δ y=y-y ' is the adjustment amount of cell position, the computing formula substitution equation (4) above-mentioned power obtains:

$(C_x+{\stackrel{\&CenterDot;}{C}}_x+{\stackrel{\&CenterDot;}{Q}}_x)\mathrm{\&Delta;x}=-({\stackrel{\&CenterDot;}{C}}_x{\mathrm{\&Phi;}}_x+\mathrm{\&beta;}\&CenterDot;\mathrm{\&gamma;}\&CenterDot;{\mathrm{\&Psi;}}_x)$

$(C_y+{\stackrel{\&CenterDot;}{C}}_y+{\stackrel{\&CenterDot;}{Q}}_y)\mathrm{\&Delta;y}=-({\stackrel{\&CenterDot;}{C}}_y{\mathrm{\&Phi;}}_y+\mathrm{\&beta;}\&CenterDot;\mathrm{\&gamma;}\&CenterDot;{\mathrm{\&Psi;}}_y)$

In the following formula

Expression

Component on X-direction,

Expression

Component on Y direction is found the solution the reposition that above-mentioned equilibrium equation obtains each unit center afterwards;

Step (4.10) is calculated adjustment factor κ and is adjusted parameter matrix

$\stackrel{\&CenterDot;}{P}\&LeftArrow;\mathrm{\&kappa;}\left(\mathrm{\&mu;}\right)\&CenterDot;\stackrel{\&CenterDot;}{P}$------(5)

$\stackrel{\&CenterDot;}{Q}\&LeftArrow;\mathrm{\&kappa;}\left(\mathrm{\&mu;}\right)\&CenterDot;\stackrel{\&CenterDot;}{Q}$

κ(μ)＝1+tanh(ln(μ_T/μ))

$\mathrm{\&mu;}=\frac{1}{m}\underset{i=1}{\overset{m}{\mathrm{\&Sigma;}}}\sqrt{\mathrm{\&Delta;}{x}^2+\mathrm{\&Delta;}{y}^2}$

Wherein μ is the average amount of movement of all unit, μ_TCell position adjustment amount for the expectation of user's appointment;

Step (5) legalizes to the result of total arrangement

The layout of utilize the resolving method that legalizes is eliminated overlapping between the unit, and is eliminated the dislocation of unit on cell row;

Step (6) is carried out decoupling capacitance to the result after legalizing and is placed

Utilization is the final layout result coupling capacitance of adding up based on sensitivity of method, sensitivity is to consider that circuit node voltage is along with the sensitivity of receiving electric current to change, the adding decoupling capacitor can improve the sensitivity of circuit, make that the variation of receiving electric current is littler to the node voltage influence of supply network, finally obtain better power supply performance.

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