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CN101872377A - A Method of Using Decoupling Capacitors to Suppress Noise in Integrated Circuit Power Supply Network - Google Patents

A Method of Using Decoupling Capacitors to Suppress Noise in Integrated Circuit Power Supply Network
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CN101872377A
CN101872377ACN 201010206229CN201010206229ACN101872377ACN 101872377 ACN101872377 ACN 101872377ACN 201010206229CN201010206229CN 201010206229CN 201010206229 ACN201010206229 ACN 201010206229ACN 101872377 ACN101872377 ACN 101872377A
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蔡懿慈
周强
王晓懿
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Tsinghua University
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使用去耦合电容抑制集成电路供电网络瞬态电压降噪声的方法属于超大规模集成电路物理设计领域,尤其是瞬态电源线地线网络噪声优化的技术范畴;其特点在于,创新之处在于(1)提出了一种在布局阶段估计去耦合电容需求的快速方法;(2)提出表示芯片中去耦合电容需求的一个二维函数;(3)利用这个二维函数,对去耦合电容的需求建立一个“供需系统”,用来引导布局过程朝着有利于减小去耦合电容需求的方向进行;(4)通过将上面的模型和方法集成到一个力指向布局中,提出了一种添加去耦合电容的布局算法;实验证明,本发明的方法非常有效,能够获得在线长增长0.5%左右的代价下,使得去耦合电容总量减小35%左右的布局结果。

Figure 201010206229

The method of using decoupling capacitors to suppress the transient voltage drop noise of the integrated circuit power supply network belongs to the field of VLSI physical design, especially the technical category of transient power line ground network noise optimization; its characteristic is that the innovation lies in ( 1) A fast method for estimating the decoupling capacitor requirement in the layout stage is proposed; (2) A two-dimensional function is proposed to represent the decoupling capacitor requirement in the chip; (3) Using this two-dimensional function, the decoupling capacitor requirement Establish a "supply and demand system" to guide the layout process in a direction that is conducive to reducing the demand for decoupling capacitors; (4) By integrating the above models and methods into a force-pointed layout, an additive decoupling capacitor is proposed. Layout algorithm of coupling capacitors; experiments have proved that the method of the present invention is very effective, and can obtain a layout result in which the total amount of decoupling capacitors is reduced by about 35% at the cost of increasing the line length by about 0.5%.

Figure 201010206229

Description

Use decoupling capacitance to suppress the method for integrated circuit electricity supply network noise
Technical field
The method of using decoupling capacitance to suppress integrated circuit electricity supply network noise belongs to the technology category of transient state power lead earth cord network noise optimization in VLSI (very large scale integrated circuit) (VLSI) physical Design field, especially the physical Design field.
Background technology
The supply network of integrated circuit comprises power-line network and earth cord network (being collectively referred to as the power ground network).The power ground Network Design belongs to the distinct line screen cloth line in the integrated circuit physical Design.Mainly need to solve supply voltage noise reduction sound problem in the power ground network design.Along with the continuous progress of integrated circuit technology, the chip feature size is constantly dwindled, and the integrated level and the frequency of operation of chip increase substantially, and the operating voltage of chip constantly reduces.These all cause the power ground network noise to increase and noise margin reduces, thereby make power ground network noise reduction problem become the major issue of VLSI (very large scale integrated circuit) (VLSI) in designing.Unsuitable power ground network design can produce excessive voltage drop and voltage fluctuation, greatly influences the performance of circuit, even causes circuit malfunction, and chip can't operate as normal.Therefore, the power ground network is analyzed accurately and optimization is very important.
The voltage drop noise mainly comprises two types on the ic power earth cord network: a kind of static state or dc voltage drop (IR Drop) of being called, this voltage drop are caused by the dead resistance of power supply gauze on the power ground network.Another is called transient voltage and falls (Transient Voltage Drop), and this voltage drop is caused by stray inductance on transistorized transient current variation and the power ground network.When the elimination quiescent voltage falls, usually can adopt power ground topology optimization (Singh J., Sapatnekar S.S., Topology optimization of structured power/ground networks.Proceedings ofInternational Symposium on Physical Design, 2004.116-123.), live width optimization (Wu Xiaohai. VLSI (very large scale integrated circuit) power ground network design and optimized Algorithm research: [PhD dissertation]. Beijing: Computer Science and Technology Department of Tsing-Hua University, 2001) etc. method solve.When problem fell in transient voltage on solving the power ground network, effective method was to add decoupling capacitance the most.Along with the modern integrated circuits design becomes increasingly complex, in order to eliminate more and more serious transient voltage noise reduction sound, the decoupling capacitance amount that need add on chip is more and more.And too much decoupling capacitance can produce many adverse influences to the performance of integrated circuit (IC) chip and stability: the transistor that (1) is used for making decoupling capacitance can produce leakage current, thereby adds the quiescent dissipation that decoupling capacitance can increase entire chip significantly too much; (2) too much decoupling capacitance causes chip yield to descend cost up; (3) too much decoupling capacitance can take a large amount of chip areas, produces resource contention with other device.For a long time, the research and design personnel are seeking a kind ofly to place decoupling capacitance less as far as possible and solve the method for transient voltage noise reduction sound always.
In traditional design cycle, decoupling capacitance is generally after layout finishes, determined after the position of each module or unit, again design result is carried out the transient analysis of power ground network, as the transient voltage noise reduction sound of finding not meet design requirement, adopt method noise reduction (the Dharchoudhury A that adds decoupling capacitance, Panda R, Blaauw D, et al.Design and analysis of powerdistribution networks in PowerPC microprocessors.Proceedings of DesignAutomation Conference, 1998.738-743.).In the process of adding decoupling capacitance, for fear of the adverse effect of a large amount of decoupling capacitances, need the placement location of decoupling capacitance be optimized chip performance, use minimum decoupling capacitance to solve transient voltage noise reduction sound problem as far as possible.In order to obtain optimum decoupling capacitance laying method, the researchist has carried out deep research to this problem: document (FuJ, Luo Z, Hong X, et al.A fast decoupling capacitor budgeting algorithm for robuston-chip power delivery.Proceedings of Asia and South Pacific Design AutomationConference, 2004.505-510.) utilization is carried out the optimization of decoupling capacitance based on the mathematic programming methods of sensitivity.But this often more consuming time based on sensitivity of method, can not be applied to larger circuit.Therefore, more new algorithm is suggested to improve the efficient of decoupling capacitance optimized Algorithm.For example, document (Li H, Fan J, Qi Z, et al.Partitioning-Based Approach to Fast On-ChipDecoupling Capacitor Budgeting and Minimization.IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, 2006,25 (11): 2402-2412.) algorithm that has proposed a kind of circuit piecemeal comes huge circuit is carried out decoupling capacitance optimization; And document (Kang L, Cai Y, Zou Y, et al.Fast Decoupling CapacitorBudgeting for Power/Ground Network Using Random Walk Approach.Proceedings of Asia and South Pacific Design Automation Conference 2007.751-756.) has further improved the efficient of algorithm by the method (Random Walk) of using random walk.Document (Zhao M, Panda R, Sundareswaran S, et al.A fast on-chip decouplingcapacitance budgeting algorithm using macromodeling and linear programming.Proceedings of Design Automation Conference 2006.217-222.) has proposed the algorithm of finding the solution the decoupling capacitance optimization problem with macro model (Macro-model) and linear programming method.In addition, also be used to quicken process (the Fan J that decoupling capacitance is optimized based on the convex programming algorithm, Liao I F, Tan S XD, et al.Localized on-chip power delivery network optimization via sequence oflinear programming.Proceedings of 7th International Symposium on QualityElectronic Design, 2006.6pp.-277.).
It is pointed out that it all is after layout is finished that the inhibition method falls in above-mentioned various transient voltage, found by the power ground network simulation that transient voltage falls and do not satisfied after the power requirement, just carry out decoupling capacitance and place and optimize.Yet,,, all be difficult to the situation of the excessive transient voltage noise reduction sound of elimination in any case add decoupling capacitance after tending to appear at layout along with receiving electric current constantly to increase in the chip and supply voltage constantly reduces.At this moment, can only return layout stage even floor planning stage, the layout of chip is adjusted, repeat the transient analysis of power ground network and the process of adding decoupling capacitance then, expectation solves the problem that transient voltage falls by this design iteration.Such design iteration often will carry out several times repeatedly, has increased the design cost and the design time of chip greatly.
The reason that this design iteration occurs does not consider that just because of above-mentioned decoupling capacitance optimized Algorithm different layout result (being the different putting position in module or unit) is to power ground network power supply Effect on Performance.Module on the chip or unit need receive electric current, are the loads of power ground network.Their different putting positions obviously can cause tangible influence to the power supply performance of power ground network.Recently the researchist has had realized that this point, and has proposed some solutions.Document (Zhao S, Roy K, Koh C K.Decoupling capacitance allocation and its application to powersupply noise-aware floorplanning.IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems, 2002,21 (1): 81-92.) proposed in floor planning, to consider the method that decoupling capacitance is placed, to reduce the total area of floor planning and decoupling capacitance.And document (Kahng A B, Liu B, Wang Q.Supply voltage degradation aware analyticalplacement.Proceedings of IEEE International Conference on Computer Design, 2005.437-443.) in, quiescent voltage on the supply network falls of being used as in the layout stage optimization aim function and is integrated in the process of whole layout, falls littler layout in order to obtain quiescent voltage.But, also do not consider that at layout stage problem falls in the transient voltage of power ground network at present, and the research of decoupling capacitance optimization problem report.
The present invention proposes a kind of method that suppresses the voltage drop of power ground network transients at layout stage with decoupling capacitance.Use the layout result that this method produces, can use minimum decoupling capacitance to eliminate transient voltage noise reduction sound on the power ground network.In the present invention, at first, decoupling capacitance placement problem is converted into a linear programming problem (Zhao M by macro model (Macro-model), PandaR, Sundareswaran S, et al.A fast on-chip decoupling capacitance budgetingalgorithm using macromodeling and linear programming.Proceedings of DesignAutomation Conference, 2006.217-222.), in order to determine the demand of different layout result to decoupling capacitance.Secondly, the linear programming problem of placing by the research decoupling capacitance is shown one " electric density " (" Electric Density ") function on the chip with the demand schedule of decoupling capacitance.In fact, " electric density " function representation the size of the power supply capacity of diverse location on the chip.In general, when excessive, just illustrate that this zone needs to use decoupling capacitance further strengthen power supply capacity as " the electric density " in certain zone on the fruit chip.Therefore, " electric density " function can represent that zones of different is to the decoupling capacitance demand on the chip.And balance " electric density " function will help placing decoupling capacitance still less.Next further set up one " supply and demand system " (" Supply and Demand System ") for " electric density " function, be used for producing the power of mobile module in the layout or mobile unit, make the unit move towards the direction that helps reducing decoupling capacitance.This power and original power are pointed to layout device (Spindler P, Schlichtmann U, Johannes F M.Kraftwerk2-A Fast Force-Directed Quadratic Placement Approach Using anAccurate Net Model.IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems, 2008,27 (8): other power is taken all factors into consideration together 1398-1411.), just can obtain existing optimized line length, can reduce layout result again the decoupling capacitance demand.So-called power is pointed to the layout device, and its basic thought is to be the equivalence of the interconnection line between any two unit or the module spring, and each unit (or module) is subjected to the effect of the attractive force that other interconnecting unit (or module) applies by spring; According to Hooke's law as can be known, the size of this attractive force is directly proportional with distance between unit (or module), and the stiffness factor of spring then is the direct weight sum of phase connecting diagram between the unit (or module); Under the effect of attractive force, all interconnecting units (or module) will move along the direction of power, reach the state of energy minimum up to total system, i.e. equilibrium state, and the size of making a concerted effort that each unit this moment (or module) is subjected to is zero; And power sensing layout device allows unit (or module) move along its suffered resultant direction exactly, makes a concerted effort to reduce to till zero up to this; The placement algorithm that points to principle based on power is through for a long time development, and one is pointed to the placement algorithm flow process as shown in Figure 9 than complete modern power.Generally speaking, the present invention can produce rational layout, and need not to place too much decoupling capacitance and just can eliminate transient voltage noise reduction sound on the power ground network, reduces design iteration, reduces design cost and shortens the purpose of design time thereby reach.
We adopt the actual design example of industry member that the inventive method is tested, and table with test results is understood validity of the present invention: the present invention can make the decoupling capacitance total amount reduce about 35% under total line length only increases cost about 0.5%.And the present invention only needs short working time, can be used as the practical approach that the layout stage decoupling capacitance is optimized.
Summary of the invention
The present invention has designed a kind of method of using decoupling capacitance to suppress ic power earth cord network transient voltage noise reduction sound efficiently, in layout process, consider the placement of conventional in layout performance index (line length) and decoupling capacitance simultaneously, can obtain to help improving the layout result of power supply performance effectively.Application macro model (Macro-model) is converted into a linear programming problem with the decoupling capacitance optimization problem, thereby can determine the different demands of different layout result to decoupling capacitance apace; Use the power supply capacity of diverse location on " electric density " (" Electric Density ") function representation layout process chips, thereby the power supply load reasonably can be distributed according to power supply capacity; " supply and demand system " (" Supply andDemand System ") is used for producing the power of adjusting unit in the layout or module position, thereby makes the power supply load to move to the position of setting effectively; Power is pointed to layout device (Force-Directed Placer) and is used for traditional layout index (line length), unit or module is overlapping and the decoupling capacitance placement integrates and is optimized, thereby can keep reducing the use amount of decoupling capacitance effectively under line length and unit or the non-overlapping prerequisite of module.The decoupling capacitance that the present invention is based on these four kinds of methods realizations suppresses ic power earth cord network transient voltage noise reduction sound and has obtained good effect.
Below " electric density " function of decoupling capacitance and " supply and demand system " are illustrated.To help the layout result that decoupling capacitance is placed in order accessing, must in layout process, to produce a power of representing the decoupling capacitance demand.And, just must in the iteration each time of layout process, can both estimate the demand of decoupling capacitance in order to produce this power.The basic step of the method for quick estimating of the decoupling capacitance total amount of Ti Chuing is in the present invention:
1) method (the Zhao M of use macro model, Panda R, Sundareswaran S, et al.A faston-chip decoupling capacitance budgeting algorithm using macromodeling andlinear programming.Proceedings of Design Automation Conference, 2006.217-222.), earlier the decoupling capacitance problem of placing is converted into linear programming problem by a nonlinear optimal problem; By with the circuit equation in the decoupling capacitance optimization problem
Figure BSA00000165093700071
With voltage drop constraint V 〉=VThre(wherein: C represents supply network node capacitor matrix, and G represents the node conductance matrix, and V represents the node voltage matrix, and J represents that node receives current matrix, V to carry out linearizationThreThe voltage drop threshold value of expression user appointment), thus the decoupling capacitance optimization problem is converted into a linear programming problem.This distortion mainly comprises following three steps: at first, and note V2sBe the voltage vector on the violation area sampling point, and [t0, t1] for violating the time window of voltage drop constraint, so, can be with improved nodal voltage equation piecemealAnd it is carried out integration obtains:
G11G12G12TG22·∫t0t1V1sdt∫t0t1V2sdt=∫t0t1J1dt∫t0t1J2dt+∫t0t1Idt
Wherein: V1sBe power supply network internal node voltages vector, J1For the power supply network internal node receives current vector, J2Be the current vector that receives of power supply network fringe node, I is the supply current vector of power pad Pad, G11Be the electric derived vector of power supply network internal node, G12Be the conductance matrix between power supply network internal node and the power pad Pad, G22Conductance matrix for power pad Pad.
Secondly, use macro model to obtain the electric weight equation of transfer to above-mentioned formula
Q=H·W+B
Wherein:
Figure BSA00000165093700081
Be the electric weight that need provide from decoupling capacitance,
Figure BSA00000165093700082
Be admittance matrix, W is the voltage waveform integration
Figure BSA00000165093700083
And
Figure BSA00000165093700084
Equivalent electric quantity for load current source; At last, transient voltage is fallen constraint V 〉=VThreBe converted into linear restriction by integration about voltage waveform integration W.As shown in Figure 1, the transient voltage waveform that falls constraint requirements voltage after having added decoupling capacitance can not be lower than voltage drop threshold value VThreAccordingly, voltage waveform integration W should be less than the area of dash area among the figure.The trapezoidal area of the area of dash area under by a dotted line is similar among the figure.This is because before adding optimum decoupling capacitance, can't know the voltage curve that surrounds the dash area area.So constraint V 〉=V falls in transient voltageThreJust be converted into the voltage waveform integral constraint, thereby decoupling capacitance optimization is converted into a following linear optimization problem;
miΣi∈Sci
s.t. ------(1)
M′⊗C≥H·W+B
W≥L
0≤ci≤cmax,i
Wherein: S is the sampling set of node in violation of rules and regulations, and m=|S| represents the element number in the S set, vectorial C=[c1, c2..., cm], ciBe illustrated in decoupling capacitor and stray capacitance sum that i sampling node adds, cMax, iBe illustrated near the maximum decoupling capacitor value that is allowed i the sampling node, symbol
Figure BSA00000165093700087
Expression is multiplied each other item by item, and a T=(t clocks1-t0)/2, M ' in the following formula and L can be calculated by following formula:
M′=V1(t0)-V1(t1)V2(t0)-V2(t1)...Vm(t0)-Vm(t1),L=(Vthre+V1(t0))·T(Vthre+V2(t0))·T...(Vthre+Vm(t0))·T---(2)
2) linear programming problem of above-mentioned decoupling capacitance is converted into its dual problem (DualProblem).Because though the decoupling capacitance optimization problem so far has been converted into a linear programming problem, obtained simplifying greatly,, it is still unclear to produce what kind of influence to the decoupling capacitance total amount when chip upper module or unit are in diverse location actually.Cause the reason of this situation be module or unit on chip the position directly influence be the equivalent electric quantity B of load current source, and in the Linear Programming Problem (1), the equivalent electric quantity B of load current source has appeared at intrafascicular approximately, causes being difficult to setting up contacting directly between the position of module or unit and the decoupling capacitance total amount.For the position and the relation between the decoupling capacitance total amount that can make chip upper module or unit is more clear, the linear programming problem (1) of decoupling capacitance is converted into its dual problem
max(L-W)T·C′-CmaxT·C′′
s.t.
M′⊗(H-1·C′)-C′′≤E---(3)
H-1·C′≥0
C′≥0,C″≥0
Wherein: W=-BTH-1, C ' and C " and represent the dual variable of C respectively,
Figure BSA00000165093700094
The maximum decoupling capacitor vector that allows adding of expression, constant vector E=[1,1 ..., 1]TDuality principle according to linear programming knows that dual problem (3) has identical separating with the former linear programming problem (1) that decoupling capacitance is optimized, and has all represented the decoupling capacitance total amount of needs.And can see that from the objective function of dual problem (3) the total amount of decoupling capacitance is proportional to norm ‖ L-W ‖1In fact, vectorial L-W has represented the integration of the gap between voltage waveform in violation of rules and regulations and the legal voltage waveform in the physical sense just, as shown in Figure 2.
3) the decoupling capacitance electric weight that need provide can be used as a standard weighing the decoupling capacitance demand, and the demand of decoupling capacitance is modeled as " electric density function " on the chip.In fact, with the supply and demand system class of chip upper module or cell distribution seemingly, it is the integration of the required voltage waveform of module or unit that L and W have also represented the supply and demand of supply voltage: W; L is the integration of the power ground network voltage waveform that can provide; And the decoupling capacitance part that will remedy just of the gap between the two.And can be further by respectively to W and L interpolation obtain on entire chip " electric density function " W (x, y) and L (x, y).By paired observation, can find " electric density function " and " cell density function "
Figure BSA00000165093700101
Between similarity
W(x,y)↔Dmoddem(x,y)
L(x,y)↔Dmodsup(x,y)
4) set up corresponding supply and demand system by " electric density function " for the demand of decoupling capacitance at last.This supply and demand system by Poisson equation (shape as
Figure BSA00000165093700104
Oval partial differential equation) define potential-energy function Ψ (x, y) expression:
(∂2∂x2+∂2∂y2)Ψ(x,y)=L(x,y)-W(x,y)
Satisfy the Newman boundary condition
Figure BSA00000165093700106
Use decoupling capacitance to suppress in the method for integrated circuit electricity supply network noise, comprise and produce the standard cell placement step that helps improving power supply performance, minimizing decoupling capacitance placement total amount, it be with the area of decoupling capacitance and conventional in layout index (line length, module or cells overlap) simultaneously as optimization aim, effective method for solving that power ground network noise and layout line length are optimized is simultaneously come in the position of adopting the method for iteration constantly to adjust module in the layout or unit.It gets up method synthesis such as macro model, electric density function, supply and demand system, power sensing layout, produces to help using a small amount of decoupling capacitance to suppress the layout result of integrated circuit electricity supply network noise, obtains good optimization effect.Specifically may further comprise the steps:
Step (1), computing machine are read in the file that comprises power ground network design parameter and cell layout's design parameter, and power ground network design parameter comprises: the position of power ground and line width, the position of energization pins Pin; Determine the relational structure between the node on it, initial resistivity value, capacitance and cell current source model between the node according to the position of power ground network and width, promptly the time dependent current waveform that receives of each unit correspondence is represented with PWL; In computing machine, set up the circuit model of power ground network in view of the above; Described cell layout design parameter comprises: whether the initial position that the side-play amount of pin, unit are placed on the size of each unit, the unit, the direction of unit, the zone of layout, the position and the unit of cell row can move;
Step (2), the power ground network is carried out static analysis, if falling, quiescent voltage do not meet the demands, then the power ground network is carried out whole live width adjustment, make dc voltage drop meet design requirement, add decoupling capacitance with this as next step and carry out the pacing items that elimination falls in transient voltage;
Step (3) is carried out initialization to layout, at first all transportable unit is placed into the center of layout areas, repeats following initialization step (3.1)-(3.3) five times then;
Step (3.1), use the bounding box linear model to obtain the quadratic expression of line length:
Γx=12xTCxx+dxTx+const1
Γy=12yTCyy+dyTy+const2
Wherein:
ΓxAnd ΓyBe respectively the semi-perimeter line length of X-direction and Y direction,
X represents the vector that each unit center constitutes in the cartesian coordinate system on X-direction,
Y represents the vector that each unit center constitutes in the cartesian coordinate system on X-direction,
(x, y) expression residing position, unit,
dxBe a vector, represent the annexation on X-direction between removable unit and the fixed cell, if they have annexation, then they are at dxThe element of middle relevant position is 1, otherwise is 0,
dyBe a vector, represent the annexation on Y direction between removable unit and the fixed cell, if they have annexation, then they are at dyThe element of middle relevant position is 1, otherwise is 0,
CxBe a title matrix that positive semidefinite is right, be used for representing the annexation on X-direction between the removable unit, if between two removable unit annexation is arranged, then they are at CxThe element of middle relevant position is 1, otherwise is 0,
CyBe a title matrix that positive semidefinite is right, be used for representing the annexation on Y direction between the removable unit, if between two removable unit annexation is arranged, then they are at CyThe element of middle relevant position is 1, otherwise is 0,
Const1 represents the line length constant term of directions X,
Const2 represents the line length constant term of Y direction,
The bounding box linear model is meant a minimum rectangle that comprises all summits of gauze, and its girth can be expressed as
Ln=2(xmax-xmin+ymax-ymin)
(x whereinMin, yMin) be the apex coordinate in this rectangle frame lower left corner, (xMax, yMax) be the apex coordinate in its upper right corner;
Step (3.2), find the solution system of linear equations respectively about x and y:
Cxx=dx
Cyy=dy
This equation is two systems of linear equations, and that matrix of coefficients has is sparse, the character of positive definite, symmetry, uses the method for ICCG to find the solution, and obtains x and y;
Step (3.3), x and y according to step (3.2) obtains make x '=x and y '=y, and the reposition that changes the unit is (x ', y ');
Step (4) is added the total arrangement of decoupling capacitance;
Step (4.1), initializes weights parameter and weight matrix:
Step (4.1.1), the initializes weights parameter beta
β=2Vdd-Vthre
V whereinDdBe supply voltage, VThreIt is the voltage drop threshold value of user's appointment;
Step (4.1.2), the initializes weights matrix
Figure BSA00000165093700133
Wherein
Figure BSA00000165093700134
Be layout quality control weight parameter matrix, by the area parameters A of each unitiCalculate, m represents the total quantity of unit, i=1, and 2 ..., m;
Step (4.1.3), initialization electric weight weight matrix
Figure BSA00000165093700136
Wherein
Figure BSA00000165093700137
Be electric weight weight coefficient matrix in the time t, receive electric weight J by each unitiIntegral and calculating to time t obtains;
Step (4.2), the Duplication Ω of computing unit, overlapping unit overlapping and the unit of comprising overlaps two kinds of situations, the implication of Duplication is the number percent that the element number that overlaps accounts for total element number, if Duplication is less than 10%, then layout finishes, otherwise repeats following steps;
Step (4.3), the distribution density function of computing unitWith
Figure BSA00000165093700139
Step (4.3.1) is calculated the object element distribution density function
Dmodsup(x,y)=Σi=1mAiAchip
The object element distribution density function
Figure BSA00000165093700141
The i.e. cell distribution density function that obtains of expectation after finishing layout, wherein: AChipThe area of expression entire chip, AiThe area of representing each unit;
Step (4.3.2) is calculated the density function of cell distribution in the current layout
Figure BSA00000165093700142
In order to calculate
Figure BSA00000165093700143
Here introduce a rectangular window function
Figure BSA00000165093700144
Represented whether select active cell, wherein (x, y) expression active cell position, (xLl, yLl) coordinate on summit, the lower left corner of expression rectangle, (w h) is the width and the height of this rectangle; If note active cell center is
Figure BSA00000165093700145
The width of active cell and highly be (wi, hi), then set up corresponding to above-mentioned rectangular window function following formula:
xll=xi′-wi2
yll=yi′-hi2
At this moment the density function of cell distributionCan calculate by following formula:
Dmoddem(x,y)=Σi=1mdmod,i·R(x,y,xi′-wi2,yi′-hi2,wi,hi)
D whereinMod, iThe density of expression unit i is set to 1 under the simple scenario;
Step (4.4), the Poisson equation of finding the solution the supply and demand system that description unit distributes, obtain potential-energy function Φ (x, y), Poisson equation be shape as
Figure BSA000001650937001410
Oval partial differential equation, it is as follows that the supply and demand system is described as Poisson equation:
(∂2∂x2+∂2∂y2)Φ(x,y)=Dmodsup(x,y)-Dmoddem(x,y)
Satisfy the Newman boundary condition
Figure BSA000001650937001412
Wherein n represents the borderline normal vector of field of definition;
Step (4.5), computing chip power on density function W (x, y) and L (x, y)
Step (4.5.1) is utilized the method for macro model, with power ground lattice network equation
Figure BSA00000165093700151
Change into following form:
G11G12G12TG22·∫t0t1V1sdt∫t0t1V2sdt=∫t0t1J1dt∫t0t1J2dt+∫t0t1Idt
Wherein:
C represents supply network node capacitor matrix,
G represents the node conductance matrix,
V represents the node voltage matrix,
J represents that node receives current matrix,
V2sBe the node voltage vector that needs to add decoupling capacitance,
V1sBe supply network internal node voltages vector,
J1For the supply network internal node receives current vector,
J2Be the current vector that receives of supply network fringe node,
I is the supply current vector of power pad Pad,
G11Be the electric derived vector of supply network internal node,
G12Be the conductance matrix between supply network internal node and the power pad Pad,
G22Conductance matrix for power pad Pad;
Step (4.5.2), according to following steps, calculate power consumption density function W (x, y) and power density function L (x, y):
Step (4.5.2.1), the calculating voltage integral of pulse shape
Figure BSA00000165093700153
There is following formula to set up simultaneously
W=-BT·H-1
WhereinThe admittance matrix of expression power ground network,
Figure BSA00000165093700162
The equivalent electric quantity of expression load current source;
Step (4.5.2.2) is at T=(t1-t0Calculate power density function L in the time of)/2
L=(Vthre+V1(t0))·T(Vthre+V2(t0))·T...(Vthre+Vm(t0))·T
V whereini(t0) be t0The voltage vector of moment unit i;
Step (4.5.2.3), utilize step (4.5.2.1) and (4.5.2.1) in the W and the L that obtain, the method that adopts Lagrange's interpolation is at the enterprising row interpolation in layout plane, obtain power consumption density function W (x, y) and power density function L (x, y);
Step (4.6) is found the solution by adding the Poisson equation that decoupling capacitance reaches the supply and demand system balancing, obtain potential-energy function Ψ (x, y)
(∂2∂x2+∂2∂y2)Ψ(x,y)=L(x,y)-W(x,y)
Satisfy the Newman boundary condition
In above-mentioned Poisson equation, contract of supply L (x, y) generally can not with demand function W (x, y) complete equipilibrium, this point are that the self character by electric power system is determined, exactly because the supply and demand function can not complete equipilibrium, carry out the equilibrium of supply and demand as a supplement just need to add decoupling capacitance, and, in order to make above-mentioned Poisson equation to separate, need carry out orthogonalization to the supply and demand function
Figure BSA00000165093700166
Represent orthogonalized power density function,
Figure BSA00000165093700167
Represent orthogonalized power consumption density function
L~(x,y)=L(x,y)-∫∫Ldxdy
W~(x,y)=W(x,y)-∫∫Wdxdy
Step (4.7), according to the result of step (3.3), use the bounding box linear model to obtain the quadratic expression of current line length:
Γx=12xTCxx′+dxTx′+const1
Γy=12yTCyy′+dyTy′+const2
Step (4.8) is utilized difference method, the continuous variable problem is converted into the discrete variable problem so that numerical solution, obtain potential-energy function Φ (x, y) and Ψ (x, gradient function y):
Φx=∂Φ(x,y)∂x,Φy=∂Φ(x,y)∂y
Ψx=∂Ψ(x,y)∂x,Ψy=∂Ψ(x,y)∂y
And to Ψx, ΨyCalculate its corresponding zoom factor γ to guarantee that cells overlap can be eliminated effectively:
&gamma;i=min(1,0.9&times;<&dtri;&Phi;i&CenterDot;&dtri;&Phi;i><&dtri;&Phi;i&CenterDot;&dtri;&Psi;i>)
Wherein i is an element number, ▽ Φi, ▽ ΨiFor potential-energy function Φ (x, y) and Ψ (x, y) at the Grad of this unit center position, operational symbol<expression asks the inner product of two vectors;
Step (4.9), the power pointing method of utilization is adjusted placement position, sets up equilibrium equation
Fxnet+Fxhold+(Fxmove+Fxdecap)=0
Fynet+Fyhold+(Fymove+Fydecap)=0---(4)
Wherein
Figure BSA000001650937001710
The pulling force of corresponding line length on the expression X-direction,
Figure BSA000001650937001711
The pulling force of corresponding line length on the expression Y direction,
Fxnet=Cx&CenterDot;x&prime;+dx
Fynet=Cy&CenterDot;y&prime;+dy
Figure BSA000001650937001714
Expression makes the power that layout remains unchanged on the X-direction under the situation of the power of not scattering,
Figure BSA000001650937001715
Expression makes the power that layout remains unchanged on the Y direction under the situation of the power of not scattering,
Fxhold=-(Cx&CenterDot;x&prime;+dx)
Fyhold=-(Cy&CenterDot;y&prime;+dy)
The center of unit in x ' and the y ' expression layout wherein,
Figure BSA00000165093700181
Eliminate the power of scattering of cells overlap on the expression X-direction,
Eliminate the power of scattering of cells overlap on the expression Y direction,
Fxmove=C&CenterDot;x(&Delta;x+&Phi;x)
Fymove=C&CenterDot;y(&Delta;y+&Phi;y)
Figure BSA00000165093700185
Be a diagonal matrix, its diagonal element is represented gauze to the tension coefficient of unit on X-direction,
Be a diagonal matrix, its diagonal element is represented gauze to the tension coefficient of unit on Y direction,
Figure BSA00000165093700187
The power of scattering on the expression X-direction under the decoupling capacitance influence,
Figure BSA00000165093700188
The power of scattering on the expression Y direction under the decoupling capacitance influence,
Fxdecap=Q&CenterDot;(&Delta;x+&beta;&CenterDot;&gamma;&CenterDot;&Psi;x)
Fydecap=Q&CenterDot;(&Delta;y+&beta;&CenterDot;&gamma;&CenterDot;&Psi;y)
Δ x=x-x ' wherein, Δ y=y-y ' is the adjustment amount of cell position, the computing formula substitution equation (4) above-mentioned power obtains:
(Cx+C&CenterDot;x+Q&CenterDot;x)&Delta;x=-(C&CenterDot;x&Phi;x+&beta;&CenterDot;&gamma;&CenterDot;&Psi;x)
(Cy+C&CenterDot;y+Q&CenterDot;y)&Delta;y=-(C&CenterDot;y&Phi;y+&beta;&CenterDot;&gamma;&CenterDot;&Psi;y)
In the following formula
Figure BSA000001650937001813
ExpressionComponent on X-direction,
Figure BSA000001650937001815
Expression
Figure BSA000001650937001816
Component on Y direction is found the solution the reposition that above-mentioned equilibrium equation obtains each unit center afterwards;
Step (4.10) is calculated adjustment factor κ and is adjusted parameter matrix
Figure BSA000001650937001817
P&CenterDot;&LeftArrow;&kappa;(&mu;)&CenterDot;P&CenterDot;
Q&CenterDot;&LeftArrow;&kappa;(&mu;)&CenterDot;Q&CenterDot;---(5)
κ(μ)=1+tanh(ln(μT/μ))
&mu;=1m&Sigma;i=1m&Delta;x2+&Delta;y2
Wherein μ is the average amount of movement of all unit, μTCell position adjustment amount for the expectation of user's appointment;
Step (5) legalizes to the result of total arrangement
The layout of utilize the resolving method that legalizes is eliminated overlapping between the unit, and is eliminated the dislocation of unit on cell row and since in this process cell position change little, very little to the influence of power ground network performance, therefore need not to do again special processing;
Step (6) is carried out decoupling capacitance to the inequality after legalizing and is placed
Utilization is the final layout result coupling capacitance of adding up based on sensitivity of method, sensitivity is to consider that circuit node voltage is along with the sensitivity of receiving electric current to change, the adding decoupling capacitor can improve the sensitivity of circuit, make that the variation of receiving electric current is littler to the node voltage influence of supply network, finally obtain better power supply performance.
Experiment showed, that method optimal speed proposed by the invention is fast, it is effective to optimize, the internal memory of saving computing machine, have the ability of optimizing large-scale circuit.
Description of drawings:
Fig. 1: do not add decoupling capacitance and add decoupling capacitance voltage waveform afterwards.
Fig. 2: the gap between voltage waveform and the legal voltage waveform in violation of rules and regulations.
Fig. 3: the piecewise linearity in time-dependent current source was represented when the unit received electric current.
Fig. 4: unit in the power ground grid of mesh network and the layout.
Fig. 5: the initialization layout result of example daiTest1 only being considered line length.
Fig. 6: to the 15 iteration result of example daiTest1 layout.
Fig. 7: to the total arrangement result of example daiTest1.
Fig. 8: the result after the layout of example daiTest1 legalized.
Fig. 9: traditional power is pointed to the algorithm flow of layout device and is described.
Figure 10: consider to add the power sensing placement algorithm flow process description of decoupling capacitance.
Embodiment:
The test circuit example daiTest1 of the Bookshelf form that provides with industry member does example and uses decoupling capacitance to suppress the optimization of integrated circuit electricity supply network noise with method of the present invention, now in conjunction with Figure 10 it is described in detail:
Step (1) is read in the circuit information file, makes up circuit structure
This is an input process, and the topology file of test use Bookshelf form (daiTest1.aux, daiTest1.nets, daiTes1.nodes, daiTest1.pl, daiTest1.scl, daiTest1.wts); The file daiTest1_pg.mat that receives current source of power ground physical design parameters and unit correspondence is described, the current source that becomes when wherein receiving current source to be, in the current source library file, use and receive the piecewise linearity of current source waveform to represent (PWL), as shown in Figure 3; And set up corresponding circuit model and current source model, here the power ground network using mesh network, the model of whole power supply/network and lower floor unit is as shown in Figure 4.
Step (2) is carried out STATIC SIMULATION to the power ground network
According to the circuit topological structure of setting up in the step (1), set up STATIC SIMULATION equation GV=J according to Kirchhoff's law, wherein G is a conductance matrix, and is only relevant with electric conductivity value and circuit structure in the circuit, V is a supply node voltage vector to be asked, and J is the current vector that receives of node.Because the matrix of coefficients G of this system of equations has character sparse, symmetrical, positive definite, colleges and universities' derivation algorithm of at present existing many maturations, we adopt is a kind of method of conjugate gradient ICCG (IncompleteCholesky Conjugate Gradient) that decomposes pre-excellent matrix based on incomplete Qiao Laisiji in the pre-excellent method of conjugate gradient (PCG, Precondition Conjugate Gradient).Find the solution finish after, obtain this magnitude of voltage of each node constantly, note is made vectorial V.The voltage of note power ground net power pad Pad is VDd, V during testDdBe set at 1.5, then to fall be exactly V to the quiescent voltage of its internal nodeDd-VThreSetting quiescent voltage during test, to fall threshold value be VThre=1.4, if falling, this quiescent voltage surpasses 0.1, then emulation finishes; Otherwise proceed the integral layout that following steps are added decoupling capacitance.
Step (3) is carried out the layout initialization
Comprise removable unit and can not mobile unit in the layout constraint file, removable unit is exactly the unit that can change its coordinate in following layout process, can not mobile unit be exactly the unit of immutable coordinate in following layout process.Comprised 1511 unit (m=1511) in the daiTest1 topology file, 1309 of wherein removable unit place it in the center of layout areas, can not mobile unit 202, place it in assigned address according to the constraint condition in the topology file.Repeating step (3.1)-(3.3) is five times then.
Step (3.1) obtains the expression formula of secondary line length according to following formula
&Gamma;x=12xTCxx+dxTx+const1
&Gamma;y=12yTCyy+dyTy+const2
Step (3.2) is found the solution system of linear equations
Cxx=dx
Cyy=dy
This equation is two systems of linear equations, and that matrix of coefficients has is sparse, the character of positive definite, symmetry, uses the method for ICCG to find the solution, and obtains x and y;
Step (3.3), x and y according to step (3.2) obtains make x '=x and y '=y, and the reposition that changes the unit is (x ', y ');
As initialization layout of the present invention, the initialization layout result as shown in Figure 5 with the above-mentioned layout result that obtains.
Step (4) is added the total arrangement of decoupling capacitance.The Duplication of regulation unit finishes less than 10% o'clock total arrangement, allows iteration at most 200 times.
Step (4.1), according to above 4.1 saving described formula initializes weights parameter:
&beta;=2Vdd-Vthre=21.5-1.4=20
The cellar area parameter that provides according to following formula and Bookshelf file and receive current parameters initiation parameter matrix
Figure BSA00000165093700222
Figure BSA00000165093700223
Step (4.2), the Duplication Ω of computing unit.The implication of Duplication is the number percent that the element number that overlaps accounts for total element number, if Ω<10%, then layout finishes, otherwise carries out following process.
Step (4.3) is according to the distribution density function of following formula computing unitWith
Figure BSA00000165093700225
Dmodsup(x,y)=&Sigma;i=1mAiAchip
Dmoddem(x,y)=&Sigma;i=1mdmod,i&CenterDot;R(x,y,xi&prime;-wi2,yi&prime;-hi2,wi,hi)
Figure BSA00000165093700231
Step (4.4) is set up the supply and demand system of unit according to following formula, and solve potential-energy function Φ (x, y)
(&PartialD;2&PartialD;x2+&PartialD;2&PartialD;y2)&Phi;(x,y)=Dmodsup(x,y)-Dmoddem(x,y)
Satisfy the Newman boundary condition
Figure BSA00000165093700233
This is a Poisson equation, the method of finding the solution is a lot, here use a kind of many grids of geometry solver DiMEPACK (M.Kowarschik and C.Wei β, " DiMEPACK-A cache-optimizedmultigrid library; " in Proc.Int.Conf.Parallel Distrib.Process.Techn.Appl., H.Arabnia, Ed., pp.425-430, Jun.2001).
Step (4.5), corresponding decoupling capacitance are set up electric density function and supply and demand system
Computing chip power on density function W (x, y) and L (x y), obtains its corresponding supply and demand function.To the power ground lattice network equation that obtains with the improved nodal method of analysis
Figure BSA00000165093700234
Carry out transient analysis, obtain power ground net node voltage vector V, and the voltage vector of note voltage drop node in violation of rules and regulations is V2s, the voltage vector that satisfies the node of voltage drop constraint is V1s, need be V therefore to node voltage2sThe node at place adds decoupling capacitance.Utilize the macro model method, the equation of circuit correspondence is turned to
G11G12G12TG22&CenterDot;&Integral;t0t1V1sdt&Integral;t0t1V2sdt=&Integral;t0t1J1dt&Integral;t0t1J2dt+&Integral;t0t1Idt
According to following formula, calculate power consumption density function W and power density function L:
W=-BT·H-1
L=(Vthre+V1(t0))&CenterDot;T(Vthre+V2(t0))&CenterDot;T...(Vthre+Vm(t0))&CenterDot;T
T=(t wherein1-t0)/2, the method that adopts Lagrange's interpolation are at the enterprising row interpolation in layout plane, obtain power consumption density function W (x, y) and power density function L (x, y).
Step (4.6), the Poisson equation of finding the solution electric density supply and demand system, obtain potential-energy function Ψ (x, y)
(&PartialD;2&PartialD;x2+&PartialD;2&PartialD;y2)&Psi;(x,y)=L(x,y)-W(x,y)
Satisfy the Newman boundary condition
Figure BSA00000165093700242
Equally, this is a Poisson equation, also the potential-energy function Ψ that obtains electric density that finds the solution with the DiMEPACK solver (x, y).
In order to make above-mentioned Poisson equation to separate, need carry out orthogonalization to the supply and demand function,Represent orthogonalized power density function,
Figure BSA00000165093700244
Represent orthogonalized power consumption density function
L~(x,y)=L(x,y)-&Integral;&Integral;Ldxdy
W~(x,y)=W(x,y)-&Integral;&Integral;Wdxdy
Step (4.7), utilize difference method obtain potential-energy function Φ (x, y) and Ψ (x, gradient function y):
&Phi;x=&PartialD;&Phi;(x,y)&PartialD;x,&Phi;y=&PartialD;&Phi;(x,y)&PartialD;y
&Psi;x=&PartialD;&Psi;(x,y)&PartialD;x,&Psi;y=&PartialD;&Psi;(x,y)&PartialD;y
And to Ψx, ΨyCalculate its corresponding zoom factor γ to guarantee that cells overlap can be eliminated effectively:
&gamma;i=min(1,0.9&times;<&dtri;&Phi;i&CenterDot;&dtri;&Phi;i><&dtri;&Phi;i&CenterDot;&dtri;&Psi;i>)
Step (4.8), solving equation:
(Cx+C&CenterDot;x+Q&CenterDot;x)&Delta;x=-(C&CenterDot;x&Phi;x+&beta;&CenterDot;&gamma;&CenterDot;&Psi;x)
(Cy+C&CenterDot;y+Q&CenterDot;y)&Delta;y=-(C&CenterDot;y&Phi;y+&beta;&CenterDot;&gamma;&CenterDot;&Psi;y)
Obtain new position, unit.Above-mentioned equation remains a system of linear equations, and that matrix of coefficients has equally is sparse, the character of positive definite, symmetry, therefore uses the method for ICCG to find the solution.Layout result when Figure 6 shows that the 15 iteration, figure blue arrow is represented the displacing force that the unit is suffered.
Step (4.9), parameter control:
At first calculate adjustment factor κ and (get μ according to following formulaT=1)
κ(μ)=1+tanh(ln(μT/μ))
&mu;=1m&Sigma;i=1m&Delta;x2+&Delta;y2
New parameter matrix is set then
P&CenterDot;&LeftArrow;&kappa;(&mu;)&CenterDot;P&CenterDot;---(5)
Q&CenterDot;&LeftArrow;&kappa;(&mu;)&CenterDot;Q&CenterDot;
Repeating step (4.1)-(4.9) are no more than 10% up to Duplication, and the result after total arrangement finishes as shown in Figure 7.
Step (5) is carried out layout and is legalized
The process that legalizes mainly is each unit is corresponded to the cell row at its place, eliminates the small dislocation on the vertical direction, simultaneously overlapping the and blank on the elimination of level direction.Here (METHOD FOR LEGALIZING THE PLACEMENT OF CELLSIN AN INTEGRATED CIRCUIT LAYOUT, 2006.8.8) the middle algorithm of describing is realized to use patent US7089521B2.After layout legalizes, export the geometric position of each unit.Result after layout legalizes as shown in Figure 8.
Step (6) is added decoupling capacitance to the layout after legalizing
Add decoupling capacitor at the supply node place of power ground network, this is one of the main target that will optimize of the present invention.According to article (Dharchoudhury A, Panda R, Blaauw D, et al.Design andanalysis of power distribution networks in PowerPC microprocessors.Proceedingsof Design Automation Conference, 1998.738-743.) in method, carry out the interpolation of decoupling capacitor, till satisfying the voltage drop constraint, the total amount of decoupling capacitance is added in output.
The algorithm application that the present invention is proposed is in the daiTest1 circuit layout, and the decoupling capacitance total amount that needs at last to add is 358.287pf, and to the layout result of classic method, needing to add the decoupling capacitance total amount be 639.977pf.By contrast, the layout result that the present invention produced has reduced by 44.02% decoupling capacitance amount.Simultaneously, the layout result line length that produces among the present invention is that the line length 0.0860957m of 0.0858811m and conventional in layout method is more or less the same.
This algorithm realizes on the Linux server of internal memory 8G and operation that at CPU 2.33G all code utilizes C Plus Plus and Matlab hybrid programming to realize.

Claims (1)

Translated fromChinese
1.使用去耦合电容抑制集成电路供电网络噪声的方法,其特征在于,是在计算机中依次按如下步骤实现的:1. use decoupling capacitance to suppress the method for integrated circuit power supply network noise, it is characterized in that, is to realize by following steps successively in computer:步骤(1),计算机读入包含电源地线网络设计参数和单元布局设计参数的文件,电源地线网络设计参数包括:电源地线的位置和线宽度,供电引脚Pin的位置;根据电源地线网络的位置和宽度确定其上节点之间的关联结构、节点之间的初始电阻值、电容值、以及单元电流源模型,即各个单元对应的随时间变化的吸纳电流波形,用PWL表示;据此在计算机内建立电源地线网络的电路模型;所述单元布局设计参数包括:每个单元的尺寸、单元上引脚的偏移量、单元放置的初始位置、单元的方向、布局的区域、单元行的位置以及单元是否可以移动;Step (1), the computer reads in the file containing the design parameters of the power supply ground network and the unit layout design parameters. The design parameters of the power supply ground network include: the position and line width of the power supply ground wire, the position of the power supply pin Pin; The position and width of the line network determine the correlation structure between nodes, the initial resistance value, capacitance value between nodes, and the unit current source model, that is, the time-varying absorbing current waveform corresponding to each unit, represented by PWL; Accordingly, the circuit model of the power ground network is established in the computer; the unit layout design parameters include: the size of each unit, the offset of the pins on the unit, the initial position of the unit placement, the direction of the unit, and the area of the layout , the position of the cell row and whether the cell can be moved;步骤(2),对电源地线网络进行静态分析,如果静态电压降不满足要求,则对电源地线网络进行整体的线宽调整,使得直流电压降满足设计要求,以此作为下一步添加去耦合电容进行瞬态电压降消除的基本条件;Step (2), conduct static analysis on the power supply ground network, if the static voltage drop does not meet the requirements, then adjust the overall line width of the power supply ground network, so that the DC voltage drop meets the design requirements, and add it as the next step The basic conditions for the coupling capacitor to eliminate the transient voltage drop;步骤(3),对布局进行初始化,首先将所有可以移动的单元放置到布局区域的中心位置,然后重复下面的初始化步骤(3.1)-(3.3)五次;Step (3), initialize the layout, first place all movable units in the center of the layout area, and then repeat the following initialization steps (3.1)-(3.3) five times;步骤(3.1),使用边界框线长模型得到线长的二次表达式:Step (3.1), use the bounding box line length model to obtain the quadratic expression of the line length:&Gamma;&Gamma;xx==1122xxTTCCxxxx++ddxxTTxx++constconst11&Gamma;&Gamma;ythe y==1122ythe yTTCCythe yythe y++ddythe yTTythe y++constconst22其中:in:Γx和Γy分别是X轴方向和Y轴方向的半周长线长,Γx and Γy are the half-perimeter line lengths in the X-axis direction and the Y-axis direction, respectively,x表示笛卡尔坐标系中各个单元中心在X轴方向上构成的向量,x represents the vector formed by the center of each unit in the X-axis direction in the Cartesian coordinate system,y表示笛卡尔坐标系中各个单元中心在X轴方向上构成的向量,y represents the vector formed by the center of each unit in the X-axis direction in the Cartesian coordinate system,(x,y)表示单元所处的位置,(x, y) indicates the location of the unit,dx是一个向量,表示可移动单元与固定单元之间在X轴方向上的连接关系,如果它们有连接关系,则它们在dx中相应位置的元素为1,否则为0,dx is a vector, which represents the connection relationship between the movable unit and the fixed unit in the X-axis direction. If they have a connection relationship, the elements at their corresponding positions in dx are 1, otherwise they are 0.dy是一个向量,表示可移动单元与固定单元之间在Y轴方向上的连接关系,如果它们有连接关系,则它们在dy中相应位置的元素为1,否则为0,dy is a vector, which represents the connection relationship between the movable unit and the fixed unit in the direction of the Y axis. If they have a connection relationship, the elements at their corresponding positions in dy are 1, otherwise they are 0.Cx是一个半正定对的称矩阵,用来表示可移动单元之间在X轴方向上的连接关系,如果两个可移动单元之间有连接关系,则它们在Cx中相应位置的元素为1,否则为0,Cx is a symmetric matrix of positive semi-definite pairs, which is used to represent the connection relationship between the movable units in the X-axis direction. If there is a connection relationship between two movable units, the elements at their corresponding positions in Cx is 1, otherwise it is 0,Cy是一个半正定对的称矩阵,用来表示可移动单元之间在Y轴方向上的连接关系,如果两个可移动单元之间有连接关系,则它们在Cy中相应位置的元素为1,否则为0,Cy is a symmetric matrix of a positive semi-definite pair, which is used to represent the connection relationship between the movable units in the Y-axis direction. If there is a connection relationship between two movable units, the elements at their corresponding positions in Cy is 1, otherwise it is 0,const1表示X方向的线长常数项,const1 represents the line length constant item in the X direction,const2表示Y方向的线长常数项,const2 represents the line length constant item in the Y direction,边界框线长模型是指包含线网所有顶点的一个最小矩形,其周长可表示为The bounding box line length model refers to a minimum rectangle that contains all the vertices of the line network, and its perimeter can be expressed asLn=2(xmax-xmin+ymax-ymin)Ln =2(xmax -xmin +ymax -ymin )其中(xmin,ymin)是该矩形框左下角的顶点坐标,(xmax,ymax)是其右上角的顶点坐标;Wherein (xmin , ymin ) is the vertex coordinates of the lower left corner of the rectangle, (xmax , ymax ) is the vertex coordinates of the upper right corner;步骤(3.2),分别求解关于x和y的线性方程组:Step (3.2), solve the linear equations about x and y respectively:Cxx=dxCx x = dxCyy=dyCy y = dy该方程是两个线性方程组,系数矩阵具有稀疏、正定、对称的性质,使用ICCG的方法求解,得到x和y;The equation is a system of two linear equations, the coefficient matrix has the properties of sparse, positive definite, and symmetric, and it is solved by ICCG method to obtain x and y;步骤(3.3),根据步骤(3.2)得到的x和y,令x′=x和y′=y,改变单元的新位置为(x′,y′);Step (3.3), according to x and y that step (3.2) obtains, make x'=x and y'=y, change the new position of unit to be (x', y');步骤(4),进行添加去耦合电容的总体布局;Step (4), carry out the overall layout of adding decoupling capacitor;步骤(4.1),初始化权重参数和权重矩阵:Step (4.1), initialize weight parameters and weight matrix:步骤(4.1.1),初始化权重参数βStep (4.1.1), initialize the weight parameter β&beta;&beta;==22VVdddd--VVthrethere其中Vdd是电源电压,Vthre是用户指定的电压降阈值;whereVdd is the supply voltage andVthre is the user-specified voltage drop threshold;步骤(4.1.2),初始化权重矩阵
Figure FSA00000165093600032
Step (4.1.2), initialize the weight matrix
Figure FSA00000165093600032
Figure FSA00000165093600033
Figure FSA00000165093600033
其中
Figure FSA00000165093600034
是布局质量控制权重参数矩阵,由每个单元的面积参数Ai计算得到,m表示单元的总数量,i=1,2,...,m;
in
Figure FSA00000165093600034
is the layout quality control weight parameter matrix, calculated from the area parameter Ai of each unit, m represents the total number of units, i=1, 2, ..., m;
步骤(4.1.3),初始化电量权重矩阵Step (4.1.3), initialize the power weight matrix
Figure FSA00000165093600036
Figure FSA00000165093600036
其中为时间t内电量权重系数矩阵,由每个单元的吸纳电量Ji对时间t的积分计算得到;in is the power weight coefficient matrix within time t, which is calculated by integrating the absorbed power Ji of each unit with respect to time t;步骤(4.2),计算单元的重叠率Ω,重叠包括单元交叠和单元重合两种情况,重叠率的含义是发生重叠的单元数量占总单元数量的百分比,如果重叠率小于10%,则布局结束,否则重复以下步骤;Step (4.2), calculate the overlap rate Ω of the unit, overlap includes two cases of unit overlap and unit overlap, the meaning of the overlap rate is the percentage of the number of overlapping units in the total number of units, if the overlap rate is less than 10%, the layout End, otherwise repeat the following steps;步骤(4.3),计算单元的分布密度函数
Figure FSA00000165093600042
Step (4.3), calculate the distribution density function of the unit and
Figure FSA00000165093600042
步骤(4.3.1),计算目标单元分布密度函数
Figure FSA00000165093600043
Step (4.3.1), calculate the target unit distribution density function
Figure FSA00000165093600043
DD.modmodsupsup((xx,,ythe y))==&Sigma;&Sigma;ii==11mmAAiiAAchipchip目标单元分布密度函数即在完成布局后期望得到的单元分布密度函数,其中:Achip表示整个芯片的面积,Ai表示各单元的面积;target unit distribution density function That is, the cell distribution density function expected to be obtained after the layout is completed, where: Achip represents the area of the entire chip, and Ai represents the area of each cell;步骤(4.3.2),计算当前布局中单元分布的密度函数Step (4.3.2), calculate the density function of the cell distribution in the current layout为了计算
Figure FSA00000165093600047
这里引入一个矩形窗函数
to calculate
Figure FSA00000165093600047
Here introduces a rectangular window function
Figure FSA00000165093600048
Figure FSA00000165093600048
表示了是否选择当前单元,其中(x,y)表示当前单元位置,(xll,yll)表示矩形的左下角顶点的坐标,(w,h)是该矩形的宽度和高度;如果记当前单元中心位置为当前单元的宽度和高度为(wi,hi),则对应于上述矩形窗函数下式成立:Indicates whether to select the current unit, where (x, y) indicates the position of the current unit, (xll , yll ) indicates the coordinates of the lower left vertex of the rectangle, (w, h) is the width and height of the rectangle; if the current The center of the unit is The width and height of the current unit are (wi , hi ), then the following equation is established corresponding to the above rectangular window function:xxllll==xxii&prime;&prime;--wwii22ythe yllll==ythe yii&prime;&prime;--hhii22这时单元分布的密度函数可由下式计算:Then the density function of the unit distribution It can be calculated by the following formula:DD.modmoddemdem((xx,,ythe y))==&Sigma;&Sigma;ii==11mmddmodmod,,ii&CenterDot;&Center Dot;RR((xx,,ythe y,,xxii&prime;&prime;--wwii22,,ythe yii&prime;&prime;--hhii22,,wwii,,hhii))其中dmod,i表示单元i的密度,简单情况下设置为1;where dmod, i represents the density of unit i, which is set to 1 in simple cases;步骤(4.4),求解描述单元分布的供需系统的泊松方程,得到势能函数Φ(x,y),泊松方程是形如
Figure FSA000001650936000414
的椭圆偏微分方程,供需系统描述成泊松方程如下:
Step (4.4), solving the Poisson equation describing the supply and demand system of unit distribution, and obtaining the potential energy function Φ(x, y), the Poisson equation is in the form of
Figure FSA000001650936000414
The elliptic partial differential equation, the supply and demand system is described as a Poisson equation as follows:
((&PartialD;&PartialD;22&PartialD;&PartialD;xx22++&PartialD;&PartialD;22&PartialD;&PartialD;ythe y22))&Phi;&Phi;((xx,,ythe y))==DD.modmodsupsup((xx,,ythe y))--DD.modmoddemdem((xx,,ythe y))满足纽曼边界条件Satisfy the Newman boundary condition其中n表示定义域边界上的法向量;where n represents the normal vector on the boundary of the domain of definition;步骤(4.5),计算芯片上电密度函数W(x,y)和L(x,y)Step (4.5), calculate the on-chip electric density function W(x, y) and L(x, y)步骤(4.5.1),利用宏模型的方法,将电源地线网络电路方程
Figure FSA00000165093600053
化成如下形式:
In step (4.5.1), using the macro model method, the circuit equation of the power ground wire network
Figure FSA00000165093600053
into the following form:
GG1111GG1212GG1212TTGG22twenty two&CenterDot;&CenterDot;&Integral;&Integral;tt00tt11VV11sthe sdtdt&Integral;&Integral;tt00tt11VV22sthe sdtdt==&Integral;&Integral;tt00tt11JJ11dtdt&Integral;&Integral;tt00tt11JJ22dtdt++&Integral;&Integral;tt00tt11IdtIdt其中:in:C表示供电网络节点电容矩阵,C represents the node capacitance matrix of the power supply network,G表示节点电导矩阵,G represents the node conductance matrix,V表示节点电压矩阵,V represents the node voltage matrix,J表示节点吸纳电流矩阵,J represents the node absorbing current matrix,V2s是需要添加去耦合电容的节点电压向量,V2s is the node voltage vector that needs to add decoupling capacitors,V1s为供电网络内部节点电压向量,V1s is the internal node voltage vector of the power supply network,J1为供电网络内部节点吸纳电流向量,J1 is the current vector absorbed by the internal nodes of the power supply network,J2为供电网络边缘节点的吸纳电流向量,J2 is the sink current vector of the edge node of the power supply network,I为供电焊盘Pad的供电电流向量,I is the supply current vector of the power supply pad Pad,G11为供电网络内部节点的电导向量,G11 is the conductance vector of internal nodes of the power supply network,G12为供电网络内部节点与供电焊盘Pad之间的电导矩阵,G12 is the conductance matrix between the internal nodes of the power supply network and the power supply pad Pad,G22为供电焊盘Pad的电导矩阵;G22 is the conductance matrix of the power supply pad Pad;步骤(4.5.2),按照以下步骤,计算耗电密度函数W(x,y)和供电密度函数L(x,y):In step (4.5.2), calculate power consumption density function W(x, y) and power supply density function L(x, y) according to the following steps:步骤(4.5.2.1),计算电压波形积分
Figure FSA00000165093600061
同时有下式成立
Step (4.5.2.1), calculate the integral of the voltage waveform
Figure FSA00000165093600061
At the same time, the following formula is established
W=-BT·H-1W=-BT H-1其中
Figure FSA00000165093600062
表示电源地线网络的导纳矩阵,
Figure FSA00000165093600063
表示负载电流源的等效电量;
in
Figure FSA00000165093600062
represents the admittance matrix of the power ground network,
Figure FSA00000165093600063
Indicates the equivalent power of the load current source;
步骤(4.5.2.2),在T=(t1-t0)/2时间内计算供电密度函数LStep (4.5.2.2), calculate the power supply density function L within T=(t1-t0 )/2 timeLL==((VVthrethere++VV11((tt00))))&CenterDot;&Center Dot;TT((VVthrethere++VV22((tt00))))&CenterDot;&CenterDot;TT......((VVthrethere++VVmm((tt00))))&CenterDot;&Center Dot;TT其中Vi(t0)为t0时刻单元i的电压向量;Where Vi (t0 ) is the voltage vector of unit i at time t0 ;步骤(4.5.2.3),利用步骤(4.5.2.1)和(4.5.2.1)中得到的W和L,采用拉格朗日插值的方法在布局平面上进行插值,得到耗电密度函数W(x,y)和供电密度函数L(x,y);In step (4.5.2.3), use W and L obtained in steps (4.5.2.1) and (4.5.2.1), and use Lagrangian interpolation method to perform interpolation on the layout plane to obtain the power consumption density function W(x , y) and supply density function L(x, y);步骤(4.6),求解通过添加去耦合电容来达到供需系统平衡的泊松方程,得到势能函数Ψ(x,y)Step (4.6), solving the Poisson equation that achieves the balance of the supply and demand system by adding decoupling capacitors, and obtaining the potential energy function Ψ(x, y)((&PartialD;&PartialD;22&PartialD;&PartialD;xx22++&PartialD;&PartialD;22&PartialD;&PartialD;ythe y22))&Psi;&Psi;((xx,,ythe y))==LL((xx,,ythe y))--WW((xx,,ythe y))满足纽曼边界条件
Figure FSA00000165093600066
Satisfy the Newman boundary condition
Figure FSA00000165093600066
对供需函数进行正交化之后求解供需系统的泊松方程,以便于添加去耦合电容使得供需系统达到平衡,
Figure FSA00000165093600067
表示正交化的供电密度函数,
Figure FSA00000165093600068
表示正交化的耗电密度函数
After orthogonalizing the supply and demand function, solve the Poisson equation of the supply and demand system in order to add decoupling capacitors to make the supply and demand system reach equilibrium.
Figure FSA00000165093600067
Represents the orthogonalized supply density function,
Figure FSA00000165093600068
Represents the orthogonalized power consumption density function
LL~~((xx,,ythe y))==LL((xx,,ythe y))--&Integral;&Integral;&Integral;&Integral;LdxdyLdxdyWW~~((xx,,ythe y))==WW((xx,,ythe y))--&Integral;&Integral;&Integral;&Integral;Wdxdywxya步骤(4.7),根据步骤(3.3)的结果,使用边界框线长模型得到当前线长的二次表达式:Step (4.7), according to the result of step (3.3), use the bounding box line length model to obtain the quadratic expression of the current line length:&Gamma;&Gamma;xx==1122xxTTCCxxxx&prime;&prime;++ddxxTTxx&prime;&prime;++constconst11&Gamma;&Gamma;ythe y==1122ythe yTTCCythe yythe y&prime;&prime;++ddythe yTTythe y&prime;&prime;++constconst22步骤(4.8),利用差分方法,将连续变量问题转化为离散变量问题以便于数值求解,得到势能函数Φ(x,y)和Ψ(x,y)的梯度函数:In step (4.8), using the difference method, the continuous variable problem is transformed into a discrete variable problem for numerical solution, and the gradient functions of the potential energy functions Φ(x, y) and Ψ(x, y) are obtained:&Phi;&Phi;xx==&PartialD;&PartialD;&Phi;&Phi;((xx,,ythe y))&PartialD;&PartialD;xx,,&Phi;&Phi;ythe y==&PartialD;&PartialD;&Phi;&Phi;((xx,,ythe y))&PartialD;&PartialD;ythe y&Psi;&Psi;xx==&PartialD;&PartialD;&Psi;&Psi;((xx,,ythe y))&PartialD;&PartialD;xx,,&Psi;&Psi;ythe y==&PartialD;&PartialD;&Psi;&Psi;((xx,,ythe y))&PartialD;&PartialD;ythe y并对Ψx,Ψy计算其对应的缩放因子γ以保证单元重叠能够被有效地消除:And calculate the corresponding scaling factor γ for Ψx , Ψy to ensure that unit overlap can be effectively eliminated:&gamma;&gamma;ii==minmin((1,0.91,0.9&times;&times;<<&dtri;&dtri;&Phi;&Phi;ii&CenterDot;&Center Dot;&dtri;&dtri;&Phi;&Phi;ii>><<&dtri;&dtri;&Phi;&Phi;ii&CenterDot;&CenterDot;&dtri;&dtri;&Psi;&Psi;ii>>))其中i为单元编号,▽Φi,▽Ψi为势能函数Φ(x,y)和Ψ(x,y)在该单元中心位置处的梯度值,运算符<·>表示求两个向量的内积;Where i is the unit number, ▽Φi , ▽Ψi are the gradient values of the potential energy functions Φ(x, y) and Ψ(x, y) at the center of the unit, and the operator <·> means to find the two vectors Inner product;步骤(4.9),利用力指向方法来调整布局位置,建立力平衡方程Step (4.9), use the force pointing method to adjust the layout position and establish the force balance equationFfxxnetnet++Ffxxholdhold++((Ffxxmovemove++Ffxxdecapdecap))==00Ffythe ynetnet++Ffythe yholdhold++((Ffythe ymovemove++Ffythe ydecapdecap))==00------((44))其中
Figure FSA000001650936000711
表示X轴方向上对应线长的拉力,
in
Figure FSA000001650936000711
Indicates the pulling force corresponding to the line length in the X-axis direction,
Figure FSA000001650936000712
表示Y轴方向上对应线长的拉力,
Figure FSA000001650936000712
Indicates the pulling force corresponding to the line length in the Y-axis direction,
Ffxxnetnet==CCxx&CenterDot;&Center Dot;xx&prime;&prime;++ddxxFfythe ynetnet==CCythe y&CenterDot;&Center Dot;ythe y&prime;&prime;++ddythe y
Figure FSA000001650936000715
表示X轴方向上使得布局在没有散开力的情况下保持不变的力,
Figure FSA000001650936000715
Indicates the force in the X-axis direction that keeps the layout constant without spreading out,
Figure FSA000001650936000716
表示Y轴方向上使得布局在没有散开力的情况下保持不变的力,
Figure FSA000001650936000716
Indicates the force in the Y-axis direction that keeps the layout constant without spreading out,
Ffxxholdhold==--((CCxx&CenterDot;&Center Dot;xx&prime;&prime;++ddxx))Ffythe yholdhold==--((CCythe y&CenterDot;&Center Dot;ythe y&prime;&prime;++ddythe y))其中x′和y′表示布局中单元的中心位置,where x' and y' represent the center position of the cell in the layout,表示X轴方向上消除单元重叠的散开力, Indicates the spreading force to eliminate element overlap in the X-axis direction,
Figure FSA00000165093600084
表示Y轴方向上消除单元重叠的散开力,
Figure FSA00000165093600084
Indicates the spreading force to eliminate cell overlap in the Y-axis direction,
Ffxxmovemove==CC&CenterDot;&Center Dot;xx((&Delta;x&Delta;x++&Phi;&Phi;xx))Ffythe ymovemove==CC&CenterDot;&Center Dot;ythe y((&Delta;y&Delta;y++&Phi;&Phi;ythe y))是一个对角矩阵,其对角元素表示线网对单元在X轴方向上的拉力系数, is a diagonal matrix, and its diagonal elements represent the tension coefficients of the line-network pair elements in the X-axis direction,是一个对角矩阵,其对角元素表示线网对单元在Y轴方向上的拉力系数, is a diagonal matrix, and its diagonal elements represent the tension coefficients of the line-network pair elements in the Y-axis direction,
Figure FSA00000165093600089
表示X轴方向上去耦合电容影响下的散开力,
Figure FSA00000165093600089
Indicates the spreading force under the influence of the decoupling capacitor in the X-axis direction,
Figure FSA000001650936000810
表示Y轴方向上去耦合电容影响下的散开力,
Figure FSA000001650936000810
Indicates the spreading force under the influence of the decoupling capacitor in the Y-axis direction,
Ffxxdecapdecap==QQ&CenterDot;&Center Dot;((&Delta;x&Delta;x++&beta;&beta;&CenterDot;&CenterDot;&gamma;&gamma;&CenterDot;&Center Dot;&Psi;&Psi;xx))Ffythe ydecapdecap==QQ&CenterDot;&Center Dot;((&Delta;y&Delta;y++&beta;&beta;&CenterDot;&Center Dot;&gamma;&gamma;&CenterDot;&Center Dot;&Psi;&Psi;ythe y))其中Δx=x-x′,Δy=y-y′为单元位置的调整量,把上述力的计算公式代入方程(4),得到:Among them, Δx=x-x′, Δy=y-y′ is the adjustment amount of the unit position, and the calculation formula of the above force is substituted into equation (4) to obtain:((CCxx++CC&CenterDot;&Center Dot;xx++QQ&CenterDot;&CenterDot;xx))&Delta;x&Delta;x==--((CC&CenterDot;&CenterDot;xx&Phi;&Phi;xx++&beta;&beta;&CenterDot;&CenterDot;&gamma;&gamma;&CenterDot;&CenterDot;&Psi;&Psi;xx))((CCythe y++CC&CenterDot;&Center Dot;ythe y++QQ&CenterDot;&Center Dot;ythe y))&Delta;y&Delta;y==--((CC&CenterDot;&Center Dot;ythe y&Phi;&Phi;ythe y++&beta;&beta;&CenterDot;&Center Dot;&gamma;&gamma;&CenterDot;&CenterDot;&Psi;&Psi;ythe y))上式中
Figure FSA000001650936000815
表示
Figure FSA000001650936000816
在X轴方向上的分量,
Figure FSA000001650936000817
表示
Figure FSA000001650936000818
在Y轴方向上的分量,求解上述力平衡方程之后得到各单元中心的新位置;
In the above formula
Figure FSA000001650936000815
express
Figure FSA000001650936000816
component in the x-axis direction,
Figure FSA000001650936000817
express
Figure FSA000001650936000818
For the component in the Y-axis direction, the new position of the center of each unit is obtained after solving the above force balance equation;
步骤(4.10),计算调整因子κ来调整参数矩阵Step (4.10), calculate the adjustment factor κ to adjust the parameter matrixPP&CenterDot;&CenterDot;&LeftArrow;&LeftArrow;&kappa;&kappa;((&mu;&mu;))&CenterDot;&CenterDot;PP&CenterDot;&Center Dot;QQ&CenterDot;&Center Dot;&LeftArrow;&LeftArrow;&kappa;&kappa;((&mu;&mu;))&CenterDot;&Center Dot;QQ&CenterDot;&Center Dot;------((55))κ(μ)=1+tanh(ln(μT/μ))κ(μ)=1+tanh(ln(μT /μ))&mu;&mu;==11mm&Sigma;&Sigma;ii==11mm&Delta;&Delta;xx22++&Delta;&Delta;ythe y22其中μ为所有单元的平均移动量,μT为用户指定的期望的单元位置调整量;Among them, μ is the average movement of all units, and μT is the expected unit position adjustment specified by the user;步骤(5),对总体布局的结果进行合法化Step (5), legalize the result of the overall layout利用解析的布局合法化方法,消除单元之间的重叠,并且消除单元在单元行上的错位;Eliminate the overlap between cells and the misalignment of cells on the cell row by using the analytical layout legalization method;步骤(6),对合法化后的不均进行去耦合电容放置Step (6), place a decoupling capacitor on the legalized unevenness利用基于灵敏度的方法为最终的布局结果加上去耦合电容,灵敏度是考虑电路节点电压随着吸纳电流变化的敏感程度,加入去耦电容可以改善电路的灵敏度,使得吸纳电流的变化对供电网络的节点电压影响更小,最终得到更好的供电性能。Use the method based on sensitivity to add decoupling capacitors to the final layout results. Sensitivity is to consider the sensitivity of the circuit node voltage to the change of the absorbing current. Adding decoupling capacitors can improve the sensitivity of the circuit, so that the change of absorbing current will affect the nodes of the power supply network. The voltage effect is less, resulting in better power delivery performance.
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Cited By (19)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN102063536A (en)*2010-12-172011-05-18清华大学Collaborative design method for power/ground network and layout planning based on pattern matching
CN102646143A (en)*2011-11-302012-08-22清华大学 Method and system for constructing conductance matrix in on-chip power supply network simulation
CN105808807A (en)*2014-12-312016-07-27新思科技有限公司Electro-migration verification for advanced semiconductor technology
CN107506526A (en)*2017-07-192017-12-22清华大学Supply network optimization method on a kind of piece
CN107577849A (en)*2017-08-102018-01-12西安电子科技大学Power distribution network design method based on fast electric pressure drop parser
CN108089624A (en)*2016-11-212018-05-29龙芯中科技术有限公司The compensation method of chip internal dynamic pressure drop and device
CN108694262A (en)*2017-04-112018-10-23中兴通讯股份有限公司A kind of decoupling capacitor optimization method and device
CN108763777A (en)*2018-05-302018-11-06福州大学VLSI global wiring method for establishing model based on Poisson's equation explicit solution
CN110348039A (en)*2019-04-302019-10-18北京理工大学A kind of decoupling capacitor design method for printed circuit board
CN110781642A (en)*2019-10-162020-02-11蔚复来(浙江)科技股份有限公司 A method of improving power supply noise based on frequency domain
CN110940944A (en)*2019-12-042020-03-31厦门大学J coupling removing method for magnetic resonance signals based on deep learning
CN111063670A (en)*2018-10-172020-04-24奇景光电股份有限公司 Circuit wiring method, circuit wiring system, and integrated circuit
CN112131831A (en)*2020-11-252020-12-25北京智芯微电子科技有限公司Multi-power domain layout method and storage medium
TWI717564B (en)*2016-12-132021-02-01台灣積體電路製造股份有限公司Method and system for estimating power supply noise of power distribution network (pdn) of circuit design
CN113505095A (en)*2021-07-302021-10-15上海壁仞智能科技有限公司System-on-chip and integrated circuit with multi-core out-of-phase processing
CN113609626A (en)*2021-05-202021-11-05山东云海国创云计算装备产业创新中心有限公司Voltage drop violation repairing method and related device
WO2023226073A1 (en)*2022-05-242023-11-30长鑫存储技术有限公司Evaluation method and device for capacitor requirement in power delivery network
CN117272915A (en)*2023-11-172023-12-22飞腾信息技术有限公司Integrated circuit design method, design device and related equipment
CN118569183A (en)*2024-08-022024-08-30杭州芯晓电子科技有限公司 A method for optimizing power network decoupling capacitors based on gradient descent algorithm

Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
WO2003030477A2 (en)*2001-10-012003-04-10Ipwireless, Inc.Single user detection using a fir filter
CN1431704A (en)*2003-02-282003-07-23清华大学Solving method for transient analysis of power source network based on equivalent circuit
CN1523662A (en)*2003-09-122004-08-25清华大学 A Fast Method for Noise Optimization of IC Power Supply Network Using Decoupling Capacitors
CN1564321A (en)*2004-03-262005-01-12清华大学High speed high precision transient simulation method able to process tree net hybrid power supply structure in VLSI

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
WO2003030477A2 (en)*2001-10-012003-04-10Ipwireless, Inc.Single user detection using a fir filter
CN1431704A (en)*2003-02-282003-07-23清华大学Solving method for transient analysis of power source network based on equivalent circuit
CN1523662A (en)*2003-09-122004-08-25清华大学 A Fast Method for Noise Optimization of IC Power Supply Network Using Decoupling Capacitors
CN1564321A (en)*2004-03-262005-01-12清华大学High speed high precision transient simulation method able to process tree net hybrid power supply structure in VLSI

Cited By (29)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN102063536A (en)*2010-12-172011-05-18清华大学Collaborative design method for power/ground network and layout planning based on pattern matching
CN102063536B (en)*2010-12-172012-11-14清华大学Collaborative design method for power/ground network and layout planning based on pattern matching
CN102646143A (en)*2011-11-302012-08-22清华大学 Method and system for constructing conductance matrix in on-chip power supply network simulation
CN102646143B (en)*2011-11-302014-03-26清华大学Conductance matrix construction method and system in simulation of on-chip power supply network
CN105808807A (en)*2014-12-312016-07-27新思科技有限公司Electro-migration verification for advanced semiconductor technology
CN108089624B (en)*2016-11-212020-04-07龙芯中科技术有限公司Method and device for compensating dynamic voltage drop inside chip
CN108089624A (en)*2016-11-212018-05-29龙芯中科技术有限公司The compensation method of chip internal dynamic pressure drop and device
TWI717564B (en)*2016-12-132021-02-01台灣積體電路製造股份有限公司Method and system for estimating power supply noise of power distribution network (pdn) of circuit design
CN108694262A (en)*2017-04-112018-10-23中兴通讯股份有限公司A kind of decoupling capacitor optimization method and device
CN108694262B (en)*2017-04-112023-09-29中兴通讯股份有限公司Decoupling capacitor optimization method and device
CN107506526A (en)*2017-07-192017-12-22清华大学Supply network optimization method on a kind of piece
CN107577849B (en)*2017-08-102019-07-02西安电子科技大学Power distribution network design method based on fast electric pressure drop parser
CN107577849A (en)*2017-08-102018-01-12西安电子科技大学Power distribution network design method based on fast electric pressure drop parser
CN108763777A (en)*2018-05-302018-11-06福州大学VLSI global wiring method for establishing model based on Poisson's equation explicit solution
CN108763777B (en)*2018-05-302023-02-28福州大学Method for establishing VLSI global layout model based on Poisson equation explicit solution
CN111063670A (en)*2018-10-172020-04-24奇景光电股份有限公司 Circuit wiring method, circuit wiring system, and integrated circuit
CN111063670B (en)*2018-10-172022-03-18奇景光电股份有限公司Circuit wiring method, circuit wiring system and integrated circuit
CN110348039A (en)*2019-04-302019-10-18北京理工大学A kind of decoupling capacitor design method for printed circuit board
CN110781642B (en)*2019-10-162023-05-19蔚复来(浙江)科技股份有限公司Method for improving power supply noise based on frequency domain
CN110781642A (en)*2019-10-162020-02-11蔚复来(浙江)科技股份有限公司 A method of improving power supply noise based on frequency domain
CN110940944A (en)*2019-12-042020-03-31厦门大学J coupling removing method for magnetic resonance signals based on deep learning
CN112131831A (en)*2020-11-252020-12-25北京智芯微电子科技有限公司Multi-power domain layout method and storage medium
CN113609626A (en)*2021-05-202021-11-05山东云海国创云计算装备产业创新中心有限公司Voltage drop violation repairing method and related device
CN113609626B (en)*2021-05-202023-09-15山东云海国创云计算装备产业创新中心有限公司 A voltage drop violation repair method and related devices
CN113505095A (en)*2021-07-302021-10-15上海壁仞智能科技有限公司System-on-chip and integrated circuit with multi-core out-of-phase processing
WO2023226073A1 (en)*2022-05-242023-11-30长鑫存储技术有限公司Evaluation method and device for capacitor requirement in power delivery network
CN117272915A (en)*2023-11-172023-12-22飞腾信息技术有限公司Integrated circuit design method, design device and related equipment
CN117272915B (en)*2023-11-172024-02-27飞腾信息技术有限公司Integrated circuit design method, design device and related equipment
CN118569183A (en)*2024-08-022024-08-30杭州芯晓电子科技有限公司 A method for optimizing power network decoupling capacitors based on gradient descent algorithm

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