CN101807601A - Grid-control PNPN field-effect transistor by utilizing SiGe source electrode and preparation method thereof - Google Patents

Abstract

Translated fromChinese

本发明属于半导体器件技术领域，具体公开了一种使用SiGe源极的凹陷沟道型栅控PNPN场效应晶体管。一方面，窄禁带宽度的源极材料使得栅控PNPN场效应晶体管的驱动电流上升；另一方面，凹陷型的沟道结构抑制了栅控PNPN场效应晶体管漏电流的增加。同时，本发明还提出了一种使用SiGe源极的凹陷沟道型栅控PNPN场效应晶体管的制造方法。

The invention belongs to the technical field of semiconductor devices, and specifically discloses a recessed channel gate-controlled PNPN field effect transistor using a SiGe source. On the one hand, the narrow bandgap source material increases the driving current of the gate-controlled PNPN field effect transistor; on the other hand, the recessed channel structure suppresses the increase of the leakage current of the gate-controlled PNPN field effect transistor. At the same time, the invention also proposes a method for manufacturing a recessed channel gate-controlled PNPN field effect transistor using a SiGe source.

Description

A kind of grid-control PNPN field-effect transistor that uses the SiGe source electrode and preparation method thereof

Technical field

The invention belongs to technical field of semiconductor device, be specifically related to a kind of grid-control PNPN field-effect transistor structure, be particularly related to a kind of depression channel type grid-control PNPN field-effect transistor structure of the SiGe of use source electrode, simultaneously, the invention allows for a kind of manufacture method of depression channel type grid-control PNPN field-effect transistor structure of the SiGe of use source electrode.

Background technology

In recent years, be that the microelectric technique of core has obtained development rapidly with the silicon integrated circuit, Moore's Law is followed in the development of integrated circuit (IC) chip basically, and promptly the integrated level of semiconductor chip is with per speed increment of doubling in 18 months.Along with the continuous development of integrated circuit technique, the size of metal oxide-silicon field-effect transistor (MOSFET) is more and more littler, and the transistor density that unit matrix lists is also more and more higher, and thing followed short-channel effect is also obvious further.How to reduce the power consumption of chip, become a research focus of technical field of semiconductors.Integrated circuit (IC)-components technology node of today has been in about 50 nanometers, and the leakage current between the MOSFET source-drain electrode rises rapidly along with dwindling of channel length.Particularly drop to 30 nanometers when following when channel length, be necessary to use novel device to obtain less leakage current, thereby reduce chip power-consumption.

One of solution of the above problems is exactly to adopt grid-control PNPN field-effect transistor, and Fig. 1 has shown a kind of n type grid-control PNPN field-effect transistor structure of planar channeling.As shown in Figure 1, onSemiconductor substrate 101, have heavily doped p type zone (source region) 102 andn type zone 103 among the SiGe, have p type dopedregion 104 and n type doped region (drain region) 105 among the Si, shown in 106 be the medium of oxides layer, shown in 107 be transistorized grid structure, shown in 108,109 and 110 metal electrodes that are respectively source electrode, grid and drain electrode, shown in 111 be dielectric.Heavily dopedn type zone 103 is pockets that exhaust fully, is used to increase horizontal conductive region.Thezone 103 ofsource region 102 and heavy doping n type can strengthen the tunnelling ability of charge carrier.The p-n-p-n junction structure that thezone 104 ofsource region 102,depletion region 103, light dope p type anddrain region 105 constitute in the grid-control PNPN field-effect transistor can reduce leakage current, simultaneously, have littler band gap in the grid-control PNPN field-effect transistor, can increase transistorized drive current.

Although the leakage current of grid-control PNPN field-effect transistor will be lower than traditional MOS transistor, can reduce chip power-consumption greatly.But along with grid-control PNPN field-effect transistor narrows down to below 20 nanometers, its leakage current is also dwindling and rise with device.The drive current of common grid-control PNPN field-effect transistor is than low 2-3 the order of magnitude of MOSFET, therefore needs to improve its drive current, with the performance of the chip that improves integrated grid-control PNPN field-effect transistor.

Summary of the invention

The objective of the invention is to propose a kind of grid-control PNPN field-effect transistor structure, this grid-control PNPN field-effect transistor also can suppress the increase of leakage current when improving drive current.

For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of depression channel type grid-control PNPN field-effect transistor structure of the SiGe of use source electrode, comprising:

Semiconductor substrate with first kind of doping type;

The drain region that on described Semiconductor substrate, forms with second kind of doping type;

The recess channel zone that a side in close drain region forms in described Semiconductor substrate;

The SiGe depletion region that the non-drain region side of depression channel region forms on described Semiconductor substrate with second kind of doping type;

The SiGe source region that on described SiGe depletion region, forms with first kind of doping type;

The grid region in the whole recess channel of the covering zone that on described recess channel zone, forms;

First kind of insulation film abutment wall of the two sides, the whole grid region of covering that form in both sides, described grid region;

Cover described source region, drain region, grid region and abutment wall district with second kind of insulation film;

In described source region, the electrode of the electric conducting material that forms of drain region and grid region.

Among the present invention, described grid region comprises at least one conductive layer and the insulating barrier with described conductive layer and the isolation of described Semiconductor substrate, and described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, and described insulating barrier is SiO₂, HfO₂, HfSiO, HfSiON, SiON, Al₂O₃The perhaps mixture between them.Described first kind, second kind insulation film is silica, silicon nitride or the insulating material for mixing mutually between them.Described electric conducting material is metallic aluminium, tungsten or is other metallic conduction material.

Among the present invention, the zone of first kind of doping type and drain region constitute a p-n-p-n junction structure in described SiGe source region, SiGe depletion region, the Semiconductor substrate.Described first kind of doping type is the p type; Second kind of doping type is the n type; Perhaps described first kind of doping type is the n type, and second kind of doping type is the p type.

The use of U-shaped raceway groove makes that the channel length of tunneling field-effect transistor can be long greater than the grid of horizontal direction, and the rising of channel length makes the leakage current of field-effect transistor be inhibited.Simultaneously, owing to adopted source electrode material with narrow band gap, make the drive current of field-effect transistor rise.

The invention allows for the manufacture method of the depression channel type grid-control PNPN field-effect transistor structure of this use SiGe source electrode, concrete steps are as follows:

Semiconductor substrate with first kind of doping type is provided;

Deposit forms the ground floor photoresist, and makes the figure that need mix in the drain region by lithography by mask exposure;

Carry out ion and inject, form the drain region of second kind of doping type;

The ground floor photoresist lift off;

Deposit forms ground floor hard mask and second layer photoresist successively;

The mask exposure etching exposes substrate, and etched substrate forms the recess channel structure of device;

Second layer photoresist and ground floor hard mask are peeled off;

Form first kind of insulation film, first kind of conductive film and the 3rd layer photoetching glue successively;

The mask exposure etching forms the grid structure of device;

The 3rd layer photoetching glue is peeled off;

Deposit forms second kind of insulation film and the 4th layer photoetching glue successively;

Mask exposure makes the figure that needs to form the source region by lithography;

Second kind of insulation film, first kind of insulation film are carried out etching to expose silicon substrate;

The reactive ion etching silicon substrate;

The 4th layer photoetching glue is peeled off;

Continuation is carried out isotropic etching to silicon substrate;

Extension forms the SiGe depletion region that one deck has second kind of doping type;

Extension forms the SiGe source region that one deck has first kind of doping type;

Expose the drain region at second kind of insulation film of described drain region side etching, first kind of insulation film;

Deposit forms the third insulation film;

The third insulation film is carried out etching form through hole;

Second kind of conductive film of deposit forms electrode.

Described Semiconductor substrate is the silicon (SOI) on monocrystalline silicon, polysilicon or the insulator.Described first kind of hard mask is silica.Described first kind of insulation film is SiO₂, HfO₂, HfSiO, HfSiON, SiON, Al₂O₃The perhaps mixture between them, described second kind, the third insulation film are silica, silicon nitride or the insulating material for mixing mutually between them.Described first kind of conductive film is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride, metal silicide or the mixture between them, and described second kind of conductive film is metallic aluminium, tungsten or is other metallic conduction material.

Further, described first kind of doping type is the n type, second kind of doping type p type; Perhaps, described first kind of doping type p type, second kind of doping type n type.

The depression channel type grid-control PNPN field-effect transistor of the use SiGe source electrode that the present invention proposes leakage current when improving drive current is also reduced, and has just also improved the performance of chip when reducing chip power-consumption.

Description of drawings

Fig. 1 is the sectional view of the n type grid-control PNPN field-effect transistor structure of an existing planar channeling.

Fig. 2 to Fig. 8 is the sectional view of the implementing process of a n type depression channel type grid-control PNPN field-effect transistor structure of using the SiGe source electrode provided by the invention.

Embodiment

Below with reference to accompanying drawings an exemplary embodiment of the present invention is elaborated.In the drawings, for convenience of description, amplified the thickness in layer and zone, shown in size do not represent actual size.Although these figure are not the actual size that reflects device of entirely accurate, their zones that still has been complete reflection and form mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.

Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.Simultaneously in the following description, employed term wafer and substrate can be understood as and comprise the just semiconductor wafer in processes, may comprise other prepared thin layer thereon.

At first, deposit forms onedeck photoresist 202 on the Semiconductor substrate that provides, and makes the figure that need mix in the drain region by lithography by mask exposure, carries out the injection of n type foreign ion then and anneal formingdrain region 201, as Fig. 2.Wherein,substrate 200a and 200b are the silicon layer that contains light dope n type or p type impurity, or are insulating oxide;Substrate 200c is the silicon layer of light dope p type impurity.

Next, strippingphotoresist 202, the film of deposit layer of silicon dioxide again 203, thedeposit photoresist 204 then, and last mask, exposure, etching form the recess channel zone of device, and its structure is as shown in Figure 3.Whereinsilica membrane 203 is in order to etch the lateral length in recess channel zone and recess channel zone more accurately, the lithographic method that etching process adopts dry etching to combine with wet etching as hard mask.

Next, elder generation's strippingphotoresist 204, etch awaysilica membrane 203 again, form onedeck insulation film 205 then, form layer ofconductive film 206 again, deposit one deck photoresist forms grid structure by mask, exposure, etching then again, last stripping photoresist, the structure of formation as shown in Figure 4.Wherein,insulation film 205 comprises the silica membrane of one deck heat growth and the high dielectric constant that one deck deposit forms,conductive film 206 comprise one deck grid metal that deposit forms (such as for Al, TiN or be TaN) and one deck polysilicon.Silica membrane is as passivation layer, and thickness is several dusts, and purpose is to improve interfacial characteristics; The thickness of high dielectric constant is several nanometers to tens nanometer, and purpose is to reduce leakage current.

Next, deposit forms one decksilicon nitride film 207, deposit one deck photoresist again, mask exposure makes the figure that needs to form the source region by lithography then, againsilicon nitride film 207 andinsulation film 205 are carried out etching to expose silicon substrate, again by reactive ion etching silicon substrate, photoresist lift off then, at last silicon substrate is carried out the zone that isotropic etching is formed for forming the source region, structure as shown in Figure 5.

Next, form one deck by extension earlier and have theSiGe depletion region 208 that the n type mixes, form one deck by extension again and have theSiGe source region 209 that the p type mixes, its structure as shown in Figure 6.

Next, 201 side etchsilicon nitride films 207 andinsulation film 205 exposedrain region 201 in the drain region, and form complete grid region abutment wall structure, as shown in Figure 7.

At last, dielectric 213 of deposit, insulating material can or be a silicon nitride for silica.Deposit one deck photoresist passes through the method formation through hole of mask, exposure, etching then, and with photoresist lift off, follows deposit layer of metal more again, can be aluminium, or be tungsten.Etching forms electrode 210,211 and 212 then.The final device architecture that forms as shown in Figure 8.

As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.

Claims (10)

1. grid-control PNPN field-effect transistor is characterized in that this field-effect transistor structure comprises:

Semiconductor substrate with first kind of doping type;

The drain region that on described Semiconductor substrate, forms with second kind of doping type;

The recess channel zone that a side in close drain region forms in described Semiconductor substrate;

The SiGe depletion region that the non-drain region side of depression channel region forms on described Semiconductor substrate with second kind of doping type;

The SiGe source region that on described SiGe depletion region, forms with first kind of doping type;

The grid region in the whole recess channel of the covering zone that on described recess channel zone, forms;

First kind of insulation film abutment wall of the two sides, the whole grid region of covering that form in both sides, described grid region;

Cover described source region, drain region, grid region and abutment wall district with second kind of insulation film;

In described source region, the electrode of the electric conducting material that forms of drain region and grid region.

2. field-effect transistor according to claim 1 is characterized in that described Semiconductor substrate is the silicon on monocrystalline silicon, polysilicon or the insulator.

3. field-effect transistor according to claim 1 is characterized in that described grid region comprises at least one conductive layer and the insulating barrier with described conductive layer and the isolation of described Semiconductor substrate.

4. field-effect transistor according to claim 3 is characterized in that described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide.

5. field-effect transistor according to claim 3 is characterized in that described insulating barrier is SiO₂, HfO₂, HfSiO, HfSiON, SiON, Al₂O₃Perhaps several mixture among them.

6. field-effect transistor according to claim 1 is characterized in that the zone of first kind of doping type in described SiGe source region, SiGe depletion region, the Semiconductor substrate and drain region constitute a p-n-p-n junction structure.

7. field-effect transistor according to claim 1 is characterized in that described first kind of doping type is the p type; Second kind of doping type is the n type; Perhaps described first kind of doping type is the n type, and second kind of doping type is the p type.

8. field-effect transistor according to claim 1 is characterized in that described first kind, second kind insulation film is silica, silicon nitride or the insulating material for mixing mutually between them.

9. field-effect transistor according to claim 1 is characterized in that described electric conducting material is metallic aluminium or tungsten.

10. the manufacture method as the described field-effect transistor structure of one of claim 1～9 is characterized in that comprising the steps:

Semiconductor substrate with first kind of doping type is provided;

Deposit forms the ground floor photoresist, and makes the figure that need mix in the drain region by lithography by mask exposure;

Carry out ion and inject, form the drain region of second kind of doping type;

The ground floor photoresist lift off;

Deposit forms ground floor hard mask and second layer photoresist successively;

The mask exposure etching exposes substrate, and etched substrate forms the recess channel structure of device;

Second layer photoresist and ground floor hard mask are peeled off;

Form first kind of insulation film, first kind of conductive film and the 3rd layer photoetching glue successively;

The mask exposure etching forms the grid structure of device;

The 3rd layer photoetching glue is peeled off;

Deposit forms second kind of insulation film and the 4th layer photoetching glue successively;

Mask exposure makes the figure that needs to form the source region by lithography;

Second kind of insulation film, first kind of insulation film are carried out etching to expose silicon substrate;

The reactive ion etching silicon substrate;

The 4th layer photoetching glue is peeled off;

Continuation is carried out isotropic etching to silicon substrate;

Extension forms the SiGe depletion region that one deck has second kind of doping type;

Extension forms the SiGe source region that one deck has first kind of doping type;

Expose the drain region at second kind of insulation film of described drain region side etching, first kind of insulation film;

Deposit forms the third insulation film;

The third insulation film is carried out etching form through hole;

Second kind of conductive film of deposit forms electrode.

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