CN101661412B

Movatterモバイル変換

Info

Publication number: CN101661412B
Application number: CN200810214696A
Authority: CN
Inventors: 袁国华; 庄贺杰; 陈肇男
Original assignee: Jmicron Tech Corp
Current assignee: Lianyun Technology Hangzhou Co ltd
Priority date: 2008-08-29
Filing date: 2008-08-29
Publication date: 2012-08-29
Anticipated expiration: 2028-08-29
Also published as: CN101661412A

Abstract

The invention provides a configuration method applied to a flash memory, which comprises the following steps: adjusting a preliminary data storage capacity corresponding to the flash memory to determine an actual data storage capacity; adjusting a preliminary extra space capacity corresponding to the flash memory to determine an actual extra space capacity, wherein a sum of the preliminary data storage capacity and the preliminary extra space capacity is equal to a sum of the actual data storage capacity and the actual extra space capacity; and configuring the actual data storage capacity and the actual extra space capacity in the flash memory, wherein the actual data storage capacity is used for storing data, and the actual extra space capacity is used for storing an operation code generated by an error correction code algorithm when the error correction code operation is carried out on the data.

Description

Translated fromChinese

快闪存储器的配置方法How to configure the flash memory

技术领域technical field

本发明是关于一快闪存储器容量配置方法，尤指延长一与非门快闪存储器(Nand flash memory)使用寿命的容量配置方法。The invention relates to a capacity configuration method of a flash memory, especially a capacity configuration method for prolonging the service life of a Nand flash memory.

背景技术Background technique

在可携式电子产品或嵌入式系统中，非挥发性的与非门快闪存储器(Nandflash memory)是目前最常使用的储存装置之一。例如，个人数字助理(PDA)、手机、数码相机、MP3随身听和录音笔等均设置有与非门快闪存储器。然而，由于储存在与非门快闪存储器内的数据的正确性会随着其存取次数的增加而减少，因此为了解决数据错误的问题，在现有的与非门快闪存储器中会搭配适合的错误更正码(ErrorCodes Correction，ECC)配置来对出现错误的数据进行修复。举例来说，在一数据页大小(Page size)为2K的与非门快闪存储器中，会提供额外空间(Spare area)64字节(Bytes)的空间来作为一特定错误更正码算法在对该数据页的数据进行一错误更正码演算时所产生的运算码(Parity code)，而在一数据页大小为4K的与非门快闪存储器中，会提供额外空间218字节(Bytes)的空间来作为该特定错误更正码算法在对该数据页的数据进行该错误更正码演算时所产生的运算码。In portable electronic products or embedded systems, non-volatile NAND flash memory (Nandflash memory) is one of the most commonly used storage devices at present. For example, personal digital assistants (PDAs), mobile phones, digital cameras, MP3 players and recording pens are all equipped with NAND flash memory. However, since the correctness of the data stored in the NAND flash memory will decrease with the increase of its access times, in order to solve the problem of data errors, the existing NAND flash memory will be matched with Appropriate Error Correction Code (ErrorCodes Correction, ECC) configuration to repair the erroneous data. For example, in a NAND flash memory with a data page size (Page size) of 2K, an additional space (Spare area) of 64 bytes (Bytes) will be provided as a specific error correction code algorithm for The operation code (Parity code) generated when the data of the data page is subjected to an error correction code calculation, and in a NAND gate flash memory with a data page size of 4K, an additional space of 218 bytes (Bytes) will be provided. The space is used as an operation code generated by the specific ECC algorithm when performing the ECC operation on the data of the data page.

请参考图1。图1所示是一已知的(Conventional)与非门快闪存储器中每一数据页的额外空间的配置方法，其中当该特定错误更正码算法是采用一里德所罗门(Reed-Solomon)错误更正码算法和一BCH(-Bose，Chaudhuri and Hocquengham)错误更正码算法。当使用一BCH8错误更正码算法对该与非门快闪存储器进行编码时，其编码后所产生的运算码会占用每一数据页13字节的额外空间。当使用一里德所罗门6(Reed-Solomon6)错误更正码算法对该与非门快闪存储器进行编码时，其编码后所产生的运算码会占用每一数据页15字节的额外空间。当使用一里德所罗门8(Reed-Solomon8)错误更正码算法对该与非门快闪存储器进行编码时，其编码后所产生的运算码会占用每一数据页20字节的额外空间。当使用一里德所罗门10(Reed-Solomon10)错误更正码算法或一BCH15错误更正码算法对该与非门快闪存储器进行编码时，其编码后所产生的运算码会占用每一数据页25字节的额外空间。另一方面，已知的与非门快闪存储器使用该里德所罗门错误更正码算法和该BCH错误更正码算法时，均会配置512字节的储存数据空间于每一数据页中。因此，一已知的与非门快闪存储器在使用该里德所罗门错误更正码算法和该BCH错误更正码算法时，其数据错误更正的能力就被预设的额外空间大小所限制住了。换句话说，该里德所罗门错误更正码算法和该BCH错误更正码算法无法对该已知的与非门快闪存储器提供更好的数据错误更正能力的原因是每一数据页所预设的额外空间有限，进而造成使用者极大的不便。Please refer to Figure 1. Fig. 1 shows a known (Conventional) method of configuring the extra space of each data page in the NAND flash memory, wherein when the specific error correction code algorithm adopts a Reed-Solomon (Reed-Solomon) error Correction code algorithm and a BCH (-Bose, Chaudhuri and Hocquengham) error correction code algorithm. When a BCH8 ECC algorithm is used to encode the NAND flash memory, the operation code generated after encoding will occupy an extra space of 13 bytes per data page. When a Reed-Solomon 6 (Reed-Solomon 6) error correction code algorithm is used to encode the NAND gate flash memory, the operation code generated after encoding will occupy an extra space of 15 bytes per data page. When a Reed-Solomon 8 (Reed-Solomon8) error correction code algorithm is used to encode the NAND gate flash memory, the operation code generated after encoding will occupy an additional space of 20 bytes per data page. When using a Reed-Solomon 10 (Reed-Solomon10) error correction code algorithm or a BCH15 error correction code algorithm to encode this NAND gate flash memory, the operation code generated after its encoding will occupy each data page 25 bytes of extra space. On the other hand, when the known NAND flash memory uses the Reed-Solomon ECC algorithm and the BCH ECC algorithm, a storage data space of 512 bytes is allocated in each data page. Therefore, when a known NAND flash memory uses the Reed-Solomon ECC algorithm and the BCH ECC algorithm, its data error correction capability is limited by the preset extra space. In other words, the reason why the Reed-Solomon error correction code algorithm and the BCH error correction code algorithm cannot provide better data error correction capability for the known NAND flash memory is that each data page is preset The additional space is limited, thereby causing great inconvenience to the user.

发明内容Contents of the invention

因此，本发明的目的是提供一种延长一与非门快闪存储器(Nand flash memory)使用寿命的容量配置方法。Therefore, the purpose of the present invention is to provide a kind of prolonging the capacity allocation method of NAND flash memory (Nand flash memory) service life.

依据本发明一方面的一种应用于一快闪存储器的配置方法，其包含有：调整对应于该快闪存储器的一初步数据储存容量来决定出一实际数据储存容量；调整对应于该快闪存储器步额外空间容量来决定出一实际额外空间容量，其中，其中该初步数据储存容量与该初步额外空间容量的总和等于该实际数据储存容量与该实际额外空间容量的总和；以及于该快闪存储器中配置该实际数据储存容量与该实际额外空间容量，其中该实际数据储存容量是用以储存数据，以及该实际额外空间容量是用以储存一错误更正码(Error Codes Correction，ECC)算法在对该数据进行一错误更正码运算时所产生的运算码(Parity Bytes)。According to an aspect of the present invention, a configuration method applied to a flash memory includes: adjusting a preliminary data storage capacity corresponding to the flash memory to determine an actual data storage capacity; The memory determines an actual extra space capacity based on the extra space capacity, wherein the sum of the preliminary data storage capacity and the preliminary extra space capacity is equal to the sum of the actual data storage capacity and the actual extra space capacity; and in the flash memory The actual data storage capacity and the actual extra space capacity are configured in the memory, wherein the actual data storage capacity is used to store data, and the actual extra space capacity is used to store an error correction code (Error Codes Correction, ECC) algorithm in Operation code (Parity Bytes) generated when an error correction code operation is performed on the data.

依据本发明的另一方面的一种应用于一快闪存储器的配置方法，包含有：决定一实际数据储存容量与一实际额外空间容量，其中该实际额外空间容量是大于对应于一错误更正码(Error Codes Correction，ECC)算法的一预设字节；以及于该快闪存储器中配置该实际数据储存容量与该实际额外空间容量，其中该实际数据储存容量是用以储存数据，以及该实际额外空间容量是用以储存该错误更正码算法在对该数据进行一错误更正码运算时所产生的运算码(Parity Bytes)。A configuration method applied to a flash memory according to another aspect of the present invention includes: determining an actual data storage capacity and an actual extra space capacity, wherein the actual extra space capacity is greater than a value corresponding to an error correction code (Error Codes Correction, ECC) algorithm a default byte; and configure the actual data storage capacity and the actual additional space capacity in the flash memory, wherein the actual data storage capacity is used to store data, and the actual The extra space capacity is used to store operation codes (Parity Bytes) generated when the ECC algorithm performs an ECC operation on the data.

附图说明Description of drawings

图1是一已知的与非门快闪存储器中每一数据页的额外空间的配置方法。FIG. 1 is a known method for configuring the extra space of each data page in a NAND flash memory.

图2是本发明一种应用于一快闪存储器(flash memory)的配置方法的一实施例流程图。FIG. 2 is a flowchart of an embodiment of a configuration method applied to a flash memory (flash memory) according to the present invention.

图3是图2的配置方法对于该快闪存储器的配置前与配置后示意图。FIG. 3 is a schematic diagram of before and after configuration of the flash memory in the configuration method of FIG. 2 .

图4是本发明一种应用于一快闪存储器的配置方法的另一实施例流程图。FIG. 4 is a flowchart of another embodiment of a configuration method applied to a flash memory according to the present invention.

具体实施方式Detailed ways

在说明书及后续的本申请权利要求中使用了某些词汇来指称特定的元件。所属领域中具有通常知识者应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及后续的权利要求并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的准则。在通篇说明书及后续的请求相当中所提及的“包含”是一开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”一词在此是包含任何直接及间接的电气连接手段，因此，若文中描述一第一装置耦接于一第二装置，则代表该第一装置可直接电气连接于该第二装置，或者通过其它装置或连接手段间接地电气连接至该第二装置。Certain terms are used in the specification and claims that follow the application to refer to particular elements. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same element. This description and the subsequent claims do not use the difference in name as the way to distinguish components, but use the difference in function of the components as the criterion for distinguishing. The "comprising" mentioned in the entire specification and the subsequent claims is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" here includes any direct and indirect electrical connection means, therefore, if it is described in the text that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the The second device, or indirectly electrically connected to the second device through other devices or connection means.

请同时参考图2和图3，图2所示是依据本发明一种应用于一快闪存储器(flash memory)的配置方法200的一实施例流程图。图3所示是本发明配置方法200对于该快闪存储器的配置前快闪存储器300a与配置后快闪存储器300b示意图。请注意，为了更清楚描述本发明的精神所在，在本实施例中的该快闪存储器是以一与非门快闪存储器(Nand Flash Memory)作说明，然而此并不为本发明所限。换句话说，熟悉此项技术者应可了解，任何具有快闪存储器特性的储存装置，例如一或非门快闪存储器(Nor Flash Memory)，均为本发明的范畴所在。倘若大体上可达到相同的结果，并不需要一定照图2所示的流程中的步骤顺序来进行，且图2所示的步骤不一定要连续进行，亦即其它步骤亦可插入其中，配置方法200包含有下列步骤：Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 2 is a flowchart of an embodiment of aconfiguration method 200 applied to a flash memory (flash memory) according to the present invention. FIG. 3 is a schematic diagram of apre-configuration flash memory 300 a and apost-configuration flash memory 300 b of the flash memory in theconfiguration method 200 of the present invention. Please note that in order to describe the spirit of the present invention more clearly, the flash memory in this embodiment is described as a Nand Flash Memory (Nand Flash Memory), but this is not limited to the present invention. In other words, those skilled in the art should understand that any storage device with the characteristics of a flash memory, such as a NOR flash memory (Nor Flash Memory), falls within the scope of the present invention. If generally the same result can be achieved, it is not necessary to follow the sequence of steps in the process shown in Figure 2, and the steps shown in Figure 2 do not have to be performed continuously, that is, other steps can also be inserted therein, theconfiguration Method 200 includes the following steps:

步骤202：减少对应于该快闪存储器的一初步数据储存容量来决定出一实际数据储存容量；Step 202: Decrease a preliminary data storage capacity corresponding to the flash memory to determine an actual data storage capacity;

步骤204：增加对应于该快闪存储器的一初步额外空间容量来决定出一实际额外空间容量，其中该初步数据储存容量与该初步额外空间容量的总和等于该实际数据储存容量与该实际额外空间容量的总和；以及Step 204: Increase a preliminary extra space capacity corresponding to the flash memory to determine an actual extra space capacity, wherein the sum of the preliminary data storage capacity and the preliminary extra space capacity is equal to the actual data storage capacity and the actual extra space sum of capacities; and

步骤206：于该快闪存储器中配置该实际数据储存容量与该实际额外空间容量，其中该实际数据储存容量是用以储存数据，以及该实际额外空间容量是用以储存一错误更正码(Error Codes Correction，ECC)算法在对该数据进行一错误更正码运算时所产生的运算码(Parity Bytes)。Step 206: Configure the actual data storage capacity and the actual extra space capacity in the flash memory, wherein the actual data storage capacity is used to store data, and the actual extra space capacity is used to store an error correction code (Error The operation code (Parity Bytes) generated when the Codes Correction (ECC) algorithm performs an error correction code operation on the data.

由于该快闪存储器与一主存储器之间数据交换的最小单位为一数据页(Page)，因此在图3中该快闪存储器是以数据页的单位来示意。在该快闪存储器未通过本发明的配置方法200进行容量配置之前，其每一数据页中的一储存数据空间302a和一额外空间304a的容量配置大小是依据一特定的错误更正码算法所预设的。举例来说，当利用一里德所罗门10(Reed-Solomon10)错误更正码算法或一BCH15(-Bose，Chaudhuri and Hocquengham15)错误更正码算法来对每一数据页中的储存数据空间302a内512字节(Bytes)的数据进行一错误更正码运算时，其运算后所产生的运算码所占有的额外空间304容量大小是预设为25字节。然而，当额外空间304a的容量大小为设置为25字节时，该特定的错误更正码算法对该快闪存储器中每一数据页的译码能力就被限制住了。同时，该快闪存储器的存取次数也被限制住了。因此，对该特定的错误更正码算法而言，本发明配置方法200的步骤202对该快闪存储器的储存容量进行配置时会先估算出该快闪存储器的一初步数据储存容量，该初步数据储存容量是该快闪存储器的总数据储存容量，如图3所示。该初步数据储存容量是所有每一数据页中的储存数据空间302a的总和。接着，配置方法200减少对应于该快闪存储器的该初步数据储存容量来决定出一实际数据储存容量，使得该实际数据储存容量是小于该初步数据储存容量。同样的，该实际数据储存容量是所有每一数据页中的储存数据空间302b的总和。请注意，为了方便起见，在本实施例中每一数据页中的储存数据空间302a和302b均以512字节作为说明，然而此并不为本发明所限制。在步骤204中，为了提高该特定的错误更正码算法对每一数据页的错误更正能力，配置方法增加对应于该快闪存储器的一初步额外空间容量来决定出一实际额外空间容量，其中该初步数据储存容量与该初步额外空间容量的总和等于该实际数据储存容量与该实际额外空间容量的总和。在步骤206中，于该快闪存储器中配置该实际数据储存容量与该实际额外空间容量，其中该实际数据储存容量是用以储存数据，以及该实际额外空间容量是用以储存该特定的错误更正码算法在对该数据进行一错误更正码运算时所产生的运算码(ParityBytes)。请再次参考图3，由于该快闪存储器通过配置方法200进行容量配置后，每一数据页中的储存数据空间302b仍维持于512字节的大小，而每一数据页中的额外空间304b却会比25字节来得大，因此该特定的错误更正码算法对每一数据页的错误更正能力就得以提高，进而延长了该快闪存储器的存取次数。请注意，虽然在图3所示的配置后快闪存储器300b中每一个储存数据空间302b和额外空间304b是以间隔的方式排列，然而此并不为本发明所限制。换句话说，每一数据页的储存数据空间302b和其相对应的额外空间304b并不一定是相邻的，亦即每一个储存数据空间302b和额外空间304b的排列是可依据设计需求而具弹性变化的。举例来说，在本发明的另一实施例中，其是连续配置多个储存数据空间302b后再连续配置相同个数的额外空间304b以组合成相对应个数的数据页。Since the minimum unit of data exchange between the flash memory and a main memory is a data page (Page), the flash memory is illustrated in units of data pages in FIG. 3 . Before the flash memory is configured through theallocation method 200 of the present invention, the capacity allocation size of astorage data space 302a and anextra space 304a in each data page is predetermined according to a specific error correction code algorithm set. For example, when utilizing a Reed-Solomon 10 (Reed-Solomon10) error correction code algorithm or a BCH15 (-Bose, Chaudhuri and Hocquengham15) error correction code algorithm to store 512 words in thestorage data space 302a in each data page When data in Bytes is subjected to an ECC operation, the capacity of the extra space 304 occupied by the operation code generated after the operation is preset to be 25 bytes. However, when the capacity of theextra space 304a is set to 25 bytes, the ability of the specific ECC algorithm to decode each data page in the flash memory is limited. At the same time, the access times of the flash memory are also limited. Therefore, for the specific ECC algorithm, when configuring the storage capacity of the flash memory in step 202 of theconfiguration method 200 of the present invention, a preliminary data storage capacity of the flash memory will be estimated first, and the preliminary data The storage capacity is the total data storage capacity of the flash memory, as shown in FIG. 3 . The preliminary data storage capacity is the sum of allstored data spaces 302a in each data page. Next, theconfiguration method 200 reduces the preliminary data storage capacity corresponding to the flash memory to determine an actual data storage capacity, so that the actual data storage capacity is smaller than the preliminary data storage capacity. Likewise, the actual data storage capacity is the sum of all storage data spaces 302b in each data page. Please note that for convenience, in this embodiment, thestorage data spaces 302a and 302b in each data page are described as 512 bytes, but this is not limited by the present invention. Instep 204, in order to improve the error correction capability of the specific error correction code algorithm for each data page, the configuration method increases a preliminary extra space capacity corresponding to the flash memory to determine an actual extra space capacity, wherein the The sum of the preliminary data storage capacity and the preliminary extra space capacity is equal to the sum of the actual data storage capacity and the actual extra space capacity. Instep 206, configure the actual data storage capacity and the actual extra space capacity in the flash memory, wherein the actual data storage capacity is used to store data, and the actual extra space capacity is used to store the specific error The operation code (ParityBytes) generated when the correction code algorithm performs an error correction code operation on the data. Please refer to FIG. 3 again. After the flash memory is configured through theconfiguration method 200, the storage data space 302b in each data page is still maintained at a size of 512 bytes, while theextra space 304b in each data page is It is larger than 25 bytes, so the error correction capability of the specific ECC algorithm for each data page is improved, thereby prolonging the access times of the flash memory. Please note that although each storage data space 302b and theadditional space 304b in theflash memory 300b are arranged at intervals after the configuration shown in FIG. 3 , this is not a limitation of the present invention. In other words, the storage data space 302b and the correspondingadditional space 304b of each data page are not necessarily adjacent, that is, the arrangement of each storage data space 302b and theadditional space 304b can be determined according to design requirements. flexible to change. For example, in another embodiment of the present invention, a plurality of storage data spaces 302b are continuously allocated, and then the same number ofadditional spaces 304b are continuously allocated to form a corresponding number of data pages.

请参考图4。图4所示是依据本发明一种应用于一快闪存储器的配置方法400的另一实施例流程图。同理，为了更清楚描述本发明的精神所在，在本实施例中的该快闪存储器是以一与非门快闪存储器作说明，然而此并不为本发明所限。换句话说，熟悉此项技术者应可了解，任何具有快闪存储器特性的储存装置，例如一或非门快闪存储器，均为本发明的范畴所在。倘若大体上可达到相同的结果，并不需要一定照图4所示的流程中的步骤顺序来进行，且图4所示的步骤不一定要连续进行，亦即其它步骤亦可插入其中，配置方法400包含有下列步骤：Please refer to Figure 4. FIG. 4 is a flowchart of another embodiment of aconfiguration method 400 applied to a flash memory according to the present invention. Similarly, in order to describe the spirit of the present invention more clearly, the flash memory in this embodiment is illustrated as a NAND flash memory, but this is not limited to the present invention. In other words, those skilled in the art should understand that any storage device having the characteristics of a flash memory, such as a NOR flash memory, falls within the scope of the present invention. If generally the same result can be achieved, it is not necessary to follow the sequence of steps in the process shown in Figure 4, and the steps shown in Figure 4 do not have to be performed continuously, that is, other steps can also be inserted therein, theconfiguration Method 400 includes the following steps:

步骤402：决定一实际数据储存容量与一实际额外空间容量，其中该实际额外空间容量是大于对应于一错误更正码(Error Codes Correction，ECC)算法的一预设的字节；以及Step 402: determine an actual data storage capacity and an actual extra space capacity, wherein the actual extra space capacity is greater than a preset byte corresponding to an error correction code (Error Codes Correction, ECC) algorithm; and

步骤404：于该快闪存储器中配置该实际数据储存容量与该实际额外空间容量，其中该实际数据储存容量是用以储存数据，以及该实际额外空间容量是用以储存该错误更正码算法在对该数据进行一错误更正码运算时所产生的运算码(ParityBytes)。Step 404: Allocate the actual data storage capacity and the actual extra space capacity in the flash memory, wherein the actual data storage capacity is used to store data, and the actual extra space capacity is used to store the ECC algorithm in The operation code (ParityBytes) generated when an ECC operation is performed on the data.

如同上述的第一实施例，当利用一里德所罗门10(Reed-Solomon10)错误更正码算法或一BCH15(-Bose，Chaudhuri and Hocquengham15)错误更正码算法来对该快闪存储器的每一数据页中的储存数据空间内512字节(Bytes)的数据进行一错误更正码运算时，其运算后所产生的运算码所占有的额外空间容量大小是预设为25字节。而步骤402会决定每一数据页中的实际数据储存空间与实际额外空间，其中该实际额外空间容量是大于25字节，而实际数据储存空间容量是512字节。在步骤404中，于该快闪存储器中配置每一数据页该实际数据储存容量与该实际额外空间容量，其中该实际数据储存容量是用以储存数据，以及该实际额外空间容量是用以储存该特定的错误更正码算法在对该数据进行一错误更正码运算时所产生的运算码(Parity Bytes)。由此可知，由于该快闪存储器通过配置方法400进行容量配置后，每一数据页中的实际数据储存空间仍维持于512字节的大小，而每一数据页中的实际额外空间却会比预设的25字节来得大，因此该特定的错误更正码算法对每一数据页的错误更正能力就得以提高，进而延长了该快闪存储器的存取次数。Like the above-mentioned first embodiment, when utilizing a Reed Solomon 10 (Reed-Solomon10) error correction code algorithm or a BCH15 (-Bose, Chaudhuri and Hocquengham15) error correction code algorithm to each data page of the flash memory When the data of 512 bytes (Bytes) in the storage data space in is subjected to an error correction code operation, the extra space occupied by the operation code generated after the operation is preset at 25 bytes. And step 402 will determine the actual data storage space and the actual extra space in each data page, wherein the actual extra space capacity is greater than 25 bytes, and the actual data storage space capacity is 512 bytes. Instep 404, configure the actual data storage capacity and the actual extra space capacity for each data page in the flash memory, wherein the actual data storage capacity is used to store data, and the actual extra space capacity is used to store The operation code (Parity Bytes) generated when the specific error correction code algorithm performs an error correction code operation on the data. It can be seen that, after the capacity of the flash memory is configured through theconfiguration method 400, the actual data storage space in each data page is still maintained at a size of 512 bytes, while the actual additional space in each data page is larger than The preset 25 bytes is larger, so the error correction capability of the specific ECC algorithm for each data page can be improved, thereby prolonging the access times of the flash memory.

综上所述，虽然本发明第一和第二实施例是以里德所罗门10错误更正码算法和该BCH15错误更正码算法来作说明，然其并不为本发明范围所限。换句话说，当该特定的错误更正码算法是一BCH8(-Bose，Chaudhuri and Hocquengham8)错误更正码算法时，通过上述所揭露的配置方法后，每一数据页中的额外空间就可以配置大于13字节的的空间，其亦属本发明的范畴所在；当该特定的错误更正码算法是一里德所罗门6(Reed-Solomon6)错误更正码算法时，通过上述所揭露的配置方法后，每一数据页中的额外空间就可以配置大于15字节的空间，其亦属本发明的范畴所在；当该特定的错误更正码算法是一里德所罗门8(Reed-Solomon8)错误更正码算法时，通过上述所揭露的配置方法后，每一数据页中的额外空间就可以配置大于20字节的空间，其亦属本发明的范畴所在。更确切来说，针对一快闪存储器而言，若该特定的错误更正码算法是一BCH8错误更正码算法时，通过上述所揭露的配置方法后，该快闪存储器可以利用任何比BCH8更高阶的错误更正码算法来进行错误更正演算，例如利用里德所罗门10、BCH15错误更正码算法等等。To sum up, although the first and second embodiments of the present invention are described with the Reed-Solomon 10 ECC algorithm and the BCH15 ECC algorithm, they are not limited to the scope of the present invention. In other words, when the specific error correction code algorithm is a BCH8 (-Bose, Chaudhuri and Hocquengham8) error correction code algorithm, after the configuration method disclosed above, the extra space in each data page can be configured greater than The space of 13 bytes also belongs to the scope of the present invention; when the specific error correction code algorithm is a Reed-Solomon 6 (Reed-Solomon6) error correction code algorithm, after the configuration method disclosed above, The extra space in each data page can be configured with a space greater than 15 bytes, which also belongs to the scope of the present invention; when the specific error correction code algorithm is a Reed-Solomon 8 (Reed-Solomon8) error correction code algorithm At this time, after the configuration method disclosed above, the extra space in each data page can be configured with a space larger than 20 bytes, which also belongs to the scope of the present invention. More precisely, for a flash memory, if the specific error correction code algorithm is a BCH8 error correction code algorithm, after the configuration method disclosed above, the flash memory can use any higher than BCH8 The first-order error correction code algorithm is used to perform error correction calculations, such as using Reed Solomon 10, BCH15 error correction code algorithms, and so on.

以上所述仅为本发明的较佳实施例，凡根据本申请权利要求范围所作出的种种等同的改变或替换，皆应属本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes or replacements made according to the claims of the present application shall fall within the scope of the present invention.

Claims

1. collocation method that is applied to a flash memory includes:

Minimizing decides a real data storage volume corresponding to a preliminary data storage volume of this flash memory;

Increase decides a real account external space capacity corresponding to a preliminary exceptional space capacity of this flash memory, and wherein the summation of this preliminary data storage volume and this preliminary exceptional space capacity equals the summation of this real data storage volume and this real account external space capacity; And

This real data storage volume of configuration and this real account external space capacity in this flash memory; Wherein this preliminary data memory capacity refers to according to specific error correction code calculation; The total data storage volume of this flash memory that estimates; This real data storage volume is in order to storage data; This preliminary exceptional space capacity refers to according to specific error correction code calculation, be used to store total storage volume of the operation code that the error correction code calculation produces in this flash memory that estimates, and this real account external space capacity is in order to store the operation code that an error correction code calculation is produced when these data are carried out an error correcting code computing.

2. collocation method according to claim 1 it is characterized in that this real data storage volume is less than this preliminary data storage volume, and this real account external space capacity is greater than this preliminary exceptional space capacity.

3. collocation method according to claim 1 is characterized in that this real account external space capacity is greater than the preset byte corresponding to this error correction code calculation.

4. collocation method according to claim 1 is characterized in that this flash memory is a Sheffer stroke gate flash memory.

5. collocation method that is applied to a flash memory includes:

Determine a real data storage volume and a real account external space capacity, it is characterized in that this real account external space capacity is greater than the preset byte corresponding to an error correction code calculation; And

This real data storage volume of configuration and this real account external space capacity in this flash memory; Wherein this real data storage volume is in order to storage data, and this real account external space capacity is in order to store the operation code that this error correction code calculation is produced when these data are carried out an error correcting code computing.

6. collocation method according to claim 5 is characterized in that this flash memory is a Sheffer stroke gate flash memory.