CN101645435B - Probing pad structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a probing pad structure and a manufacturing method thereof. The probing pad structure is suitable to be arranged in a cutting street area of a wafer, is provided with a groove and a smaller sectional area, and provides a longer glide distance for a probe. The probing pad structure comprises a substrate, at least one conductive layer and at least one protective layer, wherein the substrate is provided with the groove; the conductive layer is arranged on the substrate; the conductive layer comprises a first metal layer and a second metal layer; the first metal layer is arranged on the groove; the second metal layer is arranged on the first metal layer, and extends to the substrate outside the groove; the protective layer is arranged on the conductive layer; the protective layer is provided with an opening; and the opening is arranged corresponding to the position of the groove.

Description

Probing pad structure and manufacture method thereof

Technical field

The invention relates to a kind of semiconductor structure and manufacture method thereof, and particularly relevant for a kind of detection pad (probing pad) structure and manufacture method thereof that is used for Cutting Road.

Background technology

Along with the progress of science and technology, the semiconductor manufacturing has just like become one of most important industry, yet in response to different demands, its manufacture process also just becomes and becomes increasingly complex.Therefore, produce high yield (yield) and cheaply wafer also just become and more and more be not easy.

In order in the manufacture process of semiconductor wafer, to obtain the message of processing procedure quality at any time, generally can just have a plurality of being parallel to each other on the wafer and go up design a plurality of feeler switchs (test key) at the periphery of semiconductor wafer with vertical Cutting Road (scribe line).And these feeler switchs can be via weld pad (pad), carries out test job for the probe (probe) of detecting card, in order to the mistake that can't expect in the inspection process, monitors the quality of each stage processing procedure.

Along with the requirement to integration is more and more high, the wafer area occupied more promptly is that cost is higher.And input/output circuitry (I/O circuit), electrostatic discharge protection circuit (electrostatic discharge protection circuit), weld pad ... wait and all occupy certain chip area.Generally speaking, the existing weld pad size that is used for feeler switch all can cause the space availability ratio of wafer low excessively greater than 40 μ m * 40 μ m easily, causes manufacturing cost too high.And the spacing that present process technique also can't make detection welding pad is micro more.Can't make element further during microminiaturization in process technique, can influence the configuring condition of these feeler switchs on Cutting Road.

Owing to be subject to present process technique, and can't improve the space availability ratio of wafer and reduce manufacturing cost, so how head it off has become now industry and actively makes great efforts one of target that develops.

Summary of the invention

The invention provides a kind of probing pad structure, it is long-pending to have groove and small cross sections, and provides probe long coasting distance.

The invention provides a kind of manufacture method of probing pad structure, can improve the space availability ratio of wafer and save the processing procedure cost.

The present invention proposes a kind of probing pad structure, is suitable for being configured in the Cutting Road district of wafer, and probing pad structure comprises substrate, one deck conductive layer and protective layer at least.Substrate has groove.Conductive layer is disposed in the substrate, and conductive layer comprises the first metal layer and second metal level.The first metal layer is disposed on the groove.Second metal level is disposed on the first metal layer, and extends in the groove substrate in addition.Protective layer is disposed on the conductive layer, and protective layer has opening, and the position of opening respective slot and disposing.

In one embodiment of this invention, above-mentioned probing pad structure is when having a plurality of conductive layer, and conductive layer for example is to dispose in stacked mode.

In one embodiment of this invention, more comprise at least one conductive plunger, be disposed in the groove substrate in addition, and conductive plunger connects each conductive layer.

In one embodiment of this invention, above-mentioned conductive plunger connects each second metal level.

In one embodiment of this invention, more comprise dielectric layer, be disposed between each conductive layer.

In one embodiment of this invention, each above-mentioned conductive layer contacts with each other.

In one embodiment of this invention, the size of above-mentioned groove is between 15 μ m * 15 μ m to 30 μ m * 30 μ m.

In one embodiment of this invention, above-mentioned substrate surface is greater than 5 μ m in the section difference of groove.

In one embodiment of this invention, the opening of above-mentioned protective layer exposes second metal level.

In one embodiment of this invention, above-mentioned protective layer comprises silicon oxide layer and silicon nitride layer.

The present invention proposes a kind of manufacture method of probing pad structure, and this probing pad structure is suitable for being configured in the Cutting Road district of wafer.At first, provide substrate.Then, remove the part substrate, to form groove.Thereupon, in substrate, form one deck conductive layer at least.The method that forms conductive layer is included in and forms the first metal layer on the groove, and forms second metal level in substrate, and second metal level compliance ground covers the first metal layer and extends in the substrate beyond the groove.Afterwards, on conductive layer, form protective layer with opening, and the position of opening respective slot and disposing.

In one embodiment of this invention, when forming a plurality of this conductive layer, conductive layer disposes in stacked mode.

In one embodiment of this invention, before forming conductive layer, more be included in and form dielectric layer in the substrate, then remove the part dielectric layer,, in plug open, form conductive plunger again to form at least one plug open in the dielectric layer beyond groove.

In one embodiment of this invention, be set forth on to form conductive plunger in the plug open and form the first metal layer and carry out simultaneously.

In one embodiment of this invention, above-mentioned conductive plunger connects each second metal level.

In one embodiment of this invention, more comprise and remove the dielectric layer that is positioned on the groove.

In one embodiment of this invention, the size of above-mentioned groove is between 15 μ m * 15 μ m to 30 μ m * 30 μ m.

In one embodiment of this invention, above-mentioned substrate surface is greater than 5 μ m in the section difference of groove.

In one embodiment of this invention, the method for above-mentioned formation groove comprises the laser machine at quarter that uses.

In one embodiment of this invention, the method for above-mentioned formation groove more comprises use alignment mark photomask or irrigation canals and ditches photomask.

In one embodiment of this invention, the formation method of above-mentioned protective layer for example is prior to forming silicon oxide layer in the substrate, form silicon nitride layer again in substrate, then removing partial oxidation silicon layer and silicon nitride layer, to expose second metal level that is positioned at groove.

Probing pad structure of the present invention and manufacture method thereof dispose metal level because of adopting in groove, therefore can have less sectional area simultaneously and provide probe long coasting distance, and can also avoid probe to skid off the scope of probing pad structure when sliding.

Description of drawings

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:

Figure 1A to Fig. 1 H is the manufacturing process generalized section according to a kind of probing pad structure of one embodiment of the invention.

Fig. 2 is the generalized section according to a kind of probing pad structure of another embodiment of the present invention.

The main element symbol description:

100: substrate

102: groove

104,112,120: dielectric layer

106,110,114,118,122,126: metal level

108,116,124: conductive plunger

128: protective layer

128a: silicon nitride layer

128b: silicon oxide layer

Embodiment

Figure 1A to Fig. 1 H is the manufacturing process generalized section according to a kind of probing pad structure of one embodiment of the invention.It is noted that the manufacture method of the probing pad structure of the following stated is to be that example describes with the Cutting Road district that is formed on wafer, it mainly is for those who familiarize themselves with the technology can be implemented according to this, but is not in order to limit scope of the present invention.Quantity, allocation position and generation type as for active element district or other members such as contact hole connector, interlayer hole connector, each floor metal level etc., all can be according to having the fabrication techniques of knowing usually known to the knowledgeable in the affiliated technical field, and it is described to be not limited to following embodiment.

Please refer to Figure 1A,substrate 100 is provided, it for example is a semiconductor crystal wafer, as N type Silicon Wafer, P type Silicon Wafer, three or five family's semiconductor crystal wafers etc.Afterwards, in removingpart substrate 100, it is poor to make its surface produce section, and forms groove 102.The size ofgroove 102 for example is between 15 μ m * 15 μ m to 30 μ m * 30 μ m.The last formed section difference insubstrate 100 surfaces for example is greater than 5 μ m.The size of above-mentionedgroove 102 and 100 lip-deep sections differences of substrate all can be adjusted design according to process requirement.It should be noted that in thisstep groove 102 designs according to follow-up preformed detection pad, that is the size of follow-up preformed detection pad is that size bygroove 102 decides.

Hold above-mentionedly,groove 102 for example is directly to carry out the laser burning insubstrate 100 surfaces and form with laser machine at quarter (laser marker), or utilizes other suitable methods such as photoetching and etching processing procedure to removepart substrate 100 and form.In one embodiment, the above-mentioned step of utilizing photoetching and etching processing procedure to removepart substrate 100 can be to carry out simultaneously with the needed alignment mark of formation (alignment mark) in substrate 100.In another embodiment, the above-mentioned step of utilizing photoetching and etching processing procedure to removepart substrate 100 also can be to carry out simultaneously with the irrigation canals and ditches structure that forms semiconductor element insubstrate 100, and it for example is that the deep trenches required with forming the DRAM structure carried out simultaneously.In addition, thegroove 102 shown in Figure 1A is to be that example describes with the groove with arc-shaped sections, but the present invention is not limited to this.

Then, the active element district insubstrate 100 forms conductive part (not illustrating) or semiconductor element (not illustrating), and it for example is the element that forms transistor or generally know in thesubstrate 100 beyond the groove 102.What specify is in the process that forms above-mentioned conductive part or semiconductor element, not have any rete in thegroove 102 and form or be covered on its surface.Afterwards, insubstrate 100, form one dielectric layer 104.Dielectric layer 104 for example be compliance be covered on the surface of groove 102.Dielectric layer 104 for example as interlayer dielectric layer (inter-layer dielectric, ILD).The material ofdielectric layer 104 is silica or other suitable dielectric materials for example, and its formation method for example is a chemical vapour deposition technique.

Please refer to Figure 1B, remove partdielectric layer 104, to form contact window in thedielectric layer 104 beyond groove 102.Contact window for example is the surface that exposes substrate 100.The formation method of contact window for example is to finish by lithographic process and etching processing procedure.Afterwards, insubstrate 100, form layer of metal layer 106.Metal level 106 for example is to fill up contact window, and compliance be covered on the surface of groove 102.In one embodiment, the thickness that is formed atgroove 102 lip-deep metal levels 106 is about 3000

The material ofmetal level 106 for example is tungsten or other suitable metal materials, and its formation method for example is physical vaporous deposition or chemical vapour deposition technique.

Then, removepart metals layer 106, and in contact window, form conductive plunger 108.The method that removespart metals layer 106 for example be utilize the cmp processing procedure and withdielectric layer 104 as grinding suspension layer, remove themetal level 106 beyond the contact window and make its flattening surface.In this explanation is that when carrying out the chemical machinery processing procedure, because the surface section of having ofsubstrate 100 is poor, therefore themetal level 106 that is formed in thegroove 102 can be retained and can not be removed.

Please refer to Fig. 1 C, insubstrate 100, form layer of metal layer 110.The material ofmetal level 110 for example is aluminium, copper or other suitable metal materials, and its formation method for example is physical vaporous deposition or chemical vapour deposition technique.Then, patternedmetal layer 110 is positioned at preformed detection padarea metal level 110 in addition to remove.That is to say that themetal level 110 behind the patterning for example is to be covered on theconductive plunger 108, and is covered on the surface of groove 102.Metal level 110 behind the patterning for example is as the ground floor metal level.Afterwards, insubstrate 100, formdielectric layer 112, anddielectric layer 112 compliances be formed on the surface of groove 102.Dielectric layer 112 for example is as dielectric layer between metal layers (inter-metal dielectric, usefulness IMD).The material ofdielectric layer 112 is silica or other suitable dielectric materials for example, and its formation method for example is a chemical vapour deposition technique.

Please refer to Fig. 1 D, patterndielectric layer 112 removing the partdielectric layer 112 beyond thegroove 102, and forms the interlayer hole opening.The interlayer hole opening for example is to expose metal level 110.The formation method of interlayer hole opening for example is to finish by lithographic process and etching processing procedure.Afterwards, insubstrate 100, form layer of metal layer 114.Metal level 114 for example is to fill up the interlayer hole opening, and compliance be covered ongroove 102 surfaces.In one embodiment, the thickness that is formed atgroove 102 lip-deep metal levels 114 is about 3000

The material ofmetal level 114 for example is tungsten or other suitable metal materials, and its formation method for example is physical vaporous deposition or chemical vapour deposition technique.

Then, removepart metals layer 114, and in the interlayer hole opening, form conductive plunger 116.The method that removespart metals layer 114 for example be utilize the cmp processing procedure and withdielectric layer 112 as grinding suspension layer, to remove themetal level 114 beyond the interlayer hole opening and to make its flattening surface.Similarly, when carrying out the chemical machinery processing procedure, because the surface section of having ofsubstrate 100 is poor, therefore themetal level 114 that is formed in thegroove 102 can be retained and can not be removed.

Please refer to Fig. 1 E, insubstrate 100, form layer of metal layer 118.The material ofmetal level 118 for example is aluminium, copper or other suitable metal materials, and its formation method for example is physical vaporous deposition or chemical vapour deposition technique.Then, patternedmetal layer 118 is positioned at preformed detection padarea metal level 118 in addition to remove, and as the second layer metallayer.Metal level 118 behind the patterning for example is to be covered on theconductive plunger 116, and is covered on the surface of groove 102.Afterwards, insubstrate 100, formdielectric layer 120, anddielectric layer 120 compliances be covered on the surface of groove 102.Dielectric layer 120 for example is the usefulness as dielectric layer between metal layers.The material ofdielectric layer 120 is silica or other suitable dielectric materials for example, and its formation method for example is a chemical vapour deposition technique.

Please refer to Fig. 1 F, utilize similar above-mentioned method repeatedly insubstrate 100, to form metal level and conductive plunger.That is to say, indielectric layer 120, form the interlayer hole opening by lithographic process and etching processing procedure, and the interlayer hole opening for example is to expose metal level 118.Then, insubstrate 100, form layer of metal layer 122.Metal level 122 for example is to fill up the interlayer hole opening, and compliance be covered on the groove 102.In one embodiment, the thickness that is formed atgroove 102 lip-deep metal levels 122 is about 3000

The material ofmetal level 122 for example is tungsten or other suitable metal materials, and its formation method for example is physical vaporous deposition or chemical vapour deposition technique.Afterwards, utilize chemical mechanical milling method and removepart metals layer 122 as grinding suspension layer, and in the interlayer hole opening, formconductive plunger 124 with dielectric layer 120.Similarly, becausesubstrate 100 is poor in the surface section of having atgroove 102 places, themetal level 122 that therefore is positioned atgroove 102 still can be retained.Thereupon, insubstrate 100, form metal level 126.The material ofmetal level 126 for example is aluminium, copper or other suitable metal materials, and its formation method for example is physical vaporous deposition or chemical vapour deposition technique.Then, patternedmetal layer 126 is with as topmost metal layer (top metal layer).Metal level 126 behind the patterning for example is to cover on theconductive plunger 124, and covers on the surface ofgroove 102.

Please refer to Fig. 1 G, formprotective layer 128 insubstrate 100 comprehensive grounds.The material ofprotective layer 128 is selected from the group that silica, silicon nitride, silicon oxynitride, Pyrex (BSG), phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), other suitable insulation materials and combination thereof are formed.In one embodiment,protective layer 128 is made up ofsilicon nitride layer 128a andsilicon oxide layer 128b, and its formation method for example is a chemical vapour deposition technique.Afterwards, onprotective layer 128, formcover curtain layer 130, andcover curtain layer 130 exposes thesilicon nitride layer 128a that is positioned atgroove 102 places.The material ofcover curtain layer 130 for example is photoresist material or the material that has etching selection withsilicon nitride layer 128a.

Please refer to Fig. 1 H, serve as cover curtain and be the etching suspension layer, removeprotective layer 128 withmetal level 126 with cover curtain layer 130.Have the opening that exposespart metals layer 126 inprotective layer 128, it is so-called detection pad opening, and size for example is between 15 μ m * 15 μ m to 30 μ m * 30 μ m.Thereupon, remove cover curtain layer 130.Owing to be coated withprotective layer 128 on active element district on the wafer and the circuit region, therefore can protection component and circuit do not contact and be subjected to moisture or other pollutant effects with the external world, and prevent problems such as burning or damage.

In the above-described embodiments, be to be that example describes, yet the present invention is not limited to this with stacked multilayer conductive layer ongroove 102 surfaces (metal level 106,110,114,118,122,126) and dielectric layer 104,112,120.Fig. 2 is the generalized section according to a kind of probing pad structure of another embodiment of the present invention.In another embodiment, as shown in Figure 2, formed probing pad structure also can be only to be laminated with the conductive layer that multilayer is in contact with one another ongroove 102 surfaces, and promptly metal level 106,110,114,118,122,126.The formation method of probing pad structure shown in Figure 2 is identical generally with the formation method of the described probing pad structure of the foregoing description, its difference mainly is: removing each layer dielectric layer 104,112,120 when forming the step of contact window or interlayer hole opening, can will be formed atgroove 102 lip-deep dielectric layers 104,112,120 simultaneously removes respectively, therefore only can cover metal level 106,110,114,118,122,126 ongroove 102 surfaces, not be disposed between the metal level and do not have dielectric layer.

What specify is that when using probe to carry out testing electrical property, owing to probing pad structure of the present invention is formed in thegroove 102, so it can have less sectional area simultaneously and provide probe long coasting distance.And, when testing,, can also avoid probe when sliding, to skid off the scope of probing pad structure because probe is to contact with the metal level that is positioned at groove 102.In addition, the step that forms probing pad structure can be integrated in the conventional semiconductor processing procedure easily, does not therefore need to carry out extra complicated step, also can not cause the increase of processing procedure cost.

To be example below, probing pad structure of the present invention will be illustrated with Fig. 1 H.

Please refer to Fig. 1 H, for example be the Cutting Road district that is disposed at wafer at the described probing pad structure of this embodiment, but the present invention is not limited to this.Probing pad structure comprisessubstrate 100, multilayer conductive layer, conductive plunger 108,116,124, dielectric layer 104,112,120 andprotective layer 128, and wherein conductive layer comprises metal level 106,110,114,118,122,126.

Substrate 100 for example is a semiconductor crystal wafer, as N type Silicon Wafer, P type Silicon Wafer, three or five family's semiconductor crystal wafers etc.Substrate 100 hasgroove 102, and makes thesubstrate 100 surface sections of having poor.The size ofgroove 102 for example is between 15 μ m * 15 μ m to 30 μ m * 30 μ m.The last formed section difference insubstrate 100 surfaces for example is greater than 5 μ m.It should be noted thatgroove 102 designs according to follow-up preformed detection pad, that is the size of follow-up preformed detection pad is that size bygroove 102 decides.In one embodiment, the active element district in thesubstrate 100 can also dispose conductive part (not illustrating) or semiconductor element (not illustrating), and it for example is transistor or the element generally known.

Metal level 106 is disposed in thesubstrate 100, its for example be compliance be disposed on the surface of groove 102.The thickness ofmetal level 106 is about 3000

The material ofmetal level 106 for example is tungsten or other suitable metal materials.

Conductive plunger 108 is disposed in thegroove 102zone substrates 100 in addition.Conductive plunger 108 for example is as the contact hole connector, and its material for example is tungsten or other suitable metal materials.

Be disposed in thesubstrate 100 tometal level 110compliances.Metal level 110 for example is to be positioned at preformed detection pad area, that ismetal level 110 coversconductive plunger 108 and metal level 106.Metal level 110 for example is as the ground floor metal level.The material ofmetal level 110 for example is aluminium, copper or other suitable metal materials.

Dielectric layer 104 is disposed betweenmetal level 110 and the substrate 100.In detail,dielectric layer 104 ingroove 102 is to be disposed betweenmetal level 106 and thesubstrate 100,dielectric layer 104 beyondgroove 102 is to be disposed betweenmetal level 110 and thesubstrate 100, andconductive plunger 108 is to be disposed to be arranged ingroove 102dielectric layer 104 inaddition.Dielectric layer 104 is for example as interlayer dielectric layer.The material ofdielectric layer 104 is silica or other suitable dielectric materials for example.

Metal level 114 is disposed in thesubstrate 100, its for example be compliance be disposed on the surface of groove 102.The thickness ofmetal level 114 is about 3000

The material ofmetal level 114 for example is tungsten or other suitable metal materials.

Conductive plunger 116 is disposed in thegroove 102zone substrates 100 in addition, and it for example is to be disposed on the metal level 110.Conductive plunger 116 for example is as the interlayer hole connector, and its material for example is tungsten or other suitable metal materials.

Be disposed in thesubstrate 100 tometal level 118compliances.Metal level 118 for example is to coverconductive plunger 116 andmetal level 114, and as the second layer metal layer.The material ofmetal level 118 for example is aluminium, copper or other suitable metal materials.

Dielectric layer 112 is disposed betweenmetal level 110 and the metal level 118.In detail,dielectric layer 112 ingroove 102 is to be disposed betweenmetal level 110 and themetal level 114,dielectric layer 112 beyondgroove 102 is to be disposed betweenmetal level 110 and themetal level 118, andconductive plunger 116 is to be disposed to be arranged ingroove 102dielectric layer 112 inaddition.Dielectric layer 112 is for example as the usefulness of dielectric layer between metal layers, and its material for example silica or other suitable dielectric materials.

Metal level 122 is disposed in thesubstrate 100, its for example be compliance be disposed on the surface of groove 102.The thickness ofmetal level 122 is about 3000

The material ofmetal level 122 for example is tungsten or other suitable metal materials.

Conductive plunger 124 is disposed in thegroove 102zone substrates 100 in addition, and it for example is to be disposed on the metal level 118.Conductive plunger 124 for example is as the interlayer hole connector, and its material for example is tungsten or other suitable metal materials.

Be disposed in thesubstrate 100 tometal level 126compliances.Metal level 126 for example is to coverconductive plunger 124 andmetal level 122, and as topmost metal layer.The material ofmetal level 126 for example is aluminium, copper or other suitable metal materials.

Dielectric layer 120 is disposed betweenmetal level 126 and the metal level 118.In detail,dielectric layer 120 ingroove 102 is to be disposed betweenmetal level 122 and themetal level 118,dielectric layer 120 beyondgroove 102 is to be disposed betweenmetal level 126 and themetal level 118, andconductive plunger 124 is to be disposed to be arranged ingroove 102dielectric layer 120 inaddition.Dielectric layer 120 is for example as the usefulness of dielectric layer between metal layers, and its material for example silica or other suitable dielectric materials.

Protective layer 128 is disposed in the substrate 100.Protective layer 128 has opening, to expose themetal level 126 that is positioned atgroove 102 places.This opening is surveys the pad opening, and size for example is between 15 μ m * 15 μ m to 30 μ m * 30 μ m.The material ofprotective layer 128 is selected from the group that silica, silicon nitride, silicon oxynitride, Pyrex (BSG), phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), other suitable insulation materials and combination thereof are formed.In one embodiment,protective layer 128 is made up ofsilicon nitride layer 128a and silicon oxide layer 128b.Protective layer 128 can be protected active element district on the wafer and circuit region not to contact with the external world and be subjected to moisture or other pollutant effects, and avoids problems such as burning or damage.

In addition, in another embodiment, probing pad structure as shown in Figure 2 also can be only to dispose multiple layer metal layer 106,110,114,118,122,126 ongroove 102 surfaces.Probing pad structure shown in Figure 2 is identical generally with the feature of the probing pad structure shown in Fig. 1 H, its difference mainly is: groove can't dispose dielectric layer 104,112,120 on 102 surfaces, and only can dispose metal level 106,110,114,118,122,126 in stacked mode.

In sum, probing pad structure of the present invention and manufacture method thereof, therefore can have less sectional area simultaneously and provide probe long coasting distance as surveying pad by configuration metal level in groove.When testing,, can also avoid probe when sliding, to skid off the scope of probing pad structure because probe is to contact with the metal level that is positioned at groove.

Moreover probing pad structure of the present invention has less sectional area, can help to improve the space availability ratio of wafer.The manufacture method of probing pad structure of the present invention can also be integrated in the conventional semiconductor processing procedure easily, does not therefore need to carry out extra complicated step, also can not cause the increase of processing procedure cost.

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.

Claims (21)

1. probing pad structure is suitable for being configured in the Cutting Road district of wafer, comprising:

One substrate, this substrate has a groove;

At least one conductive layer is disposed in this substrate, and this conductive layer comprises:

One the first metal layer is disposed on this groove; And

One second metal level is disposed on this first metal layer, and extends in this substrate in addition of this groove; And

One protective layer is disposed on this conductive layer, and this protective layer has an opening, and this opening is to position that should groove and dispose.

2. probing pad structure as claimed in claim 1 is characterized in that, when having a plurality of this conductive layer, those conductive layers dispose in stacked mode.

3. probing pad structure as claimed in claim 2 is characterized in that, also comprises at least one conductive plunger, is disposed in this substrate in addition of this groove, and this conductive plunger connects each those conductive layer.

4. probing pad structure as claimed in claim 3 is characterized in that, this conductive plunger connects each those second metal level.

5. probing pad structure as claimed in claim 2 is characterized in that, also comprises a dielectric layer, is disposed between each those conductive layer.

6. probing pad structure as claimed in claim 2 is characterized in that, each those conductive layer contacts with each other.

7. probing pad structure as claimed in claim 1 is characterized in that, the size of this groove is between 15 μ m * 15 μ m to 30 μ m * 30 μ m.

8. probing pad structure as claimed in claim 1 is characterized in that, this substrate surface is greater than 5 μ m in the section difference of this groove.

9. probing pad structure as claimed in claim 1 is characterized in that, this opening of this protective layer exposes this second metal level.

10. probing pad structure as claimed in claim 1 is characterized in that, this protective layer comprises an one silica layer and a silicon nitride layer.

11. the manufacture method of a probing pad structure, this probing pad structure are suitable for being configured in the Cutting Road district of wafer, comprising:

One substrate is provided;

Remove this substrate of part, to form a groove;

In this substrate, form at least one conductive layer, comprising:

On this groove, form a first metal layer; And

Form one second metal level in this substrate, this second metal level compliance ground covers this first metal layer and extends in this substrate in addition of this groove; And

On this conductive layer, form a protective layer, and this opening disposes to position that should groove with an opening.

12. the manufacture method of probing pad structure as claimed in claim 11 is characterized in that, when forming a plurality of this conductive layer, those conductive layers dispose in stacked mode.

13. the manufacture method of probing pad structure as claimed in claim 12 is characterized in that, before forming this conductive layer, also comprises:

In this substrate, form a dielectric layer;

Remove this dielectric layer of part, to form at least one plug open in this dielectric layer beyond this groove; And

In this plug open, form a conductive plunger.

14. the manufacture method of probing pad structure as claimed in claim 13 is characterized in that, forms this conductive plunger and carry out simultaneously with this first metal layer of formation in this plug open.

15. the manufacture method of probing pad structure as claimed in claim 13 is characterized in that, this conductive plunger connects each those second metal level.

16. the manufacture method of probing pad structure as claimed in claim 13 is characterized in that, also comprises removing this dielectric layer that is positioned on this groove.

17. the manufacture method of probing pad structure as claimed in claim 11 is characterized in that, the size of this groove is between 15 μ m * 15 μ m to 30 μ m * 30 μ m.

18. the manufacture method of probing pad structure as claimed in claim 11 is characterized in that, this substrate surface is greater than 5 μ m in the section difference of this groove.

19. the manufacture method of probing pad structure as claimed in claim 11 is characterized in that, the method that forms this groove comprises the laser machine at quarter that uses.

20. the manufacture method of probing pad structure as claimed in claim 11 is characterized in that, the method that forms this groove comprises uses alignment mark photomask or irrigation canals and ditches photomask.

21. the manufacture method of probing pad structure as claimed in claim 11 is characterized in that, the formation method of this protective layer comprises:

In this substrate, form one silica layer;

In this substrate, form a silicon nitride layer; And

Remove this silicon oxide layer of part and this silicon nitride layer, to expose this second metal level that is positioned at this groove.

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