CN101593695B - Method for solving power field effect tube wafer bending - Google Patents

Abstract

The invention provides a method for reducing a wafer bending degree of a power field effect tube in a manufacturing procedure of contact, which comprises the following steps: a light resistor with a set characteristic size of larger than or equal to 1.3 um is placed at the surface of a P-type semiconductor substrate; N-type ions are injected into areas of both sides of the light resistor of the P-type semiconductor substrate; then, the light resistor is removed, and the N-type ion injection areas are etched so as to form a sunk area. The characteristic size of the light resistor used by the invention is increased to more than 1.3 um from 0.7 um in the prior art, because of the shielding of the light resistor with larger characteristic size, the distance between the N-type ion injection areas at both sides can be increased after the ions are injected, and a connecting part of the diffused ions at both sides is smaller even after a working procedure of high temperature, therefore, the method can reduce the etching depth of the sunk contact area, effectively reduces the wafer bending degree and ensures the smooth completion of the manufacturing procedure of a power field effect tube wafer.

Description

The solution of power field effect tube wafer bending

Technical field

The present invention relates to a kind of wafer contact procedure method of power field effect pipe, and be particularly related to a kind of power field effect pipe and in contact procedure, reduce the wafer bending degree methods.

Background technology

During the developing manufacture process of the wafer of power field effect pipe after exposure, the vacuum pump that little shadow machine can take place can't hold wafer, and processing procedure is terminated, and the situation that wafer is scrapped, reason are that crooked phenomenon has taken place the wafer of power field effect pipe.And the reason of wafer bending mainly is that one procedure is arranged in the contact procedure is to make the processing procedure of contact depressed area, it is after contact etch, on silicon layer, also to dig certain depth, to separate the ion implanted region territory of these both sides, contact depressed area, this depressed area is drawn lead in order to the formation contact zone and is contacted with outer member.The design of some power field effect pipe designs into strips, and the groove of power field effect tube wafer all is that strip and direction are identical with the depressed area, and groove and depressed area all are to want etch silicon layer, and cause the bending of wafer in the process of etch silicon layer probably.Please refer to Fig. 1 and Fig. 2, the wafer that Figure 1 shows that power field effect pipe in the prior art carries out utilizing in the contact procedure photoresistance to carry out the schematic diagram that ion injects, and Figure 2 shows that the wafer of power field effect pipe in the prior art carries out the schematic diagram in etching notched district in the contact procedure.Form this processing procedure of depressed area with etching, placing a characteristic size on the zone between thegroove 110 at the semiconductor-basedend 100 in the prior art for example is thephotoresistance 130 of 0.7um, be perfused withpolysilicon 120 in the wherein above-mentioned groove, and then ion is carried out in thezone 140 of thesephotoresistance 130 both sides inject, with Ptype semiconductor substrate 100 is example, the ion that injects is a N type ion, carry out a high temperature process afterwards, in high temperature process, the N type ion in twoparts zone 140 can spread and partly connect together, this just need be etched with this part that connects together and formdepression contact zone 150, and this etching must be dug the operate as normal that the Ntype ion zone 140 of wearing the part that links to each other could guarantee device, the silicon layer that for the wafer of thephotoresistance 130 that uses the 0.7um characteristic size, needs the etching 4000A degree of depth, however be easy to cause the bending of wafer at the silicon layer of the chip etching degree of depth like this of power field effect pipe.

Summary of the invention

The object of the present invention is to provide a kind of power field effect pipe to reduce the wafer bending degree methods in contact procedure, this method can effectively reduce the degree of wafer bending, the finishing smoothly of guaranteed output field effect tube wafer processing procedure.

To achieve these goals, the present invention proposes a kind of power field effect pipe and reduce the wafer bending degree methods in contact procedure, and it comprises the following steps: to provide the P type semiconductor substrate; Place photoresistance with setting characteristic size at above-mentioned P type semiconductor substrate surface; The two side areas of the above-mentioned photoresistance of above-mentioned P type semiconductor substrate is carried out N type ion to be injected; Take away photoresistance and form the depressed area to carrying out etching between the above-mentioned N type ion implanted region territory, wherein the setting characteristic size of above-mentioned photoresistance is more than or equal to 1.3um.

Further, wherein above-mentioned P type semiconductor substrate has a plurality of grooved area, is perfused with polysilicon in the above-mentioned groove.

Further, wherein above-mentioned photoresistance is positioned over the intermediate surface of the above-mentioned P type semiconductor substrate between two grooves.

Further, wherein after above-mentioned N type ion implantation step, more comprise high temperature process.

Further, the step that wherein above-mentioned etching forms the depressed area is the mid portion in above-mentioned two the N type ion implanted region territories of etching, so that above-mentioned two N type ion implanted region territories are kept apart by the depressed area.

Further, wherein above-mentioned depressed area is drawn lead and is contacted with outer member in order to form the contact zone.

Further, wherein the degree of depth of above-mentioned depressed area is smaller or equal to 1000A.

The power field effect pipe that the present invention proposes reduces the wafer bending degree methods in contact procedure, have the photoresistance of setting characteristic size in the placement of P type semiconductor substrate surface more than or equal to 1.3um, the two side areas of the above-mentioned photoresistance of above-mentioned P type semiconductor substrate is carried out N type ion to be injected, take away photoresistance then and form the depressed area carrying out etching between the above-mentioned N type ion implanted region territory, so that above-mentioned two N type ion implanted region territories are kept apart by the depressed area, the characteristic size of photoresistance used in the present invention is increased to more than the 1.3um from the 0.7um of previous technology, like this because covering than the photoresistance of large-feature-size, after ion injects, can strengthen the distance in N ion implanted region territories, both sides, even if after high-temperature process, the part that the ion of both sides diffusion links to each other is also fewer, so just can reduce the etch depth of depression contact zone, the degree of depth of depressed area can be tapered to below the 1000A from 4000A, so just can effectively reduce the degree of wafer bending, thereby guarantee finishing smoothly of power field effect tube wafer processing procedure.

Description of drawings

Figure 1 shows that wafer carries out utilizing in the contact procedure photoresistance to carry out the schematic diagram that ion injects in the prior art.

Figure 2 shows that wafer in the prior art carries out the schematic diagram in etching notched district in the contact procedure.

Figure 3 shows that wafer carries out utilizing in the contact procedure photoresistance to carry out the schematic diagram that ion injects in a preferred embodiment of the present invention.

Figure 4 shows that wafer in a preferred embodiment of the present invention carries out the schematic diagram in etching notched district in the contact procedure.

Embodiment

In order more to understand technology contents of the present invention, especially exemplified by preferred embodiment and cooperate appended graphic being described as follows.

The power field effect pipe that the present invention proposes reduces the wafer bending degree methods in contact procedure, it comprises the following steps: to provide the P type semiconductor substrate; Place photoresistance with setting characteristic size at above-mentioned P type semiconductor substrate surface; The two side areas of the above-mentioned photoresistance of above-mentioned P type semiconductor substrate is carried out N type ion to be injected; Take away photoresistance and form the depressed area to carrying out etching between the above-mentioned N type ion implanted region territory, wherein the setting characteristic size of above-mentioned photoresistance is more than or equal to 1.3um.

Please refer to Fig. 3 and Fig. 4, Figure 3 shows that wafer in a preferred embodiment of the present invention carries out utilizing in the contact procedure photoresistance to carry out the schematic diagram that ion injects, Figure 4 shows that wafer in a preferred embodiment of the present invention carries out the schematic diagram in etching notched district in the contact procedure.From Fig. 3 and Fig. 4 as can be seen, Ptype semiconductor substrate 200 provided by the present invention has a plurality ofgrooved area 210, and be perfused withpolysilicon 220 in thegroove 210, to have the photoresistance 230 of setting characteristic size is placed on the intermediate surface of the above-mentioned Ptype semiconductor substrate 200 between above-mentioned twogrooves 210, then the N ion being carried out in Ptype semiconductor substrate 200 zones of above-mentioned photoresistance 230 both sides injects, form two N type ion implantedregion territories 240, and between the zone because covering of photoresistance 230 can not be injected into N type ion, simultaneously because the characteristic size of the photoresistance 230 that preferred embodiment of the present invention is adopted is more than or equal to 1.3um, promptly the photoresistance than the 0.7um that prior art adopted is big, so the distance that two N type ion implantedregion territories 240 are separated by is bigger, even after high temperature process subsequently, two N type ion implantedregion territories 240 yet can not connect together or only have part seldom to connect because of diffusion.Remove above-mentioned photoresistance 230 then to carry out the step of etching formationdepressed area 250, the mid portion in above-mentioned two the N type ion implantedregion territories 240 of etching, so that above-mentioned two N type ion implantedregion territories 240 are kept apart bydepressed area 250, wherein above-mentioneddepressed area 250 is to draw lead and the contacted zone of outer member in order to form the contact zone, because the characteristic size of the photoresistance 230 that preferred embodiment of the present invention is adopted is more than or equal to 1.3um, promptly the photoresistance than the 0.7um that prior art adopted is big, while two N type ion implantedregion territories 240 also do not connect together or only have part seldom to connect, therefore only need etching seldom the silicon layer of the degree of depth just can form qualified depression contact zone, the degree of depth of the above-mentioned depressed area of etching of carrying out according to preferred embodiment of the present invention is smaller or equal to 1000A.

The power field effect pipe that the present invention proposes reduces the wafer bending degree methods in contact procedure, have the photoresistance of setting characteristic size in the placement of P type semiconductor substrate surface more than or equal to 1.3um, the two side areas of the above-mentioned photoresistance of above-mentioned P type semiconductor substrate is carried out N type ion to be injected, take away photoresistance then and form the depressed area carrying out etching between the above-mentioned N type ion implanted region territory, so that above-mentioned two N type ion implanted region territories are kept apart by the depressed area, the characteristic size of photoresistance used in the present invention is increased to more than the 1.3um from the 0.7um of previous technology, like this because covering than the photoresistance of large-feature-size, after ion injects, can strengthen the distance in N ion implanted region territories, both sides, even if after high-temperature process, the part that the ion of both sides diffusion links to each other is also fewer, so just can reduce the etch depth of depression contact zone, the degree of depth of depressed area can be tapered to below the 1000A from 4000A, so just can effectively reduce the degree of wafer bending, thereby guarantee finishing smoothly of power field effect tube wafer processing procedure.

Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.

Claims (7)

1. a power field effect pipe reduces the wafer bending degree methods in contact procedure, it is characterized in that comprising the following steps:

The P type semiconductor substrate is provided;

Place photoresistance with setting characteristic size at above-mentioned P type semiconductor substrate surface;

The two side areas of the above-mentioned photoresistance of above-mentioned P type semiconductor substrate is carried out N type ion to be injected;

Take away photoresistance and form the depressed area carrying out etching between the above-mentioned N type ion implanted region territory,

Wherein the setting characteristic size of above-mentioned photoresistance is more than or equal to 1.3 microns.

2. minimizing wafer bending degree methods according to claim 1 is characterized in that wherein above-mentioned P type semiconductor substrate has a plurality of grooved area, is perfused with polysilicon in the above-mentioned groove.

3. minimizing wafer bending degree methods according to claim 2 is characterized in that wherein above-mentioned photoresistance is positioned over the intermediate surface of the above-mentioned P type semiconductor substrate between two grooves.

4. minimizing wafer bending degree methods according to claim 1 is characterized in that wherein more comprising high temperature process after above-mentioned N type ion implantation step.

5. minimizing wafer bending degree methods according to claim 1, the step that it is characterized in that wherein above-mentioned etching formation depressed area is the mid portion in above-mentioned two the N type ion implanted region territories of etching, so that above-mentioned two N type ion implanted region territories are kept apart by the depressed area.

6. minimizing wafer bending degree methods according to claim 1 is characterized in that wherein above-mentioned depressed area draws lead and contact with outer member in order to form the contact zone.

7. minimizing wafer bending degree methods according to claim 1 is characterized in that wherein the degree of depth of above-mentioned depressed area is smaller or equal to 1000.

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