CN101546286A - Method and device for logic analysis of high-speed serial bus - Google Patents

Abstract

The invention provides a method and a device for the logic analysis of a high-speed serial bus. The method comprises the following steps: receiving a bus signal of the high-speed serial bus; copying the bus signal with a signal shunting module to generate a first signal and a second signal; feeding the first signal back to the high-speed serial bus; and resolving the second signal to acquire parallel data. Through the shunting processing of the signal in the high-speed serial bus, the use of the one path of shunt signal obtain in logic analysis through resolution, and the feedback of the other path of shunt signal to the high-speed serial bus, the method can analyze data transmitted in the high-speed serial bus under a condition of not influencing the data transmission of the high-speed serial bus.

Description

A kind of high-speed serial bus analytics and device

Technical field

The present invention relates to a kind of high-speed serial bus analytics and device, belong to data communication technology field.

Background technology

The interconnected local bus that often adopts between CPU (central processing unit) (Central Process Unit is called for short CPU) and the peripheral components thereof is as peripheral component interconnection (Peripheral ComponentInterconnect is called for short PCI) local bus.Along with development of technology, more and more higher to the data rate requirement of local bus, so high-speed serial bus is born thereupon.At present the high-speed serial bus that occurs is varied, and nonstandardized technique is arranged, and also has standardized, peripheral component high-speed interconnect standard (PCI Express for example, be called for short PCIE) universal serial bus, PCIE is a kind of high-speed serial bus standard, these high-speed serial bus often have following characteristics:

(1) point-to-point connection is adopted in the connection of bus between device.

(2) only form by sending data bus and receiving data bus, and do not have synchronous clock bus and other control bus, the band inner control is adopted in the control and management of bus.So-called band inner control is meant the method that managing control information and data message use unified physical channel to transmit; The outer control of band is opposite with the band inner control, is meant by the different physical channel independence transfer management control informations and the method for data message.

(3) the synchronous clock bus is mixed in the data bus, extracts synchronous clock at receiving end by the clock recovery device in the receiving trap.

(4) owing to do not control bus outside the band, need to adopt band inner control agreement to carry out total line traffic control, for the data of distinguishing band inner control command word and being transmitted, need (can be 4-bit (bit to control command word waiting for transmission and data, be called for short b) data or 8-bit data) carry out extended coding, so that distinguish data and control command word, as the 8b/10b coding of PCI Express, the character code that is about to 8bit is converted into the character code of 10bit through the mechanism of mapping.The effect of 8b/10b coding is that 0 and 1 number is reached unanimity substantially, reaches the direct current equilibrium, and guaranteeing has enough hopping edges so that the clock recovery device of receiver can recover synchronous clock.

(5) in order to reduce the noise and the electromagnetic interference (EMI) of high-speed bus transmission, often carry out data transmission with the differential mode transmission manner.Difference mode signal is meant equal and opposite in direction, the direction pair of opposite signal, and the transmission of difference mode signal is called the differential mode transmission.

(6) in order to reduce the required energy of bus transfer, except each word waiting for transmission being carried out the 8b/10b coding, also in transmitter, before the 8b/10b coding, carry out the scrambler operation earlier, promptly adopt special data sequence (as pseudo-random sequence) and data character code to be sent to multiply each other, carry out conversion to sent the data character code, do having guaranteed can not repeat for a long time on the transmission signal line a certain specific sequence string like this, a certain space double vibrations electric flux and magnetic energy externally send on the transmission signal line thereby reduce.Adopt corresponding descrambler to parse data at receiving end.

Because the data of transmitting on universal serial bus have been passed through aforesaid technical finesse, are not common binary-coded data sequences, make people directly to observe the data sequence of being transmitted on the high-speed serial bus by oscillograph.When people carry out system debug, test, transmission performance analysis or efficiency analysis, only use oscillograph can't finish.

The bus data analysis often is very important in system debug test and system effectiveness analysis, for example: the system delay analysis, performance evaluation, fault analysis, or even device issue track location etc.

In order to finish the purpose of system debug test and systematic analysis, the logic analyser that people are accustomed to adopting professional equipment producer to provide is analyzed the data transmission on the bus.Its method of testing as shown in Figure 1.Equipment 001 is PCIE root node equipment (PCIE Root Complex, be called for short PCIE RC),equipment 003 is PCIE endpoint device (PCIE Endpoint),equipment 001 andequipment 003 sendbus 002 by PCI Express and PCI Expressreception bus 004 is interconnected, 003 and 004 is collectively referred to as universal serial bus, and universal serial bus is of coupled connections by ac coupling capacitor 007.Provinginstallation logic analyser 006 uses miniature connecting line type A (SubMiniature version A, being called for short SMA)test cable 005 is connected to PCI Express and sends and receive bus and obtain data sequence on the transfer bus, and logic analyser is data that can Direct observation with the decoded data sequence that obtains.Ac coupling capacitor is can the isolated DC common mode electrical level, and guarantees that the energy of position signal that changes can expedite capacitor in the two ends transmission; SMA test cable is a kind of high speed signal test that is specifically designed to, and connects the cable of signal to be tested to proving installation.

Adopt the high-speed serial bus logic analyser can arrive the purpose of bus data transimiison analysis.But the logic analyser that specialized factory provides often costs an arm and a leg, and utilization factor is not high, often can't reach desirable cost performance for non-large-scale debugging test, and general Application Design producer is unwilling to bear the testing apparatus of this costliness.

Because PCI Express bus is a kind of high-speed serial bus of point-to-point connection,, often requirePCIE endpoint device 003 is disconnected in addition, carry out simulation test and replaceequipment 003 with logic analyser in order to guarantee the reliability of transmission signals.The shortcoming of doing like this is to test by direct-on-line, can't use in some occasion (as location of mistake).

In order to realize online detection, some logic analysis producer has adopted by centre bus sniffer (Mid Bus Prober) and has connected the method for logic analyser to the PCIE bus, as shown in Figure 2.008 and 009 of centre bus sniffer such as Fig. 2.The principle of work of this device is: reserve the sensing point that the centre bus sniffer is installed on former bus, the centre bus sniffer is installed on the sensing point of reservation, the sub-fraction energy of the signal that the centre bus sniffer obtains on the bus to be transmitted from bus by sensing point, then this extremely low-energy signal is amplified and shaping on device, be sent to logic analyser by the high-speed transfer cable again.In order not influence the transmission of former bus, the centre bus sniffer must be the device of a kind of high impedance, low electric capacity, and must have the ability that high speed signal is amplified.Because above three characteristics, the centre bus sniffer need adopt the device with extraordinary electrical specification, and its cost is that cost is high relatively, and design is complicated.Simultaneously,, unavoidably the signal on the former bus is exerted an influence,, cause test inaccurate if connect the improper distorted signals that might make on the former bus because the centre bus sniffer is to take out portion of energy from bus.In addition, because the centre bus sniffer is a kind of electromechanical device of relative complex, its volume ratio is bigger, in some highdensity designs, often can't reserve the space of placing the centre bus sniffer.

Summary of the invention

The purpose of this invention is to provide a kind of high-speed serial bus analytics and device, under the situation that does not influence the high-speed serial bus data transmission, promptly can realize the transmission data on the high-speed serial bus are analyzed.

For achieving the above object, the invention provides a kind of high-speed serial bus analytics, described method comprises:

Receive the bus signals of high-speed serial bus, described bus signals is copied as first signal and secondary signal, first signal is returned described high-speed serial bus, and secondary signal resolved obtain parallel data by the signal shunt module.

To achieve these goals, the present invention also provides a kind of high-speed serial bus logic analysis unit, and described device comprises signal shunt module and signal resolution module;

Described signal shunt module is used for described bus signals is copied as first signal and secondary signal, and first signal is returned described high-speed serial bus, and secondary signal is sent to signal resolution module;

Described signal resolution module is connected with the signal shunt module, is used for secondary signal resolved obtaining parallel data.

The invention provides a kind of easy use high-speed serial bus analytics and device cheaply, handle by the signal on the high-speed serial bus being carried out shunt, the shunting sign that obtains is leaded up to resolve and is used for logic analysis, one the tunnel returns high-speed serial bus, under the situation that does not influence the high-speed serial bus data transmission, promptly can analyze the transmission data on the high-speed serial bus, and simplicity of design, cost is lower.

Description of drawings

Fig. 1 is prior art high-speed serial bus logic analysis scheme one synoptic diagram

Fig. 2 is prior art high-speed serial bus logic analysis scheme two synoptic diagram

Fig. 3 is a kind of high-speed serial bus analytics of the present invention embodiment one synoptic diagram

Fig. 4 is a kind of high-speed serial bus analytics of the present invention embodiment two synoptic diagram

Fig. 5 is a kind of high-speed serial bus analytics of the present invention embodiment three synoptic diagram

Fig. 6 is a kind of high-speed serial bus analytics of the present invention embodiment four synoptic diagram

Fig. 7 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment one synoptic diagram

Fig. 8 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment two synoptic diagram

Fig. 9 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment three synoptic diagram

Figure 10 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment four synoptic diagram

Figure 11 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment five synoptic diagram

Figure 12 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment six synoptic diagram

Embodiment

The invention provides a kind of high-speed serial bus analytics, Fig. 3 has provided a kind of high-speed serial bus analytics of the present invention embodiment one synoptic diagram, said method comprising the steps of:

Step S1, the bus signals of reception high-speed serial bus;

Step S2 copies as first signal and secondary signal by the signal shunt module with described bus signals;

For example can described bus signals be copied as first signal and secondary signal by the high-frequency clock driver, the high-frequency clock driver is a kind of electric current and voltage and fan-out capability that is used to increase clock signal, or one tunnel clock signal is strengthened the device of exporting for multichannel.

The inventor finds in implementing process of the present invention, the high-frequency clock driver can carry out shunt to any high-speed serial bus signal through the direct current equilibrium treatment, its principle of carrying out shunt is as follows: because the PCIE physical signalling is the direct current equalizing signal through the 8b/10b coding, be that coding in each 10bit character code of transmitting on the signal transmssion line all guarantees the hopping edge of 0 enough level translation to 1 level or 1 level translation to 0 level, the quantity of 0 level that occurs in each character code and 1 level is in a basic balance simultaneously.PCIE bus per second can transmit 2.5G bit level signal in PCI Express 1.0 standards, and PCIE bus per second can transmit 5G bit level signal in PCIExpress 2.0 standards.If 0 level and 1 level of each character code of PCIE transmission alternately occur, then the PCIE physical signalling is exactly the clock signal of a 1.25G hertz (Hz) or 2.5GHz.And the 8b/10b coding is several 0 and several 1 signal that alternately occurs, therefore the PCIE physical signalling can be regarded a clock signal that changes as near variation or 2.5GHz near the 1.25GHz, this clock signal can adopt the high-frequency clock driver that its driving is copied as two-way output, the original signal transmission path is returned in a road of two-way output, the transmission of continuity original signal, other one the tunnel uses for analytical test.Because PCI Express 1.0 signal frequencies are up to 1.25GHz, PCI Express 2.0 signal frequencies are up to 2.5GHz, and therefore the high-frequency clock driver of designed logic analysis unit need select for use the high speed device that can drive more than the 1.25GHz maybe can drive the above high speed device of 2.5GHz.

The present invention is applicable to the logic analysis to the high-speed serial bus of any process direct current equilibrium treatment, comprise and be not limited to the PCIE universal serial bus, for example also comprise 10 gigabit Ethernet accessory unit interfaces (XAttachment Unit Inte rface, be called for short XAUI) universal serial bus, the 4th grade of the 2nd stage (System Packet Interface Level 4 Phase 2 of system's packet interface, be called for short SPI4.2) universal serial bus, serial gigabit Media Independent Interface (Serial Gigabit Media IndependentInterface, be called for short SGMII), the quick input and output agreement of serial (Serial RapidInput/Output is called for short SRIO) etc.

Step S3 returns first signal to described high-speed serial bus;

Step S4 resolves secondary signal and to obtain parallel data, is specifically as follows: secondary signal is carried out descrambling and decoding obtains parallel data.For example, because bus signals is the signal through scrambler is operated and the 8b/10b coding obtains, therefore can resolve secondary signal by descrambling and 8b/10b decoding, obtain parallel data, supervisory control signals, synchronizing clock signals and the bus state indicator signal of 8bit or 16bit.

Fig. 4 has provided a kind of high-speed serial bus analytics of the present invention embodiment two synoptic diagram, and present embodiment also comprises except the step that comprises method embodiment one:

Step S5 stores described parallel data.Specifically can pass through field programmable gate array (Field-Programmable Gate Array, be called for short FPGA) parallel data is stored in the internal memory, for example described internal memory can be second generation double-speed Synchronous Dynamic Random Access Memory (Double Data Rate 2Synchronous Dynamic Random Access Memory is called for short DDR2 SDRAM).FPGA is as special IC (Application Specific Integrated Circuit, abbreviation ASIC) a kind of semi-custom circuit in the field occurs, both solve the deficiency of custom circuit, overcome the limited shortcoming of original programming device gate circuit number again.Parallel data stored be convenient to that data are sent to terminal and analyze and show.

Fig. 5 has provided a kind of high-speed serial bus analytics of the present invention embodiment three synoptic diagram, and present embodiment also comprises except the step that comprises embodiment two:

Step S6 is sent to the universal asynchronous receiving-transmitting terminal with described parallel data and preserves or show.Described universal asynchronous receiving-transmitting terminal is the centralized host computer system of a kind of universal asynchronous receiving-transmitting, for example can be personal computer (Personal Computer is called for short PC) terminal.Described parallel data is sent to the universal asynchronous receiving-transmitting terminal to be convenient to long data are preserved, analyzed and show.

Fig. 6 has provided a kind of high-speed serial bus analytics of the present invention embodiment four synoptic diagram, and present embodiment also comprises except the step that comprises embodiment one:

Step S7 outputs to oscillograph with described parallel data.Specifically can use oscilloprobe to survey and resolve the parallel data that obtains, and send to oscillograph, thereby realize real-time monitored data on the high-speed serial bus.

Present embodiment also can carry out above-mentioned expansion on the basis of method embodiment two and method embodiment three.

The present invention also provides a kind of high-speed serial bus logic analysis unit, and Fig. 7 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment one synoptic diagram, and described device comprises: signal shunt module M1 and signal resolution module M2;

Described signal shunt module M1 is used for described bus signals is copied as first signal and secondary signal, first signal is returned described high-speed serial bus, and secondary signal is sent to signal resolution module M2;

Described signal shunt module is specifically as follows the high-frequency clock driver, and the high-frequency clock driver heavily drives the bus signals of high-speed serial bus such as PCIE system and is two-way, and one the tunnel returns original system, and one the tunnel is used for test.

Described signal resolution module M2 is connected with signal shunt module M1, is used for secondary signal resolved obtaining parallel data.

Described signal resolution module is specifically as follows PCIE physical layer interface device (PCIE PHY), secondary signal is carried out descrambling to use PCIE PHY and decoding obtains parallel data, PCIE PHY is device or a device of realizing PCIE agreement physical layer function, can realize descrambling and decoding to the PCIE signal.For example, because bus signals is the signal through scrambler is operated and the 8b/10b coding obtains, therefore can use PCIEPHY that secondary signal is carried out descrambling and 8b/10b decoding, obtain parallel data, supervisory control signals, synchronizing clock signals and the bus state indicator signal of 8bit or 16bit.

Fig. 8 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment two synoptic diagram, present embodiment also comprises memory module M3 except the architectural feature that comprises device embodiment one, M2 is connected with signal resolution module, be used to receive described parallel data, and store described parallel data.

Fig. 9 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment three synoptic diagram, and present embodiment also is divided into described memory module M3 field programmable gate array unit M31 and internal storage location M32 except the architectural feature that comprises device embodiment two;

Described field programmable gate array unit M31 is used to receive described parallel data, carries out buffer memory, and sends to internal storage location M32;

Described internal storage location M32 is connected with field programmable gate array unit M31, is used to store described parallel data.

Described field programmable gate array unit is specifically as follows FPGA, and memory modules can be DDR2SDRAM.

Described high-speed serial bus logic analysis unit can also comprise the universal asynchronous receiving-transmitting terminal, is used to receive the described parallel data that described field programmable gate array unit sends, and preserves or show.

Described high-speed serial bus logic analysis unit can also comprise oscillograph, is used for the described parallel data that the received signal parsing module sends, and shows.

Figure 10 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment four synoptic diagram, present embodiment also is divided into described field programmable gate array unit M31 and resolves interface controller M311, memory i/f controller M312, global controller M313 and universal asynchronous receiving-transmitting terminal interface controller M314 except the architectural feature that comprises device embodiment three;

Described parsing interface controller M311 is used for parallel data that the received signal parsing module the sends row cache of going forward side by side, and sends to memory i/f controller M312 then;

Described memory i/f controller M312 is connected with parsing interface controller M311, is used for storing parallel data into internal storage location M32, and reads the parallel data of internal storage location M32 storage and send to global controller M313;

Described global controller M313 is connected with memory i/f controller M312 with parsing interface controller M311, is used for parallel data is read from internal storage location M32 by memory i/f controller M312, and sends to universal asynchronous receiving-transmitting terminal interface controller M314;

Described universal asynchronous receiving-transmitting terminal interface controller M314 is connected with global controller M313, is used for that the parallel data that global controller M313 sends is sent to the asynchronous communication terminal and stores and show.

Figure 11 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment five synoptic diagram, and present embodiment is the more excellent embodiment of the present invention.

Present embodiment high speed universal serial bus is PCIE, and the PCIE system is by PCIEroot node equipment 114,PCIE endpoint device 121, and PCIE sends bus 115,119 and PCIE receives bus 116,120, and busac coupling capacitor 117 and 118 is formed.When 115,117, the 119 transmission bus requirementses of forming carried out the logic analysis test, 117 ac coupling capacitors need remove.

Described high-speed serial bus logic analysis unit is by forming as lower member: high-frequency clock driver 102,PCIE PHY 105,FPGA 110,DDR2 sdram memory 106, universal asynchronous receiving-transmitting (UniversalAsynchronous Receiver/Transmitter is called for short UART) terminal andoscillograph 113.

Described high-frequency clock driver can be clock driver ICS858011, and PCIE PHY can be PCIEPHY XIO1100.

High-frequency clock driver 102 obtains the PCIE bus signals bybus 101, the PCIE bus signals of PCIE system heavily driven be two-way, thebus 104 of leading up to is returned original system as the system communication passage, and one the tunnel is used for test, sends toPCIE PHY 105 bybus 103.

PCIE PHY 105 decodes heavily driving the PCIE serial bus signal that obtains, and be converted to parallel 8bit or 16bit signal, and send to FPGA 110 bybus 107, be example with parallel 8bit data-signal below.

FPGA 110 bybus 109 with decoded Parallel PC IE data storage inDDR2 sdram memory 106, and in needs, it is sent to the preservation of universal asynchronous receiving-transmitting terminal or shows that described universal asynchronous receiving-transmitting terminal can be the PC terminal byversabus 111.

The detection system that oscilloprobe 108 andoscillograph 113 are formed can be surveyed the parallel data signal of PCIE PHY output, thus the data on all right real-time monitored PCIE data bus.

Bus 101 is connected to 115 buses in the PCIE to be measured system.Because theac coupling capacitor 117 in this moment PCIE to be measured system has removed, the signal flow of 115 buses does not flow tobus 119 to bus 101.The signal thatbus 101 is taken out is input to high-frequency clock driver 102, heavily driven to two-way PCIE physical signalling outputs tobus 103 andbus 104 respectively by the input signal of high-frequency clock driver 102 withbus 101, the signal on thismoment bus 103 and thebus 104 is the duplicating of signal on thebus 115 fully.The signal ofbus 104 uses SMA test cable to reconnect tobus 119 in the former PCIE system, guarantees that the communication path of former bus does not interrupt, and promptly keeps original signal transmission.Signal on thebus 103 then as the original signal of taking out from bus, uses for subsequent treatment.

Because the signal that the PCIE high-speed serial bus is carried is the low-yield signal that changes at a high speed, the signal that transmitter sends can only drive a receiver at most, therefore this bus two ends only allow respectively to connect a transmitter and a receiver, i.e. said point-to-point connection in the PCIE standard.If directly connect the test cable to former transfer bus, then former driver need drive two receivers, then may cause to drive deficiency, causes receiver to receive error in data.Therefore, be difficult to from the PCIE high-speed serial bus, directly take out test signal.The way of general logic analyser is the centre bus sniffer that adopts through particular design, and this device is still unavoidably to exerting an influence on the former transfer bus, and is difficult for using.

It is the characteristic of the direct current equalizing signal of process 8b/10b coding that present embodiment has utilized the PCIE physical signalling, adopt the high-frequency clock driver, utilize it to carry out signal replication, designed a circuit that takes out signal on the high-speed serial bus, realize taking out test signal from the PCIE high-speed serial bus.

Because the data sequence of transmitting on the PCIE bus is the data sequence of handling through scrambler, 8b/10b coding etc., but not binary code sequence, this raw data can't be analyzed.This programme utilizes PCIEPHY that the original test signal of taking out is handled the binary-coded conventional sequence of output.

The output ofbus 103 is inputs of PCIE PHY 105.PCIE PHY 105 carries out the technical finesse of PCIE Physical layers such as descrambling, 8b/10b decoding with the serial data of input, then onbus 107, export 8bit parallel data, supervisory control signals, synchronizing clock signals and bus state indicator signal, condition indicative signal indication bus state, connect situation as bus, the bus transfer error situation, whether the data on the bus are effective, and whether bus inserts extended byte etc.PCIE PHY is output as the 8bit parallel data of decoding, i.e. the conventional coded data of true transmission on the PCIE bus.Therefore direct data of the output signal ofbus 107 by transmitting on the 108 and 113 oscilloscope apparatus direct-on-line Real Time Observation buses of forming.

Storage and display system that FPGA 110,DDR2 sdram memory 106 and UART terminal are formed, the data that preservation and output are taken out from the PCIE bus are used for analyzing.

Data are preserved automatically and by the data transmission situation on the UART terminal analysis PCIE bus in order to realize analyzing, and the output signal ofbus 107 is input to FPGA 110.FPGA 110 stores the 8bit parallel data on thebus 107 in theDDR2 sdram memory 106 into.The data that will be stored in simultaneously in theDDR2 sdram memory 106 send to UART terminal 112 by bus 111.UART terminal 112 shows the data that send and preserves.

The inner structure design of describedFPGA 110 as shown in figure 12.

FPGA 110 is made up of PCIE phyinterface controller 202, DDR2 sdrammemory interface controller 208,UART interface controller 210,global controller 207.

PCIEphy interface controller 202 carries out buffer memory with the parallel data thatbus 107 sends, and sends to DDR2 sdrammemory interface controller 208 then.

DDR2 sdrammemory interface controller 208 writes the DDR2 sdram memory with the data that PCIE phyinterface controller 202 sends by bus 109.The data that while DDR2 sdrammemory interface controller 208 also can be read the DDR2 sdram memory send toglobal controller 207.

UART interface controller 210 can receive the control command thatbus 111 sends over, and control command is transmitted to global controller 207.Also the data thatglobal controller 207 sends over can be sent tobus 111.

The function ofglobal controller 207 comprises:

(1) start address that will preserve the DDR2 sdram memory of PCIE parallel data is written in thePCIEPHY interface controller 202;

(2) according to the data length indicator of PCE phyinterface controller 202 data are read from the DDR2 sdram memory by DDR2SDRAM memory i/f controller 208, and send to UARTinterface controller 210;

(3) receiveUART interface controller 210 and pass the command word of coming, and resolve, send the FPGA internal control signal according to command word.

The internal work process ofFPGA 110 is as follows:

The start address thatglobal controller 207 will be preserved the DDR2 sdram memory of PCIE parallel data is written to 202 PCIE phy interface controllers;

PCIEphy interface controller 202 begins to store parallel data from the total line drawing of PCIE from start address, carrying out automatic memory address adds up, preserve EO address and the total data volume that is written to the DDR2 sdram memory simultaneously, and start address is updated to the EO address.

Whenglobal controller 207 receives the video data order thatUART interface controller 210 sends over, data are read from the DDR2 sdram memory by DDR2 sdrammemory interface controller 208, and send to UARTinterface controller 210, send to demonstration of UART terminal and preservation byUART interface controller 210, use for the system designer analysis.

Whenglobal controller 207 receives the order that clears data thatUART interface controller 210 sends over, then start address and end address in the PCIE phyinterface controller 202 are changed to initial value again.And reset to 0 being written to DDR2 sdram memory data total amount.

Easy in order to design,global controller 207 receives only the demonstration that 210 UART interface controllers send over and removes two kinds of orders, and other orders are not carried out.

Because the technical characterstic of high-speed serial bus such as PCIE bus, make system designer can't only adopt equipment commonly used such as oscillograph that high-speed serial bus is analyzed and tested, and must acquire complexity and the higher logical analysis device of cost, reach the purpose of system debug test by logical analysis device, use logic analyser need dispose some not wield sniffers, cause the test difficulty toward contact.Simultaneously,, unavoidably the signal on the former bus is exerted an influence,, cause test inaccurate if connect the improper distorted signals that might make on the former bus because the centre bus sniffer is to take out portion of energy from bus.

The invention provides a kind of easy use high-speed serial bus analytics and device cheaply, handle by the signal on the high-speed serial bus being carried out shunt, the shunting sign that obtains is leaded up to resolve and is used for logic analysis, one the tunnel returns high-speed serial bus, under the situation that does not influence the high-speed serial bus data transmission, promptly can analyze the transmission data on the high-speed serial bus, and simplicity of design, cost is lower, the parallel data that the present invention also obtains parsing stores in the internal memory, and parallel data is sent to the universal asynchronous receiving-transmitting terminal preserve and show, be convenient to carry out logic analysis.Apparatus of the present invention only need to cooperate the purpose that can reach online high-speed serial bus logic analysis with common equipment such as oscillograph or PC terminal etc., have made things convenient for the debugging test of high-speed serial bus system.

Parts that exemplify in apparatus of the present invention such as high-frequency clock driver, PCIE PHY, DDR2 sdram memory etc. are not as limitation of the present invention; the similar realization all can be substituted in the device of the present invention with the device of above-mentioned parts identical function, all belongs to protection scope of the present invention.

It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.

Claims (12)

1. a high-speed serial bus analytics is characterized in that, described method comprises:

Receive the bus signals of high-speed serial bus, described bus signals is copied as first signal and secondary signal, first signal is returned described high-speed serial bus, and secondary signal resolved obtain parallel data by the signal shunt module.

2. arbitrary high-speed serial bus analytics according to claim 1 is characterized in that described signal shunt module is specially the high-frequency clock driver.

3. high-speed serial bus analytics according to claim 1 and 2 is characterized in that, described to secondary signal resolve obtain parallel data after, also comprise: store described parallel data.

4. high-speed serial bus analytics according to claim 3 is characterized in that, after the described parallel data of described storage, also comprises: described parallel data is sent to the universal asynchronous receiving-transmitting terminal preserves or show.

5. arbitrary high-speed serial bus analytics according to claim 1 and 2 is characterized in that, to secondary signal resolve obtain parallel data after, also comprise: described parallel data is outputed to oscillograph.

6. arbitrary high-speed serial bus analytics according to claim 1 and 2 is characterized in that, described secondary signal is resolved obtains parallel data and be specially: secondary signal is carried out descrambling and decoding obtains parallel data.

7. a high-speed serial bus logic analysis unit is characterized in that, comprising: signal shunt module and signal resolution module;

Described signal shunt module is used for described bus signals is copied as first signal and secondary signal, and first signal is returned described high-speed serial bus, and secondary signal is sent to signal resolution module;

Described signal resolution module is connected with the signal shunt module, is used for secondary signal resolved obtaining parallel data.

8. high-speed serial bus logic analysis unit according to claim 7 is characterized in that, also comprises memory module, is connected with signal resolution module, is used to receive described parallel data, and stores described parallel data.

9. high-speed serial bus logic analysis unit according to claim 8 is characterized in that described memory module comprises field programmable gate array unit and internal storage location;

Described field programmable gate array unit is used to receive described parallel data, carries out buffer memory, and sends to internal storage location;

Described internal storage location is connected with the field programmable gate array unit, is used to store described parallel data.

10. high-speed serial bus logic analysis unit according to claim 9 is characterized in that, also comprises the universal asynchronous receiving-transmitting terminal, is used to receive the described parallel data that described field programmable gate array unit sends, and preserves or show.

11., it is characterized in that according to the described arbitrary high-speed serial bus logic analysis unit of claim 7-10, also comprise oscillograph, be used for the described parallel data that the received signal parsing module sends, and show.

12. high-speed serial bus logic analysis unit according to claim 10, it is characterized in that described field programmable gate array unit comprises: resolve interface controller, memory i/f controller, global controller and universal asynchronous receiving-transmitting terminal interface controller;

Described parsing interface controller is used for parallel data that the received signal parsing module the sends row cache of going forward side by side, and sends to memory i/f controller then;

Described memory i/f controller is connected with the parsing interface controller, is used for storing parallel data into internal storage location, and reads the parallel data of internal storage location storage and send to global controller;

Described global controller is connected with the parsing interface controller with memory i/f controller, is used for parallel data is read from internal storage location by memory i/f controller, and sends to the universal asynchronous receiving-transmitting terminal interface controller;

Described universal asynchronous receiving-transmitting terminal interface controller is connected with global controller, is used for that the parallel data that global controller sends is sent to the asynchronous communication terminal and stores and show.

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