CN101494579A

Movatterモバイル変換

Info

Publication number: CN101494579A
Application number: CNA2008100043961A
Authority: CN
Inventors: 吕闻; 吴枫
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2008-01-22
Filing date: 2008-01-22
Publication date: 2009-07-29
Anticipated expiration: 2028-01-22
Also published as: CN101494579B

Abstract

The invention provides a bus dispatching device and a method. The bus dispatching device comprises a receiving unit and a transmitting unit, wherein, the receiving unit continuously receives data packets of scheduled amount after transmitting a writing request to an interface at an opposite end, or the transmitting unit transmits the processed data packets accumulated to the scheduled amount to the interface at the opposite end by one-time operation after transmitting a reading request to the opposite end. The invention receives and/or transmits the data packets in batches, which can prevent packet-loss phenomenon in the intermediate process, and avoid the frequent transmitting of reading and writing requests and the waiting for response, thus guaranteeing the reliability of data transmission and improving the transmission efficiency.

Description

Bus scheduling device and method

Technical field

The present invention relates to mobile communcations system, especially device interconnection and bus scheduling device and the method used in the mobile communcations system.

Background technology

The IEEE802.16 technology is a wireless access wide band technology, provides professional by inserting core net to the user, and core net adopts the network based on the IP agreement usually.The physical layer of IEEE802.16e can be selected single carrier, OFDM (OFDM) and OFDM (OFDMA) totally 3 kinds of technology for use.The single carrier option mainly is for the line-of-sight transmission of compatible 10GHz to the 66GHz frequency range.IEEE 802.16e to the OFDMA physical layer can support 128,512,1024 with 2048 totally 4 kinds of different number of subcarriers, but subcarrier spacing is constant, signal bandwidth is directly proportional with number of subcarriers.This technology is called extendible OFDMA (Scalable OFDMA).Adopt this technology, system can be in mobile environment the variation of flexible adaptation channel width.IEEE 802.16 technology can obtain different access rates under different wireless parameter combinations.With the 10MHz carrier bandwidths is example, if adopt 64QAM (quadrature amplitude modulation) modulation system, the single carrier bandwidth can provide effective access rate of about 30Mbit/second.The carrier bandwidths scope that IEEE 802.16 standards are suitable for does not wait from 1.75MHz to 20MHz, and under the situation of 20MHz channel width, 64QAM modulation, transmission rate can reach 74.81Mbit/second.

Multiple-input and multiple-output (MIMO) technology is that future mobile communication system is realized high data rate, improves the important channel of transmission reliability, and the method that solves following wireless access wide band technology volume of business demand bottleneck problem is provided.The MIMO technology adopts a plurality of antennas respectively at transmitting terminal and receiving terminal exactly, thereby improves the service quality (bit error rate or data rate) that each user obtains, and utilizes the MIMO technology can reach higher channel width, improves the service performance of network.

IEEE 802.16e standard reasonable development space resources on the basis of OFDM OFDMA in conjunction with constituting MIMO OFDMA system, can provide higher data transmission bauds with the technology of MIMO and OFDM OFDMA.Simultaneously, because the technology of OFDM OFDMA has added guardtime at interval, has very strong anti-multipath interference performance.When multidiameter delay is protected at interval less than it; can make system not be subjected to the puzzlement of intersymbol interference; this just allows Single Frequency Network can be used for the wideband orthogonal fdma system, and the emission array that relies on a large amount of low power transmissions antennas to form is eliminated shadow effect, realizes covering fully.

Because the baseband system of 802.16e need be supported the MIMO technology, so must satisfy the channel width demand of 20MHz, this just means needs the transmission speed that reaches higher on the data link of base band.In baseband system, because the input and output of coprocessor all are to dispatch with the form of packet, packet input/output scheduling to coprocessor is a key technology place of improving transmission speed on the whole data link, prior art realizes data packet dispatching by the parallel bidirectional bus structures, comprise receiving terminal and transmitting terminal, data can be carried out transmitted in both directions simultaneously.Receiving terminal is handled and is sent to end interface by transmitting terminal by the internal data processing module after receiving packet, and in this process, the intact packet of inter-process resume module is promptly to end interface is sent a packet.The packet loss phenomenon may appear because link is unstable in this mechanism, can not guarantee safety of data transmission, and, cause the data transmission efficiency of total system low because need need often response reading and writing request to end interface constantly to end interface is sent the reading and writing request.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of bus scheduling device and method, to guarantee reliability of data transmission and to improve efficiency of transmission.

For solving the problems of the technologies described above, the invention provides a kind of bus scheduling device, this device comprises receiving element and transmitting element, receiving element is after sending write request to end interface, receive the scheduled traffic data bag continuously, or transmitting element is after the opposite end sends read request, and packet is disposable after the processing of scheduled volume sends to end interface with being accumulated to.

Further, receiving element comprises the reception control module and receives formation, wherein receives control module in order to the packet of control reception to the end interface transmission, it is deposited into receive in the formation, sends to inner Co-processor Module then; Receive the packet that formation receives in order to buffer memory, wait for that receiving control module sense data bag gives inner Co-processor Module;

Transmitting element comprises transmission control module and transmit queue, wherein sending control module send in the formation in order to control to set out through the scheduled traffic data bag storage after the Co-processor Module processing, once send to then end interface, and send handle the back packet after to the transmit queue initialization; Transmit queue, in order to the packet after the processing of buffer memory Co-processor Module, its space is enough to storing predetermined amount packet, waits disposable all the scheduled traffic data bags of reading of control module to be sent to give end interface.

Further, receiving formation and transmit queue all is the read-write isochronous queue, and in order to the packet that receives is lined up according to the mode of first-in first-out, wherein receiving formation in a single day has data to write, and promptly begins read operation.

Further, receiving element also comprises handles preceding packet counter, be used for counting to depositing the packet that receives formation in, transmitting element also comprises handles back packet counter, be used for the packet that deposits transmit queue in is counted, send control module and judge when the currency of this two counter equates, be used for sending all data that read request and disposable transmission are stored in transmit queue.

Further, adopt high speed parallel bus to connect between the bus scheduling device, receiving element and transmitting element adopt and interrupt communication mechanism control reception and send data, receiving element interrupts to end interface is sent write request, receive and send packet, up to sending the packet that carries frame end to inner Co-processor Module; Transmitting element receives the packet after the processing, when the preceding data packet number of data packet number after the judgment processing and processing is identical, interrupts the packet after all processing of disposable transmission to end interface is sent read request.

For solving the problems of the technologies described above, the present invention also provides a kind of bus scheduling method, this end interface receives the scheduled traffic data bag or continuously after end interface being sent read request after end interface being sent write request, will be accumulated to after the processing of scheduled volume disposable sending to end interface behind the packet.

This method may further comprise the steps:

(a) this end interface receives the packet that end interface is sent to end interface is sent write request, and sends the coprocessor to device inside;

(b) packet after this end interface is handled inner coprocessor writes buffer memory, runs up to the scheduled traffic data bag to end interface is sent read request, and sends to end interface the scheduled traffic data bag is disposable.

Further, different components adopts high speed parallel bus to connect, and step (a) further comprises:

(a1) this end interface interrupts to end interface is sent write request;

(a2) after this end interface is received end interface replied, begin to receive and data cached bag, the sense data bag is given inner Co-processor Module simultaneously;

(a3) when this end interface buffer memory was sky, repeating step (a1) was to (a2), up to receiving the scheduled traffic data bag;

Step (b) further comprises:

(b1) data pack buffer after this end interface will be handled is up to receiving all packets;

(b2) this end interface interrupts to end interface being sent read request, receive end interface replied after, with disposable the sending to of all packets of buffer memory to end interface.

Further, the cached data packet counting is received in the butt joint of this end interface in the step (a2); This end interface, is thought to receive all packets when the data packet number before handling the back cached data packet and handling equates to handling back cached data packet counting in the step (b2).

Compared to prior art, bus scheduling device that the present invention introduces between different devices and method, realized the batch of packet is received, sends in batches, prevent that pilot process from producing the packet loss phenomenon, avoid frequently sending the reading and writing request and awaiting a response, to guarantee reliability of data transmission and to improve efficiency of transmission.

Description of drawings

Fig. 1 is the structural representation of embodiment of the invention high speed parallel bus scheduling implement device.

Fig. 2 is the state flow chart of the reception control module of apparatus of the present invention.

Fig. 3 is the state flow chart of the transmission control module of apparatus of the present invention.

Fig. 4 is the schematic diagram of bus scheduling method of the present invention.

Embodiment

The thought of bus scheduling device of the present invention and method is to end interface being sent write request or read request, and after obtaining end interface replied, need not to send once more read request or write request, receive continuously and packet is disposable after inner Co-processor Module sends the processing that the scheduled traffic data bag maybe will be accumulated to scheduled volume sends to end interface.The advantage of this mechanism is to realize that the batch to packet receives, sends in batches, can prevent that pilot process from producing the packet loss phenomenon, avoids frequently sending the reading and writing request, improves efficiency of transmission.

The scheduled traffic data bag can be that a frame data bag also can be one group of packet or several packet of dividing according to data characteristic, and the packet number that concrete batch sends can be grasped flexibly according to concrete applicable cases.

In the practical application, adopting to receive in batches still to send in batches also needs according to end interface is decided, same bus interface (being bus scheduling device) can adopt simultaneously and receive in batches and send in batches, also can only adopt and receive in batches or send in batches, no matter which kind of situation can both embody advantage of the present invention.

Bus scheduling device of the present invention is a bus interface, comprise receiving element and transmitting element, accept that the unit is realized receiving in batches and or transmitting element realize sending in batches, be receiving element after end interface being sent write request, receive the scheduled traffic data bag continuously, and/or transmitting element is after the opposite end sends read request, and packet is disposable after the processing of scheduled volume sends to end interface with being accumulated to.

Below mainly describe to embody to send in batches.

Bus scheduling device of the present invention comprises receiving element and transmitting element, wherein,

Receiving element sends to the Co-processor Module of device inside in order to receive the packet that end interface is sent behind the buffer memory;

Packet after transmitting element is handled through Co-processor Module in order to buffer memory is accumulated to disposable sending to end interface behind the scheduled traffic data bag.

Based on inventive concept, can adopt the serial or parallel bidirectional bus to connect each device and realize the present invention, but the packet of considering the inventive method is imported and packet output can be carried out at times, in order to improve resource utilization, the embodiment of the invention adopts high speed parallel bus, and introduce to interrupt communication mechanism, below be that example describes in detail to apparatus of the present invention with the high speed parallel bus.

As shown in Figure 1, each device of mobile communication system links to each other by the high-speed parallel data/address bus, bus scheduling device of the present invention, utilize and interrupt the scheduling that communication mechanism is realized processing data packets, the receiving element of this dispatching device comprises the reception control module and receives formation, transmitting element comprises transmission control module and transmit queue, in addition, packet counter before receiving element is provided with and handles, transmitting element is provided with handles back packet counter, receive the number-of-packet that packet that formation receives and transmit queue receive by checking and equate, guarantee that the packet that need once send in batches all sends to end interface in batches.

Wherein:

Receive control module, receive the packet that end interface is sent, it is deposited in the reception formation, send to inner Co-processor Module then in order to control; And after sending the scheduled traffic data bag to packet counter O reset before handling;

Receive control module and send the write request interruption according to the state that receives formation, if receive formation is empty, (specifically refer to, when the reception control module is received the init state signal that receives formation) then, end interface interrupts to being sent write request, if end interface made read request replied, then send write signal to receiving formation.

Receiving formation, is a read-write isochronous queue, in order to the packet that will receive, lines up according to the mode of first-in first-out, waits for that receiving control module gives subordinate's processing module according to calling over packet;

Be the raising input efficiency, the embodiment of the invention receives formation and adopts read-write synchronously, after data write the reception formation, promptly begins read operation, because the time difference of write operation and read operation is very little, can be similar to and thinks that this reception formation is that read-write is synchronous.After finishing the writing and read an of packet, receiving formation be sky, at this moment, receiving control module interrupts to end interface being sent write request once more, receive end interface replied after, beginning writes next packet to receiving formation, up to receiving the packet that has frame end mark.

The packet counter is used for counting depositing the packet that receives formation in before handling;

Send control module, send in the formation in order to control to set out through the packet storage after the Co-processor Module processing, when packet counter content after the judgment processing equates with packet counter before the processing, the transmission read request is interrupted, receive end interface replied after, send read signal to transmit queue, once send to then, and after sending processing back packet, the transmit queue initialization is reached handling back packet counter O reset end interface;

Transmit queue, it is a read-write isochronous queue, line up according to the mode of first-in first-out in order to the data after inner Co-processor Module is handled, once send to end interface by interrupting communication mechanism etc. control module to be sent, the space of transmit queue is enough to the data that storing predetermined batch sends, as storing frame data.

Handling back packet counter is used for the packet that deposits transmit queue in is counted.

In concrete application example, inner Co-processor Module is that unit handles data with the packet, receiving element in the parallel bus dispatching device of the present invention whenever sends a write request and interrupts, receive a packet, after packet accumulation after transmit queue is handled inner coprocessor is cached to frame data, send control module and send read request and interrupt, issue end interface frame data are disposable.

If a last mode that also adopts batch to send to end interface sends packet, then receiving control module interrupts to end interface being sent a write request, all scheduled traffic data bags (as a frame) can be write the reception formation, constantly send to simultaneously inner Co-processor Module, send to next in batches by sending control module control transmit queue again end interface.

Fig. 2 is the state flow chart of reception control module of the present invention, and it is specific as follows that it receives state of a control:

After state 1, the system reset, receive control module and enter into the IDLE state;

State 2, after the initializing signal that receives formation arrives, interrupt to end interface is sent write request, receive control module and enter into the write request interrupt INT _ SEND state that sends,

State 3, end interface received in the write request have no progeny that the high-speed bus dispatching device in this device sends packet, receive control module and enter the formation WRITE_PRE_FIFO state that receives of writing;

State 4, receiving control module lines up according to the mode of first-in first-out the packet that receives in receiving formation, after the data of certain byte are received in the reception formation, the reception control module enters into reads to receive formation READ_PRE_FIFO state, and give inner Co-processor Module and the packet that receives is counted according to the packet that calls over of first-in first-out, read sky if receive formation, the reception control module circulates again and gets the hang of 1 to state 4, until sending the packet that has frame end mark, receive control module and no longer send the write request interruption, reenter the IDLE state.

Fig. 3 is the state flow chart of transmission control module of the present invention, and it is specific as follows that it sends state of a control:

State 1: behind the system initialization, send control module and enter into idle IDLE_P state, wait for that inner Co-processor Module sends to handle packet;

State 2: after the Co-processor Module in the device is handled the packet of reception, the packet after handling is mail to the high-speed bus dispatching device, send control module and enter into the transmit queue WRITE_POST_FIFO state of writing;

The packet storage is seted out and is sent formation after the processing of state 3, high-speed bus dispatching device Co-processor Module reception internally, and packet after the processing that receives is counted; If the number-of-packet that number-of-packet and reception control module are received after the processing that receives equates, then send control module and interrupt to end interface is sent read request, enter into the read request interruption READ_FRAME_INT state that sends;

State 4: reply if end interface made read request, then send control module and enter into the transmit queue READ_POST_FIFO state of reading;

The mode of packet in the transmit queue according to first-in first-out sent to end interface, all data in sending transmit queue, packet sends control module and reenters the IDLE_P state.

Bus scheduling method of the present invention, to end interface being sent write request or read request, and after obtaining end interface replied, receive continuously and packet is disposable after inner Co-processor Module sends the processing that the scheduled traffic data bag maybe will be accumulated to scheduled volume sends to end interface.As shown in Figure 4, this method may further comprise the steps:

Step 401: this end interface receives the packet that end interface is sent to end interface is sent write request, and sends the coprocessor to device inside;

Step 402: the packet after this end interface is handled inner coprocessor, write buffer memory, run up to the scheduled traffic data bag to end interface is sent read request, and send to end interface the scheduled traffic data bag is disposable.

Particularly, adopt the bus scheduling method of bus scheduling device shown in Figure 2 may further comprise the steps:

Step 1, bus scheduling device interrupt to end interface is sent write request;

Step 2, end interface received in the write request has no progeny that the dispatching device in this device sends packet;

Step 3, reception control module are lined up according to the mode of first-in first-out the packet that receives in receiving formation;

Step 4, after receiving the data of certain byte, the reception control module counts to inner Co-processor Module and to the packet that receives according to the packet that calls over of first-in first-out, if receive formation is empty, repeating step 1-4, until sending the packet that has frame end mark, enter step 5;

After step 5, Co-processor Module are handled the packet of reception, the packet after handling is mail to the high-speed bus dispatching device;

The packet storage is seted out and is sent formation after the processing that step 6, bus scheduling device will receive from Co-processor Module, and packet after the processing that receives is counted;

If the number-of-packet that number-of-packet and reception control module receive after the processing that step 7 receives equates, then, end interface interrupts to being sent read request;

If step 8 has been made read request end interface and having been replied, then the dispatching device in this device sends to the mode of the data in the transmit queue according to first-in first-out to end interface all data in sending transmit queue.

Step 9, bus scheduling device the processing of a frame after packet send to after the end interface, to receiving formation and transmit queue initialization, and, wait for the packet that receives next frame to counter O reset.The whole input of packet is insensitive to the packet sequence of input, and the packet of output is sent to end interface successively according to the order in transmit queue, carry out order rearrangement by the inter-process module of opposite end according to the packet sequence number in the packet header.

In actual applications, mechanism to end interface is different with the identical also possibility of bus scheduling device possibility of the present invention, but can adopt inventive concept, carries out the batch transmission to sending to corresponding data to end interface, thereby prevent loss packet, guarantee safety of data transmission.

Apparatus of the present invention and method can be applied in the various high-speed mobile communication systems, wherein receiving element sends a write request, receive the scheduled traffic data bag continuously, packet after the transmitting element judgment processing with handle before data packet number when equating to end interface is sent read request, and put end mark on the packet of transmission in the end.

Compared with prior art, the present invention introduces a kind of bus scheduling device between different devices, Realization prevents that to batch reception, the Batch sending of packet pilot process from producing the packet loss phenomenon, avoids Frequent send the reading and writing request and await a response, improved efficiency of transmission. Total with existing parallel bidirectional The scheduling mechanism of line compares, although real-time is good not as the parallel bidirectional bus, because this at a high speed also Row bus is applied to the scheduling to coprocessor, and requirement of real-time is not high, so can make list fully Process to data packet dispatching, improved flexibility and the Yi Hangxing of whole system.

Claims

1, a kind of bus scheduling device, this device comprises receiving element and transmitting element, it is characterized in that: receiving element is after sending write request to end interface, receive the scheduled traffic data bag continuously, or transmitting element is after the opposite end sends read request, and packet is disposable after the processing of scheduled volume sends to end interface with being accumulated to.

2, device as claimed in claim 1, it is characterized in that: receiving element comprises the reception control module and receives formation, wherein receive control module and receive the packet that end interface is sent, it is deposited in the reception formation, send to inner Co-processor Module then in order to control; Receive the packet that formation receives in order to buffer memory, wait for that receiving control module sense data bag gives inner Co-processor Module;

3, device as claimed in claim 2 is characterized in that: receiving formation and transmit queue all is the read-write isochronous queue, and in order to the packet that receives is lined up according to the mode of first-in first-out, wherein receiving formation in a single day has data to write, and promptly begins read operation.

4, device as claimed in claim 2, it is characterized in that: receiving element also comprises handles preceding packet counter, be used for counting to depositing the packet that receives formation in, transmitting element also comprises handles back packet counter, be used for the packet that deposits transmit queue in is counted, send control module and judge when the currency of this two counter equates, be used for sending all data that read request and disposable transmission are stored in transmit queue.

5, as each described device in the claim 2 to 4, it is characterized in that: adopt high speed parallel bus to connect between the bus scheduling device, receiving element and transmitting element adopt and interrupt communication mechanism control reception and send data, receiving element interrupts to end interface is sent write request, receive and send packet, up to sending the packet that carries frame end to inner Co-processor Module; Transmitting element receives the packet after the processing, when the preceding data packet number of data packet number after the judgment processing and processing is identical, interrupts the packet after all processing of disposable transmission to end interface is sent read request.

6, a kind of bus scheduling method, it is characterized in that: this end interface receives scheduled traffic data bag or this end interface continuously after end interface being sent read request after end interface being sent write request, will be accumulated to after the processing of scheduled volume disposable sending to end interface behind the packet.

7, method as claimed in claim 6 is characterized in that, this method may further comprise the steps:

8, method as claimed in claim 7 is characterized in that, different components adopts high speed parallel bus to connect, and step (a) further comprises:

(a1) this end interface interrupts to end interface is sent write request;

Step (b) further comprises:

9, method as claimed in claim 8 is characterized in that: the cached data packet counting is received in the butt joint of this end interface in the step (a2); This end interface, is thought to receive all packets when the data packet number before handling the back cached data packet and handling equates to handling back cached data packet counting in the step (b2).