CN101447457A

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Info

Publication number: CN101447457A
Application number: CNA200710171663XA
Authority: CN
Inventors: 张海洋
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2007-11-27
Filing date: 2007-11-27
Publication date: 2009-06-03
Anticipated expiration: 2027-11-27
Also published as: CN101447457B

Abstract

The invention discloses a method for manufacturing a double-stress membrane CMOS, comprising: a semiconductor substrate which comprises a first transistor and a second transistor is provided; a doped first stress membrane is formed on the first transistor; a second stress membrane is formed on the first stress membrane and the second transistor, wherein, the thickness of the second stress membrane is at least equal to the sum of the thicknesses of a grid medium layer, a grid and the first stress membrane of the first transistor; the second stress membrane is flattened, so that the surface of the first stress membrane is exposed out; photoresist patterns are formed on the exposed surface of the first stress membrane and the second stress membrane above a grid of the second transistor, wherein, the line width of the photoresist patterns above the grid of the second transistor and on the second stress membrane is larger than the line width of the grid of the second transistor; the second stress membrane which is not covered by the photoresist patterns is etched until the second stress membrane on the first stress membrane is removed. No bossed defects can be produced at the joint of a tension stress membrane and a compressive stress membrane layer.

Description

The manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor

Technical field

The present invention relates to technical field of manufacturing semiconductors, the manufacture method of particularly a kind of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor (CMOS).

Background technology

Along with the continuous development of semiconductor fabrication, the size of metal oxide semiconductor transistor also reduces day by day, but physical properties such as its unfailing performance and the speed of response have been had higher requirement.

The key factor that influences the speed of response in the metal oxide semiconductor transistor is a carrier mobility, under same driving voltage, transistor with big carrier mobility has the speed of response faster, and people always improve the carrier mobility of metal oxide semiconductor transistor to obtain the higher speed of response by the whole bag of tricks.At present, industry develops " strained silicon technology " and improves mobility of charge carrier rate in the conducting channel.

Publication number is that the Chinese patent application file of CN 1819121A discloses a kind of method of making strain silicon transistor, in its disclosed method, by deposited silicon nitride rete on MOS transistor, then described silicon nitride film layer is carried out UV-irradiation technology, make this silicon nitride film layer become the stress film of high tensile stress, to improve mobility of charge carrier rate in the metal oxide silicium semiconductor transistor.

Stress in the stress film is divided into two kinds: tensile stress and compression.The tensile stress stress film can improve the mobility of electronics in the N type metal oxide semiconductor transistor (NMOS); The compression stress film can improve the mobility in hole in the P-type mos transistor (PMOS).For the CMOS transistor, be to improve the speed of response, need on NMOS and PMOS, form the stress rete of different stress respectively.

Existing a kind of manufacturing process that forms double-stress membrane complementary metal oxide semiconductor (CMOS) transistor such as Fig. 1 are to shown in Figure 6.

As shown in Figure 1, provideSemiconductor substrate 100 withnmos pass transistor 102 andPMOS transistor 104.

As shown in Figure 2, on describednmos pass transistor 102 andPMOS transistor 104, formtensile stress rete 106.

As shown in Figure 3, remove tensile stress rete on the describedPMOS transistor 104, keep thetensile stress rete 106a on the described nmos pass transistor by chemical wet etching.

As shown in Figure 4, on describedtensile stress rete 106a andPMOS transistor 104,form compression rete 108.

As shown in Figure 5, above described PMOS transistor, form photoresist layer 107, and etching is removed the pressure rete on the describedtensile stress rete 106a, the formationcompressive stress film 108a on described PMOS transistor by photoetching;

Then, as shown in Figure 6, remove described photoresist layer 107.

Yet, because whendeposition compression rete 108, can form as shown in Figure 4projection 109 withtensile stress rete 106a junction, thereby cause after formation pressure is answeredrete 108a, has as shown in Figure 6projection 109 at the joint ofcompression rete 108a andtensile stress rete 106a, thisprojection 109 can the follow-up technology of influence, and cause the stability of the CMOS (Complementary Metal Oxide Semiconductor) transistor that forms to descend.

Summary of the invention

The invention provides a kind of manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor, method of the present invention can not produce the defective of projection at the joint of tensile stress film and compression rete.

The manufacture method of a kind of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor provided by the invention comprises:

Semiconductor substrate with the first transistor and transistor seconds is provided, and wherein the first transistor is nmos pass transistor or PMOS transistor; Transistor seconds corresponds to PMOS transistor or nmos pass transistor;

On the first transistor, be formed for improving first stress film of the first transistor carrier mobility;

Be formed for improving second stress film of transistor seconds carrier mobility on first stress film and transistor seconds, the thickness of described second stress film equals the thickness sum of gate dielectric layer, grid and first stress film of described the first transistor at least;

Described second stress film of planarization is exposed the surface of first stress film on the described the first transistor grid;

Forming the photoresist pattern on the surface that described first stress film is exposed and on second stress film above the transistor seconds grid, wherein, the live width of the photoresist pattern on second stress film above the described transistor seconds grid is greater than the live width of the grid of this transistor seconds;

Etching is not by second stress film of described photoresist pattern covers, until second stress film of removing on described first stress film;

Wherein, if described the first transistor is a nmos pass transistor, then first stress film is the doping stress film; If transistor seconds is a nmos pass transistor, then second stress film is the doping stress film.

Optionally, it is as follows to form the step of first stress film:

On described the first transistor and transistor seconds, form first stress film by depositing operation;

On first stress film on the described the first transistor, form the photoresist pattern;

Etching is removed not by first stress film of described photoresist pattern covers;

Remove described photoresist pattern;

Wherein, if described the first transistor is a nmos pass transistor, the technology that then forms first stress film is deposition and in-situ doped technology.

Optionally, the described in-situ doped impurity that mixes is germanium or carbon.

Optionally, further comprise: the execution UV-irradiation technology or the thermal anneal process of described first stress film.

Optionally, described first stress film is a silicon nitride.

Optionally, if transistor seconds is a nmos pass transistor, the technology that then forms second stress film is deposition and in-situ doped technology.

Optionally, the technology of described second stress film of planarization is cmp, and wherein, first stress film of the grid of described the first transistor top stops layer for grinding.

Optionally, the step of described second stress film of planarization is as follows:

Described second stress film is carried out chemical mechanical milling tech;

After finishing described cmp, described second stress film of etching is until second stress film of removing described the first transistor grid top.

Optionally, described second stress film is a silicon nitride.

Optionally, described etching is a dry etching.

Optionally, detect the etching terminal of described dry etching with first stress film as etching stop layer or control the etching terminal of described dry etching with etch period.

Optionally, further comprise: remove described photoresist pattern.

Compared with prior art, one of them technical scheme of the present invention has following advantage:

By after forming first stress film on the first transistor, then form second stress film of thickness greater than first stress film and transistor seconds grid, and described second stress film carried out planarization, then this second stress film is carried out selective etch, make that remaining second stress film and first stress film have junction preferably on transistor seconds, can not produce the defective of projection, thereby can not exert an influence to follow-up technology (for example interconnection process), and can increase the process window of subsequent technique, improve the stability of manufacturing process; In addition, also can improve the stability of the device of formation.

Description of drawings

Fig. 1 to Fig. 6 is each step corresponding structure generalized section of the manufacturing process of existing a kind of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor;

Fig. 7 is the flow chart of first embodiment of the manufacturing process of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor of the present invention;

Fig. 8 is for having the cross-sectional view of NMOS and the transistorized Semiconductor substrate of PMOS in the first embodiment of the present invention;

Fig. 9 is the cross-sectional view that forms first stress film on NMOS shown in Figure 8 and PMOS transistor;

Figure 10 is the cross-sectional view that forms the photoresist pattern on first stress film above the nmos pass transistor shown in Figure 9;

Figure 11 is the cross-sectional view that forms first stress film above nmos pass transistor;

Figure 12 is the schematic diagram that forms second stress film on first stress film shown in Figure 11 and PMOS transistor;

Figure 13 is to the cross-sectional view after the second stress film planarization shown in Figure 12;

Figure 14 is the generalized section that forms the photoresist pattern on as shown in figure 13 first stress film and second stress film;

Figure 15 is for carrying out the cross-sectional view after the etching to second stress film shown in Figure 14;

Figure 16 is the flow chart of second embodiment of the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor of the present invention.

Embodiment

Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.

On MOS transistor, cover stress film and can improve mobility of charge carrier rate in the conducting channel, thereby can improve the speed of response of MOS device.Nmos pass transistor in CMOS covers the tensile stress film, covers compressive stress film on the PMOS transistor, can improve the electronics in NMOS and the PMOS transistor and the carrier mobility in hole respectively.

In the embodiments of the invention, provide a kind of manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor;

At first on the first transistor, be formed for improving first stress film of the first transistor carrier mobility, be formed for improving second stress film of transistor seconds carrier mobility then on this first stress film and transistor seconds, the thickness of described second stress film equals the thickness sum of the first transistor gate dielectric layer, grid and first stress film at least;

Then, described second stress film of planarization is exposed the first stress film surface on the described the first transistor grid, so that first stress film on described second stress film and the first transistor grid is roughly in a plane;

With photoresist pattern protect that the first stress film surface exposed with the transistor seconds grid on second stress film (wherein, the live width of the photoresist pattern on second stress film on the grid of wherein said transistor seconds is greater than the live width of the grid of described transistor seconds);

Etching is not by second stress film of described photoresist pattern covers, till second stress film on described first stress film is removed;

Remove described photoresist pattern, thereby on transistor seconds, keep second stress film;

The method of present embodiment can make the joint surface of remaining second stress film on first stress film on the described the first transistor and the transistor seconds comparatively smooth, does not have the defective of projection.

Fig. 7 is the flow chart of first embodiment of the manufacturing process of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor of the present invention.

State among first embodiment at this, described the first transistor is a nmos pass transistor, and transistor seconds is the PMOS transistor.

As shown in Figure 7, step S100 provides to have nmos pass transistor and the transistorized Semiconductor substrate of PMOS.

Fig. 8 is for having the cross-sectional view of NMOS and the transistorized Semiconductor substrate of PMOS in the first embodiment of the present invention.

As shown in Figure 8, provideSemiconductor substrate 10, describedSemiconductor substrate 10 can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon, and describedSemiconductor substrate 10 also can be a silicon Germanium compound, can also have epitaxial layer structure on insulating barrier silicon-on or the silicon.

Haveisolation structure 12 in describedSemiconductor substrate 10, describedisolation structure 12 can be that shallow trench isolation is from (Shallow Trench Isolation STI), also can be selective oxidation (LocalOxidation of Silicon, a LOCOS) isolation structure.It between the describedisolation structure 12 active area (Active Area).

Havenmos pass transistor 13 andPMOS transistor 23 in described active area zone.Wherein, describednmos pass transistor 13 hassource electrode 14a anddrain electrode 14b,gate dielectric layer 16,grid 18 and gatelateral wall layer 20.

Describedsource electrode 14a anddrain electrode 14b are arranged in describedSemiconductor substrate 10, form by doping process.

Describedgate dielectric layer 16 is on theSemiconductor substrate 10 between describedsource electrode 14a and thedrain electrode 14b, and thisgate dielectric layer 16 can silica or silicon oxynitride or other dielectric material.

Describedgrid 18 is positioned on the described gatedielectric layer 16, andgrid 18 can be the stacked structure of polysilicon or polysilicon and metal silicide.

Described gatelateral wall layer 20 is positioned atgrid 18 sidewalls, and it can be the stepped construction of silica, silicon nitride or silica and silicon nitride, perhaps silica-silicon-nitride and silicon oxide (ONO) structure.

DescribedPMOS transistor 23 hassource electrode 25a anddrain electrode 25b,gate dielectric layer 22,grid 24 and gatelateral wall layer 26.

Describedsource electrode 25a anddrain electrode 25b are arranged in describedSemiconductor substrate 10, form by doping process.

Describedgate dielectric layer 22 is on theSemiconductor substrate 10 between describedsource electrode 25a and thedrain electrode 25b, and thisgate dielectric layer 22 can silica or silicon oxynitride or other dielectric material.

Describedgrid 24 is positioned on the described gatedielectric layer 22, andgrid 24 can be the stacked structure of polysilicon or polysilicon and metal silicide.

Described gatelateral wall layer 26 is positioned atgrid 24 sidewalls, and it can be the stepped construction of silica, silicon nitride or silica and silicon nitride, perhaps silica-silicon-nitride and silicon oxide (ONO) structure.

Step S110 forms first stress film that mixes on described nmos pass transistor.

Fig. 9 is the cross-sectional view that forms first stress film on NMOS shown in Figure 8 and PMOS transistor.

As shown in Figure 9, by deposition and in-situ dopedfirst stress film 28 that mixes that on described nmos pass transistor and PMOS transistor, forms.

Among the embodiment therein, describedfirst stress film 28 is the silicon nitride film of the doping of tensile stress, and the impurity that mixes can be germanium or carbon.

The method of the silicon nitride film that form to mix can be chemical vapour deposition (CVD), carries out in-situ dopedly in deposition, mixes impurity germanium or carbon.

Mixing germanium or carbon impurity in silicon nitride film can increase the tensile stress of rete, compares with the silicon nitride film that does not have to mix, and the tensile stress of the silicon nitride film of doping approximately increases by 1.0 to 1.2GPa, even bigger.

In addition, mix impurity in silicon nitride film, can change its etch rate or grinding rate, the grinding that can be used as follow-up grinding stops the etching stop layer of layer or etching.

In other embodiments, can further carry out ultraviolet irradiation technology or thermal anneal process, with the tensile stress of further raising first stress film to first stress film that mixes.

In other embodiments, the stack layer that describedfirst stress film 28 can multilayer stress film (comprising tensile stress and compression), the stress that the back produces that piles up of multilayer stress film shows as tensile stress.

Figure 10 is the cross-sectional view that forms the photoresist pattern on first stress film on the nmos pass transistor shown in Figure 9.

Spin coating photoresist layer on describedfirst stress film 28 forms as shown in figure 10photoresist pattern 30 by exposure imaging, and describedphotoresist pattern 30 is positioned onfirst stress film 28 on thenmos pass transistor 13.

Figure 11 is the cross-sectional view that forms first stress film on nmos pass transistor.

As etching barrier layer,first stress film 28 that etching is covered by describedphotoresist pattern 30 is removed first stress film that is positioned on the describedPMOS transistor 23 with describedphotoresist pattern 30.

Then, remove describedphotoresist pattern 30 by oxygen gas plasma ashing and wet-cleaned after, first stress film that keeps on describednmos pass transistor 13 is 28a, as shown in figure 11.

Thefirst stress film 28a with tensile stress is formed on the describednmos pass transistor 13, can improve mobility of charge carrier rate in the conducting channel of thisnmos pass transistor 13, improves the speed of response of nmos pass transistor.

In other embodiments, the describedfirst stress film 28a also can not exclusively cover described nmos pass transistor, repeats no more here.

Step S120 forms second stress film on described first stress film and PMOS transistor, the thickness of described second stress film equals the thickness sum of gate dielectric layer, grid and first stress film of described nmos pass transistor at least.

Figure 12 is the schematic diagram that forms second stress film on first stress film shown in Figure 11 and PMOS transistor.

As shown in figure 12, on describedfirst stress film 28a andPMOS transistor 23, form second stress film 32.Wherein, the thickness of describedsecond stress film 32 will equal the thickness sum ofgate dielectric layer 16,grid 18 and thefirst stress film 28a of describednmos pass transistor 13 at least.

Among the embodiment therein, describedsecond stress film 32 is a silicon nitride, and the method that forms described silicon nitride film is a plasma enhanced chemical vapor deposition, and the temperature of deposition is 200 to 300 ℃.

The flow of the gas by change forming silicon nitride film and the power of radio frequency source can change the content of hydrogen in the silicon nitride of formation, form the silicon nitride film with compression.The compression silicon nitride film can improve the mobility of charge carrier rate in hole among the PMOS.

Step S130, described second stress film of planarization is exposed the surface of first stress film of described nmos pass transistor grid top.

Figure 13 is to the cross-sectional view after the second stress film planarization shown in Figure 12.

Owing to be surface depositionsecond stress film 32 at uneven degree, cause after depositionsecond stress film 32 surface also uneven, need be undertaken smooth by flatening process, remove partsecond stress film 32, and thefirst stress film 28a surface on thegrid 18 ofnmos pass transistor 13 is exposed.

Among the embodiment therein, by describedsecond stress film 32 of cmp planarization, because thefirst stress film 28a has the grinding rate different withsecond stress film 32, thereby can stop layer as grinding with thefirst stress film 28a, when thefirst stress film 28a surface on thegrid 18 that is ground tonmos pass transistor 13 is exposed, grinding stops, as shown in figure 13.

In a further embodiment, described flatening process is divided into grinding and two steps of etching, wherein grinds to be cmp.Its step is as follows:

At first describedsecond stress film 32 is carried out chemical mechanical milling tech, make describedsecond stress film 32 have comparatively smooth surface;

Then describedsecond stress film 32 is carried out etching technics, because thefirst stress film 28a that mixes has the etch rate different withsecond stress film 32, can be with thefirst stress film 28a as etching stop layer, when the surface of thefirst stress film 28a on thegrid 18 of describednmos pass transistor 13 is exposed, etching stopping.

Step S140, forming the photoresist pattern on the surface that described first stress film is exposed and on second stress film above the PMOS transistor gate, wherein, the live width of the photoresist pattern on second stress film above the described PMOS transistor gate is greater than the live width of the transistorized grid of described PMOS.

Figure 14 is the generalized section that forms the photoresist pattern on as shown in figure 13 first stress film and second stress film.

Spin coating photoresist on the describedfirst stress film 28a andsecond stress film 32, and by exposure imaging

formation photoresist pattern

34a and 34b, as shown in figure 14, wherein, describedphotoresist pattern 34a is positioned on the describedfirst stress film 28a, and covers the describedfirst stress film 28a; Describedphotoresist pattern 34b is positioned on second stress film of the transistorized grid of describedPMOS 24 tops, and the live width of describedphotoresist pattern 34b is greater than the live width of describedgrid 24.

Step S150, etching is not by second stress film of described photoresist pattern covers, until second stress film of removing on described first stress film.

As shown in figure 15, with described

photoresist pattern

34a and 34b as etching barrier layer, etching is not bysecond stress film 32 of described

photoresist pattern

34a and 34b covering,second stress film 32 of etching stopping on the describedfirst stress film 28a is removed, and forms thesecond stress film 32a on describedPMOS transistor 23.

Because thefirst stress film 28a that mixes has the etch rate different withsecond stress film 32, thereby can be used as the etching stop layer of etchingsecond stress film 32.

The method of describedsecond stress film 32 of etching is a dry etching, and etching gas can be fluorine-containing gas.Among the embodiment therein, etching gas is CF₄And CHF₃, and mix inert gas Ar, and wherein, CF₄Flow be 10sccm to 500sccm, CHF₃Flow be 10 to 500sccm, the flow of Ar is 10sccm to 500sccm; The pressure of etching gas is 10mTorr to 200mTorr, and radio frequency source power is 50W to 500W.

In other embodiments, also can control the terminal point of etching with etch period.

After finishing etching, remove described

photoresist pattern

34a and 34b, promptly be formed with the CMOS (Complementary Metal Oxide Semiconductor) transistor of dual stressed films.

If the describedfirst stress film 28a does not cover describednmos pass transistor 13 fully, the interface of the then describedfirst stress film 28a and thesecond stress film 32a can be positioned at the zones beyond describedisolation structure 12 zones, and shown in Figure 15 is the situation that the interface of thefirst stress film 28a and thesecond stress film 32a is positioned at top,isolation structure 12 zone.

After forming first stress film on the nmos pass transistor, then form second stress film of thickness greater than the grid of first stress film and nmos pass transistor, and second stress film carried out planarization, then second stress film is carried out selective etch, make that remaining second stress film and first stress film have junction preferably on the PMOS transistor, can not produce the defective of projection, thereby can not exert an influence to follow-up technology (for example interconnection process), and can increase the process window of subsequent technique, improve the stability of manufacturing process; In addition, also can improve the stability of the device of formation.

Figure 16 is the flow chart of second embodiment of the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor of the present invention.In this second embodiment, described the first transistor is the PMOS transistor, and transistor seconds is a nmos pass transistor.

As shown in figure 16,

Step S200 provides to have nmos pass transistor and the transistorized Semiconductor substrate of PMOS.

Described nmos pass transistor has grid, source electrode and drain electrode, and described PMOS transistor has grid, source electrode and drain electrode.

Step S210 forms first stress film on described PMOS transistor.

The step of its formation is as follows, deposition first stress film on PMOS transistor and nmos pass transistor at first, and pattern is protected first stress film on the described PMOS transistor with photoresist then, removes first stress film on the described nmos pass transistor by etching.

The method that deposits described first stress film is a plasma enhanced chemical vapor deposition, and the temperature of deposition is 200 to 300 ℃.

Described first stress film is a silicon nitride.The flow of the gas by change forming silicon nitride film and the power of radio frequency source can change the content of hydrogen in the silicon nitride of formation, form the silicon nitride film with compression.

The compression silicon nitride film can improve the mobility of charge carrier rate in hole among the PMOS.

Step S220 forms second stress film that mixes on described first stress film and nmos pass transistor, the thickness of described second stress film equals the thickness sum of the transistorized gate dielectric layer of described PMOS, grid and first stress film at least.

Impurity in second stress film of described doping is germanium or carbon.Described second stress film is a silicon nitride, mixes the tensile stress that germanium or carbon can improve this rete in silicon nitride film.

Step S230, described second stress film of planarization is exposed the surface of first stress film on the described PMOS transistor gate.

Among the embodiment therein, the technology of described second stress film of planarization is cmp, and wherein, first stress film of the transistorized grid of described PMOS top stops layer for grinding.

In a further embodiment, the step of described second stress film of planarization is as follows:

At first described second stress film is carried out chemical mechanical milling tech, make described second stress film have comparatively smooth surface;

Then described second stress film is carried out etching technics, described second stress film of etching, till the first stress film surface of extremely described PMOS transistor gate top was exposed, promptly described first stress film was an etching stop layer.

Step S240, forming the photoresist pattern on the surface that described first stress film is exposed and on second stress film above the nmos pass transistor grid, wherein, the live width of the photoresist pattern on second stress film above the described nmos pass transistor grid is greater than the live width of the grid of described nmos pass transistor.

Step S250, etching is not by the second stress rete of described photoresist pattern covers, until second stress film of removing on the described first stress rete.

Described etching is a dry etching.

After finishing etching, residue has certain thickness second stress film on described nmos pass transistor.

Further, remove described photoresist pattern.

After forming first stress film on the PMOS transistor, then form second stress film of thickness greater than first stress film and the transistorized grid of PMOS, and second stress film carried out planarization, then second stress film is carried out selective etch, make that remaining second stress film and first stress film have junction preferably on nmos pass transistor, can not produce the defective of projection, thereby can not exert an influence to follow-up technology (for example interconnection process), and can increase the process window of subsequent technique, improve the stability of manufacturing process; In addition, also can improve the stability of the device of formation.

Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.

Claims

1, a kind of manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor is characterized in that, comprising:

2, the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor as claimed in claim 1 is characterized in that, the step that forms first stress film is as follows:

Remove described photoresist pattern;

3, the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor as claimed in claim 2 is characterized in that: the described in-situ doped impurity that mixes is germanium or carbon.

4, the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor as claimed in claim 3 is characterized in that, further comprises: to the execution UV-irradiation technology or the thermal anneal process of described first stress film.

5, as the manufacture method of the described double-stress membrane complementary metal oxide semiconductor (CMOS) transistor of the arbitrary claim of claim 1 to 4, it is characterized in that: described first stress film is a silicon nitride.

6, the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor pipe as claimed in claim 1 is characterized in that: if transistor seconds is a nmos pass transistor, the technology that then forms second stress film is deposition and in-situ doped technology.

7, the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor as claimed in claim 1, it is characterized in that: the technology of described second stress film of planarization is cmp, wherein, first stress film of the grid of described the first transistor top stops layer for grinding.

8, the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor as claimed in claim 1 is characterized in that, the step of described second stress film of planarization is as follows:

Described second stress film is carried out chemical mechanical milling tech;

9, the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor as claimed in claim 1 is characterized in that: described second stress film is a silicon nitride.

10, as the manufacture method of the described double-stress membrane complementary metal oxide semiconductor (CMOS) transistor of the arbitrary claim of claim 1 to 4, it is characterized in that: described etching is a dry etching.

11, the manufacture method of double-stress membrane complementary metal oxide semiconductor (CMOS) transistor as claimed in claim 10 is characterized in that: detect the etching terminal of described dry etching as etching stop layer or control the etching terminal of described dry etching with etch period with first stress film.

12, as the manufacture method of the described double-stress membrane complementary metal oxide semiconductor (CMOS) transistor of the arbitrary claim of claim 1 to 4, it is characterized in that, further comprise: remove described photoresist pattern.