CN101404569B - Apparatus and method for frequency expansion of reference clock signal - Google Patents

Abstract

The invention provides a device for spreading spectrum of a reference clock signal and a method thereof, wherein, the device comprises a divider which is used for receiving an M value and an N value, generating a first floating point decimal according to the M value and the N value, and sending the first floating point decimal to a spread spectrum control generator; the spread spectrum control generator which is used for receiving the first floating point decimal from the divider and the reference clock signal from an analog circuit, generating a second floating point decimal for spreading the spectrum according to the first floating point decimal, the reference clock signal and modulation frequency, and sending the second floating point decimal to a delta sigma modulator; the delta sigma modulator which is used for generating a first integer distribution according to the second floating point decimal and sending the first integer distribution to the analog circuit; and the analog circuit which is used for sending the external reference clock signal to the spread spectrum control generator, generating a first frequency division clock signal according to the first integer distribution, and comparing and adjusting phases of the first frequency division clock signal, and spreading the spectrum of the reference clock signal.

Description

Reference clock signal is opened up apparatus and method frequently

Technical field

The present invention relates to electronic device field, relate in particular to a kind of apparatus and method that are used for reference clock signal is opened up frequency.

Background technology

When an electronic system is worked under certain single-frequency, since very high at the energy of this frequency, therefore will be created in the very strong electromagnetic pulse interference (Electromagnetic Interference is called for short EMI) under this frequency.This electromagnetic interference can be to other electronic equipments, or human body exerts an influence.To electronic product, especially to electronic equipment for consumption, all there is very strict EMI to quantize regulation, at present to reduce EMI.At present for the basic skills that reduces EMI be by clock or signal exhibition frequently (spreading spectrum) to reduce the energy of characteristic frequency.

The method of spread spectrum clock is by control phase-locked loop (Phase Lock Loop when utilizing floating-point N phase-locked loop (fractional N PLL) to produce recovered clock at present, abbreviation PLL) electric capacity or the resistance value of low pass filter in, influence voltage controlled oscillator (VoltageControl Oscillator thus, abbreviation VCO) output clock phase reaches exhibition purpose frequently.As shown in Figure 1, be the instantiation of this method.

This method need design the tunable capacitor and the adjustable resistance of more complicated in board design, and because the factor of technology and design is difficult to accomplish accurate.On the other hand, accomplish to open up change frequency and amplitude frequently and all can change, cost can be bigger.The 3rd, be in the filter of phase-locked loop, to realize owing to produce exhibition frequency function, so the high-frequency noise that needs extra circuit to come filtering to introduce owing to frequency modulation(FM).

As shown in Figure 2, be the instantiation of another kind method commonly used.This method is at first handled the input signal phase place, and the clock signal that generates leggy by the multiphase clock generator is sent into phase option circuit.The spread spectrum control circuit is controlled the frequency of spread spectrum and the amplitude of frequency, and by accumulator phase place is selected to control, by selecting suitable phase place output spread spectrum signal.

The shortcoming of this method mainly comprises following 2 points:

The first, exhibition precision frequently is low.The precision of Zhan Pin depends on the phase place number that the multiphase clock generator can produce and the precision of phase intervals.Generally speaking number of phases be 2 index doubly, mean every increase by 1 bit (bit) control, phase place produces and the phase place selection all will increase a large amount of hardware spendings.These characteristics make the number that produces phase place receive restriction, thereby have limited exhibition precision frequently.The precision of Zhan Pin is low to be unfavorable for increasing the noise of spread spectrum clock simultaneously at the receiving terminal restoring signal.

The second, the spread spectrum clock signal has spuious (spur).The phase place of accumulator control select can be in the spread spectrum signal of output bigger spuious of produce power.This is by the decision of the characteristic of accumulator.This spuious very harmful in the system that needs the high-quality clock signal.

Summary of the invention

One or more problems in view of the above the present invention proposes a kind of apparatus and method that are used for reference clock signal is opened up frequency.By utilizing ripe floating-point N PHASE-LOCKED LOOP PLL TECHNIQUE, when recovering specific clock accurately, produce the information of clock modulation by digital method, and exhibition frequency and amplitude frequently can easily dispose, and to reach the exhibition of generation clock signal frequently, finally reduces the purpose of the EMI of whole system.

Being used for that according to an embodiment of the invention reference clock signal is opened up device frequently comprises: divider (Divider) 302, be used to receive M value and N value, and generate the first floating-point decimal and the first floating-point decimal is sent to exhibition frequency control generator according to M value and N value; Exhibition is control generator (SSC generator) 304 frequently, be used to receive from the first floating-point decimal of divider with from the reference clock signal of analog circuit, according to the first floating-point decimal, reference clock signal, and modulating frequency generate and be used to open up the second floating-point decimal frequently and the second floating-point decimal is sent to Δ ∑ modulator (∑ Δ Modulator); Δ ∑ modulator 306 is used for generating the distribution of first integer and sending it to analog circuit according to the second floating-point decimal; And analog circuit, be used for to send to from the reference clock signal of outside exhibition control generator frequently, and be used for distribute generating first sub-frequency clock signal, and first sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment reference clock signal is opened up frequently according to first integer.

Wherein,exhibition control generator 304 frequently comprises: generator is calculated in configurable exhibition amplitude frequently, be used to receive from the first floating-point decimal of divider with from the reference clock signal of analog circuit, generate the crest frequency amplitude and send it to configurable triangular-wave generator according to the first floating-point decimal and reference clock signal, and be used for generating the second floating-point decimal and the second floating-point decimal being sent to Δ ∑ modulator according to the triangular wave that configurable triangular-wave generator generates; And configurable triangular-wave generator, be used for generating triangular wave and triangular wave being sent to configurable exhibition amplitude calculating frequently generator according to crest frequency amplitude and modulating frequency.

Wherein, Δ ∑ modulator 306 also is used for distributing according to being used for generating second integer at the 3rd floating-point decimal at random that exhibition adds noise signal frequently the time, and second integer distributed sends to analog circuit; And analog circuit distribute to generate second sub-frequency clock signal according to second integer, and second sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment reference clock signal is opened up frequently.

Triangle wave period is the inverse of modulating frequency.Zhan Pin comprises following at least a: central authorities exhibitions frequently (central spreading), go up exhibition (up spreading), and exhibition (down spreading) frequently down frequently.

Being used for according to another aspect of the present invention may further comprise the steps the method that reference clock signal is opened up frequently: step S402 receives M value and N value, according to M value and the N value generation first floating-point decimal; Step S404, according to the first floating-point decimal, reference clock signal, and the modulating frequency of configuration generate and be used to open up the second floating-point decimal frequently; Step S406 generates first integer according to the second floating-point decimal and distributes; And step S408, distribute to generate corresponding sub-frequency clock signal according to first integer, and sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment reference clock signal is opened up frequently.

Wherein, step S404 may further comprise the steps:step 1 generates the crest frequency amplitude according to the first floating-point decimal and reference clock signal; Step 2 is according to the modulating frequency generation triangular wave of crest frequency amplitude and configuration; And step 3, generate the second floating-point decimal according to triangular wave.

Wherein, generating corresponding second integer according to the second floating-point decimal with the 3rd floating-point decimal at random that is used for adding noise signal when opening up frequently distributes, distribute to generate corresponding sub-frequency clock signal according to second integer, and sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment reference clock signal is opened up frequently.

Wherein, be triangle wave period the inverse of the modulating frequency of configuration.Zhan Pin comprises following at least a: central authorities open up frequently, go up and open up frequently, reach exhibition frequency down.

By the present invention, utilize the structure of digital circuit and floating-point N phase-locked loop to realize exhibition frequently, design difficulty reduces greatly, and accuracy improves, and because existing phase-locked loop structures is not destroyed, signal to noise ratio is very desirable.And because major part adopts digital circuit, reusability, testability, flexibility and system are predictable greatly to be improved.

Description of drawings

Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:

Fig. 1 is a kind of block diagram of reference clock signal being opened up device frequently of the prior art;

Fig. 2 is the another kind of block diagram of reference clock signal being opened up device frequently of the prior art;

Fig. 3 is a block diagram of according to an embodiment of the invention reference clock signal being opened up device frequently; And

Fig. 4 is the flow chart of the method frequently of according to an embodiment of the invention reference clock signal being opened up.

Embodiment

Below with reference to accompanying drawing, describe the specific embodiment of the present invention in detail.

The present invention is when recovering the characteristic frequency clock, and floating-point N phase-locked loop structures and technology that utilization must be used only need to add the part digital circuit, can produce on recovered clock and open up frequently, to reach the purpose that reduces EMI.Utilize the technology and the Digital Signal Processing of floating-point N phase-locked loop, in the recovered clock frequency, can produce the accurate spread spectrum clock of any cycle and amplitude, and can be that central authorities open up frequently, go up and open up frequently, reach exhibition frequency down, the spuious energy of effective simultaneously control output spread spectrum clock.

Fig. 3 is a block diagram of according to an embodiment of the invention reference clock signal being opened up device frequently.Wherein, part be a digital processing circuit shown in the frame of broken lines below among Fig. 3, is analog circuit 308 partly shown in the top dot-dash wire frame.Particularly, as shown in Figure 3, this device comprises:divider 302, exhibition becontrol generator 304, ∑ Delta modulator 306, analog circuit 308 frequently.Below be the specific descriptions of the each several part of this device:

Divider 302 is used to receive M value that is used to recover and N value from transmit leg, and M value and N value are handled to obtain the first floating-point decimal, and the exhibition frequency amplitude that the first floating-point decimal sends in the exhibition frequency control generator is calculated generator.

Exhibition iscontrol generator 304 frequently, be used to receive from the first floating-point decimal of divider with from the reference clock signal of analog circuit, according to the first floating-point decimal, reference clock signal, and modulating frequency generate and be used to open up the second floating-point decimal frequently and the second floating-point decimal is sent to Δ ∑ modulator.

Wherein, exhibition control generator frequently is the exhibition of producing frequency modulation(FM) digital circuit frequently, comprise: generator is calculated in configurable exhibition amplitude frequently, be used to receive from the first floating-point decimal of divider with from the reference clock signal of analog circuit, generate the crest frequency amplitude and send it to configurable triangular wave (trianglewaveform) generator according to the first floating-point decimal and reference clock signal, and be used for generating the second floating-point decimal and the second floating-point decimal being sent to Δ ∑ modulator according to the triangular wave that configurable triangular-wave generator generates; And configurable triangular-wave generator, be used for generating triangular wave and triangular wave being sent to configurable exhibition amplitude calculating frequently generator according to crest frequency amplitude and modulating frequency.

Particularly, exhibition frequency control generator is the exhibition of producing frequency modulation(FM) digital circuit frequently.Comprising modulation period configurable triangular-wave generator and configurable exhibition amplitude calculating frequently generator.Exhibition frequently amplitude calculate after generator receives floating-point decimal from divider, the crest frequency of generator according to floating-point decimal and following formula (1) and (2) generation clock calculated in exhibition amplitude frequently, promptly, fs ' (this promptly opens up the peak value of frequency range frequently), and determine the value of floating-point decimal change according to the phase value that triangular-wave generator generates, add in the floating-point decimal, the final generation can be satisfied the floating-point decimal that exhibition requires frequently.The warbled frequency f sp that the triangular-wave generator utilization is disposed to this module generates triangular wave, and wherein triangle wave period is T (T=l/fsp).Be triangle wave period the inverse of the modulating frequency of configuration.Have for the warbled triangular wave cycle: T=fr/fsp (fsp is warbled frequency, fsp=1k, and 2k, 3k ...)

Wherein, for central authorities' exhibition frequency mode, because

$\mathrm{fs}=\frac{M}{N}\mathrm{fr}---\left(1\right)$

Therefore, the crest frequency for the clock after the frequency modulation(FM) has:

${\mathrm{fs}}^{\′}=\frac{M}{N}\mathrm{fr}\±\frac{M}{N}\·k\·\mathrm{fr}---\left(2\right)$

Wherein, k is a range coefficient, k=0.25%, 0.5%, 1%.....

Δ ∑ modulator 306 is used for generating first integer distribution (that is, the arithmetic mean of the integer in the certain hour equals this floating-point decimal) and sending it to analog circuit according to the second floating-point decimal.

Analog circuit 308, be used for to send to from the reference clock signal of outside exhibition control generator frequently, and be used for distribute generating first sub-frequency clock signal, and first sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment reference clock signal is opened up frequently according to first integer.Particularly, the output clock of the voltage-controlled oscillator (VCO) in the analog circuit will carry out frequency division according to integer value, and for example, integer is 10 and carries out 10 frequency divisions.Phase-locked loop will compare and adjust phase place according to the phase place of frequency-dividing clock and reference clock, final in the closed loop of phase-locked loop the clock signal after the exhibition frequently, promptly voltage controlled oscillator is output as the clock signal after the exhibition frequently.Whole process is dynamic, adaptive.

Wherein, Δ ∑ modulator 306 also is used for generating second integer according to the second floating-point decimal with the 3rd floating-point decimal at random that is used for adding noise signal when opening up frequently and distributes, and the distribution of second integer is sent to analog circuit; And analog circuit distribute to generate second sub-frequency clock signal according to second integer, and second sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment reference clock signal is opened up frequently.That is, can be chosen in adding shake (dither) signal in the Δ ∑ modulator.Dither signal simulated the filter filtering as noise signal after by Δ ∑ modulator shaping tremendously high frequency end, intensity by the control dither signal, can not influence exhibition precision and loop stability frequently, but can reduce the energy of spuious (spur) in the floating-point N phase-locked loop greatly, to realize output high-performance spread spectrum clock signal.This is to use other digital control approaches to realize that exhibition is frequently not available.To the digital Δ ∑ modulator that 24bit realizes, frequency resolution is fr/2^24, amplitude that can point-device control triangular wave, thereby very accurate control exhibition scope frequently.

Fig. 4 is the flow chart of the method frequently of according to an embodiment of the invention reference clock signal being opened up.As shown in Figure 4, this method may further comprise the steps:

Step S402 receives M value and N value, generates the first floating-point decimal according to M value and N value;

Step S404, according to the first floating-point decimal, reference clock signal, and the modulating frequency of configuration generate and be used to open up the second floating-point decimal frequently;

Step S406 generates first integer according to the second floating-point decimal; And

Step S408 generates corresponding sub-frequency clock signal according to first integer, and sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment reference clock signal is opened up frequently.

Wherein, step S404 may further comprise the steps:

Step 1 generates the crest frequency amplitude according to the first floating-point decimal and reference clock signal;

Step 2 is according to the modulating frequency generation triangular wave of crest frequency amplitude and configuration; And

Step 3 generates the second floating-point decimal according to triangular wave.

Wherein, generating corresponding second integer according to the second floating-point decimal with the 3rd floating-point decimal at random that is used for adding noise signal when opening up frequently distributes, distribute to generate corresponding sub-frequency clock signal according to second integer, and sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment reference clock signal is opened up frequently.

Wherein, be triangle wave period the inverse of the modulating frequency of configuration.Zhan Pin comprises following at least a: central authorities open up frequently, go up and open up frequently, reach exhibition frequency down.

Be the preferred embodiments of the present invention only below, be not limited to the present invention, for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. one kind is used for reference clock signal is opened up device frequently, it is characterized in that described device comprises:

Divider is used to receive M value and N value, and generates the first floating-point decimal and the described first floating-point decimal is sent to exhibition frequency control generator according to described M value and described N value, and wherein, M and N are integer;

Described exhibition is control generator frequently, be used to receive from the described first floating-point decimal of described divider with from the described reference clock signal of analog circuit, according to the described first floating-point decimal, described reference clock signal, and modulating frequency generate and be used to open up the second floating-point decimal frequently and the described second floating-point decimal is sent to Δ ∑ modulator;

Described Δ ∑ modulator is used for generating the distribution of first integer and sending it to described analog circuit according to the described second floating-point decimal; And

Described analog circuit, be used for to send to from the described reference clock signal of outside described exhibition control generator frequently, and be used for distributing and generate first sub-frequency clock signal, and described first sub-frequency clock signal and described reference clock signal are carried out bit comparison mutually and phase place adjustment described reference clock signal is opened up frequently according to described first integer.

2. device according to claim 1 is characterized in that, described exhibition control generator frequently comprises:

Generator is calculated in configurable exhibition amplitude frequently, be used to receive from the described first floating-point decimal of described divider with from the described reference clock signal of described analog circuit, generate the crest frequency amplitude and send it to configurable triangular-wave generator according to described first floating-point decimal and described reference clock signal, and be used for generating the described second floating-point decimal and the described second floating-point decimal being sent to described Δ ∑ modulator according to the triangular wave that described configurable triangular-wave generator generates; And

Described configurable triangular-wave generator is used for generating described triangular wave and described triangular wave being sent to described configurable exhibition amplitude calculating frequently generator according to described crest frequency amplitude and described modulating frequency.

3. device according to claim 2 is characterized in that,

Described Δ ∑ modulator also is used for generating second integer according to the described second floating-point decimal with the 3rd floating-point decimal at random that is used for adding noise signal when opening up frequently and distributes, and described second integer distribution is sent to described analog circuit; And

Described analog circuit distributes according to described second integer and generates second sub-frequency clock signal, and described second sub-frequency clock signal and described reference clock signal are carried out bit comparison mutually and phase place adjustment described reference clock signal is opened up frequently.

4. device according to claim 2 is characterized in that, described triangle wave period is the inverse of described modulating frequency.

5. according to each described device in the claim 1 to 4, it is characterized in that described exhibition frequency comprises following at least a: central authorities open up frequently, go up and open up frequently, reach exhibition frequency down.

6. one kind is used for reference clock signal is opened up method frequently, it is characterized in that, said method comprising the steps of:

Step S402 receives M value and N value, according to described M value and described N

Value generates the first floating-point decimal, and wherein, M and N are integer;

Step S404, according to the described first floating-point decimal, described reference clock signal, and the modulating frequency of configuration generate and be used to open up the second floating-point decimal frequently;

Step S406 generates first integer according to the described second floating-point decimal and distributes; And

Step S408, distributing according to described first integer generates corresponding sub-frequency clock signal, and described sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment described reference clock signal is opened up frequently.

7. method according to claim 6 is characterized in that, described step S404 may further comprise the steps:

Step 1 generates the crest frequency amplitude according to described first floating-point decimal and described reference clock signal;

Step 2 is according to the modulating frequency generation triangular wave of described crest frequency amplitude and described configuration; And

Step 3 generates the second floating-point decimal according to described triangular wave.

8. according to claim 6 or 7 described methods, it is characterized in that, generating corresponding second integer according to the described first floating-point decimal with the 3rd floating-point decimal at random that is used for adding noise signal when opening up frequently distributes, distributing according to described second integer generates corresponding sub-frequency clock signal, and described sub-frequency clock signal and reference clock signal are carried out bit comparison mutually and phase place adjustment described reference clock signal is opened up frequently.

9. according to claim 6 or 7 described methods, it is characterized in that described triangle wave period is the inverse of the modulating frequency of described configuration.

10. according to claim 6 or 7 described methods, it is characterized in that described exhibition frequency comprises following at least a: central authorities open up frequently, go up and open up frequently, reach exhibition frequency down.

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