CN101370089B - Split joint display parallel processing system - Google Patents
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Abstract
Description
Technical field
The present invention relates to the electronic display system field, particularly a kind of tiled display parallel processing system (PPS).
Background technology
The tiled display treatment system obtains application more and more widely as a kind of novel display device.Performance requirement is more and more higher, and the particularly requirement of display speed is 60Hz such as the 3D rendering refresh rate more than 5,000,000 pixels, and this transmission rate for shows signal has proposed new requirement; Spliced display wall also will show demonstration output signal, network video data and IP video data etc. from monitoring camera, DVD player, computer except showing computer desktop or large-scale application.For the image information that each IMAQ passage collects, need superpose on whole spliced display wall usually shows output.
Fig. 1 is a tiled display treatment system of the prior art, a tiled display processor will start 32 display units of demonstration (16 PCI show plug-in card), also will finish the collection (2 PCI plug-in cards) of 16 tunnel vision signals (4 PCI plug-in cards) and 4 road rgb signals (pcs signal), the slot sum reaches 22.Because the speed limit of a tiled display processor P CI, stack and other various application of processing image information make this tiled display processor can't bear the heavy load simultaneously, and display speed is slow, and refresh rate is very low, so can only handle some simple application.
The patent No. is ZL200510037591.0, name is called the patent of invention of multilayer real time image overlapping controller, a kind of multilayer real time image overlapping controller is disclosed, it comprises kernel control module, output module and a plurality of input module, this kernel control module, output module is connected by signal bus and backboard with a plurality of input modules, kernel control module produces needed pixel clock of entire image overlapping controller and synchronizing signal, these signals pass to all signal processing modules that are connected on the signal bus, make the picture signal at all entering signal centers synchronous.Each display unit can be realized the nearly stack of 11 tomographic images.If the splice displaying system of forming by 16 display units, each display unit all will insert 1 road desktop rgb signal, 10 vision signals or rgb signal, and accumulative total just has 176 vision signals or rgb signal transmission line and has 176 plug receptacles and interface circuit thereof at least.And most input image informations need handle by video exchange matrix or RGB switching matrix, increase by 160 video signal transmission wire and 160 plug receptacles and interface circuit thereof so again.This image controller also will carry out convergent-divergent to each input image information to be handled, and needs a large amount of hardware resources to finish.So it is complicated that the splice displaying system cost that adopts such image overlay controller, is produced debugging than higher, installation and maintenance are all inconvenient.
Summary of the invention
The invention provides a kind of tiled display parallel processing system (PPS), its processing speed than very fast, refresh rate than higher.
Technical scheme of the present invention is: a kind of tiled display parallel processing system (PPS) is characterized in that comprise: circuit, at least one frame synchronization control circuit are selected in desktop processor, at least one signal receiving processor and at least one stack; The output of described desktop processor selects the input of circuit to be connected with described stack respectively with the output of described signal receiving processor; One end of described frame synchronization control circuit is connected respectively with described desktop processor with described signal receiving processor, and the other end selects circuit to be connected with described stack;
Described desktop processor produces desktop picture information, outputs to corresponding described stack and selects circuit; Described signal receiving processor is used to receive the video image of input, show processing after, output to corresponding described stack and select circuit;
Described stack selects circuit to receive the desktop picture information that described desktop processor sends, and therefrom extracts the position overlapped information and according to this position overlapped information the described video image that receives is carried out outputing to corresponding display unit after the overlap-add procedure to show;
Described frame synchronization control circuit is used to detect the frame synchronizing signal of the video image that described signal receiving processor and described desktop processor export separately, and the video image of controlling described signal receiving processor and the output of desktop processor according to this frame synchronizing signal output control signal is synchronous.
Tiled display parallel processing system (PPS) of the present invention, show with the receiver, video image of traditional tiled display processor and to video image and to handle and the partial stack function is mainly finished by signal receiving processor, the function of traditional tiled display processor generation desktop picture information is finished by the desktop processor; Select circuit to realize by the stack among the present invention the function that image is carried out overlap-add procedure of traditional tiled display processor; The present invention is divided into various piece with the processing capacity of traditional tiled display processor and finishes jointly like this, various piece does not take nervous computer resource mutually, desktop processor, signal receiving processor, stack selection circuit disposal ability have separately fully been guaranteed, can make tiled display parallel processing system (PPS) of the present invention efficiently to move, processing speed than very fast, refresh rate than higher; And the stack of forming this tiled display parallel processing system (PPS) selects circuit, signal receiving processor can be designed to special circuit or chip as required separately; Can develop, safeguard and update various piece, thereby can reduce the cost of development cost, maintenance cost and update.
Description of drawings
Fig. 1 is the structure principle chart of the tiled display treatment system of prior art;
Fig. 2 is the structural principle block diagram of tiled display parallel processing system (PPS) one embodiment of the present invention;
Fig. 3 is the structural principle block diagram of tiled display parallel processing system (PPS) one embodiment of the present invention;
Fig. 4 is the structural principle block diagram of tiled display parallel processing system (PPS) one embodiment of the present invention;
Fig. 5 is the structural principle block diagram of tiled display parallel processing system (PPS) one embodiment of the present invention;
Fig. 6 is the structural principle block diagram of tiled display parallel processing system (PPS) one embodiment of the present invention;
Fig. 7 is the structural principle block diagram that circuit one embodiment is selected in stack in the tiled display parallel processing system (PPS) of the present invention;
Fig. 8 is the structural principle block diagram that circuit one embodiment is selected in stack in the tiled display parallel processing system (PPS) of the present invention;
Fig. 9 is the structural principle block diagram of output circuit one embodiment in the tiled display parallel processing system (PPS) of the present invention;
Figure 10 is a structural principle block diagram of cutting apart output and circuit one embodiment in the tiled display parallel processing system (PPS) of the present invention;
Figure 11 is the structural principle block diagram of output circuit one embodiment in the tiled display parallel processing system (PPS) of the present invention.
Embodiment
Tiled display parallel processing system (PPS) of the present invention, show that with the receiver, video image of traditional tiled display processor and to video image the function of processing (comprise window, convergent-divergent handle and partial stack) mainly finished by signal receiving processor, the function that traditional tiled display processor is produced desktop picture information is finished by the desktop processor, when needed, the desktop processor can also be taken the task to the part inputted video image is windowed, convergent-divergent is handled; Traditional tiled display processor being carried out the partial function of overlap-add procedure selects circuit to realize image by the stack among the present invention; The present invention is divided into various piece with the processing capacity of traditional tiled display processor and finishes jointly like this, various piece does not take nervous computer resource mutually, desktop processor, signal receiving processor, stack selection circuit disposal ability have separately fully been guaranteed, can make tiled display parallel processing system (PPS) of the present invention efficiently to move, processing speed than very fast, refresh rate than higher; And the stack of forming this tiled display parallel processing system (PPS) selects circuit, signal receiving processor can be designed to special circuit or chip as required separately; Can develop, safeguard and update various piece, thereby can reduce the cost of development cost, maintenance cost and update.
Below in conjunction with the drawings and specific embodiments the present invention is done a detailed elaboration.
Embodiment one
As Fig. 2, in this embodiment, tiled display parallel processing system (PPS) of the present invention comprises that circuit 1 is selected in desktop processor, signal receiving processor, stack, selection circuit 2 superposes; The output of described desktop processor selects circuit 1, stack to select the input of circuit 2 to be connected with stack respectively with the output of described signal receiving processor.
Described desktop processor produces desktop picture information, outputs to corresponding described stack respectively and selects circuit; Described signal receiving processor is used to receive the video image of input, show processing (comprise window, convergent-divergent is handled, partial stack) after output to stack respectively and select circuit 1 and stack to select circuit 2; Stack is selected circuit 1, stack to select circuit 2 and is received the desktop picture information that described desktop processor sends respectively, extracts the position overlapped information and according to this position overlapped information the described video image that receives is carried out outputing to corresponding display unit after the overlap-add procedure to show.
Further, in order to adapt to the needs of spliced display wall, tiled display parallel processing system (PPS) of the present invention can also comprise to be cut apart output circuit 1 and cuts apart output circuit 2, the input of cutting apart output circuit 1 selects the output of circuit 1 to be connected with stack, and the input of cutting apart output circuit 2 selects the output of circuit 2 to be connected with stack; The described video image of cutting apart after output circuit 1 receives stack selection circuit 1 overlap-add procedure, cut apart output circuit 2 and receive video image after circuit 2 overlap-add procedure are selected in stack, and respectively the video image that receives is divided into and outputs to after at least two image blocks and cut apart output circuit 1, cut apart the corresponding display unit of output circuit 2 and show.
Select the video image of circuit synchronous in order to make desktop processor and signal receiving processor output to stack, in this embodiment, tiled display parallel processing system (PPS) of the present invention also comprises frame synchronization control circuit 1 and frame synchronization control circuit 2, one end of frame synchronization control circuit 1 selects circuit 1 to be connected with stack, and the other end is connected with desktop processor and signal receiving processor respectively; One end of frame synchronization control circuit 2 selects circuit 2 to be connected with stack, the other end is connected with desktop processor and signal receiving processor respectively, the frame synchronization control circuit is used to detect the desktop processor and signal receiving processor outputs to the frame synchronizing signal that circuit is selected in stack, come control signal receiving processor and desktop processor output video image according to this frame synchronization control signal output control signal, so that receiving processor and desktop processor output to video image frame synchronization or relative frame synchronization that circuit is selected in each stack.
Wherein stack selects circuit can comprise in one embodiment, as Fig. 7, and place in circuit, first memory, color switch (color key) comparison circuit and first output circuit; One end of described place in circuit is connected with described output circuit by described first memory; The other end of place in circuit is connected with the output of desktop processor and signal receiving processor respectively; One end of color switch comparison circuit is connected with first output circuit, and the other end is connected with described place in circuit; Described string and conversion are that the serial data or the differential signal that receive are converted to parallel data;
Place in circuit is used to receive the desktop picture information of desktop processor and the video image of signal receiving processor output; And the described video image that receives and described desktop picture information gone here and there and change.During concrete enforcement, can adopt the TMDS agreement described video image is gone here and there and to change, can also produce pixel clock required in the image transmission course and row, frame synchronizing signal simultaneously.Wherein said desktop picture information comprises the particular color information that the video image of described desktop processor self output and the video image that described signal receiving processor is exported show on described desktop processor.The video image of signal receiving processor adopts particular color to show in the zone that desktop processor uplifting window shows, the video image window displayed zone on the desktop processor that is signal receiving processor only shows a kind of single color, so that distinguish identification.The all corresponding particular color information of the video image of each signal receiving processor, this particular color information has obviously different with the normal pixel coder that shows.
First memory is provided with the memory block in this first memory, be used for video image and desktop picture information after described string and the conversion are stored.Can store respectively the video image after described string and the conversion in one embodiment, the video image that is about to the desktop picture information of desktop processor and signal receiving processor output is deposited respectively in separately the memory block.
Color switch (color key) comparison circuit, be used for according to described particular color information, from described desktop picture information, obtain the video image of described desktop processor and the position overlapped information of video image on described desktop processor of described signal receiving processor.Because signal receiving processor has particular color information what the desktop processor showed, then can obtain the video image of desktop processor and the position overlapped information of video image on the desktop processor of signal receiving processor according to the particular color information that color key comparison circuit shows from the desktop processor.When the video image of desktop processor and signal receiving processor stores separately memory block respectively into, described position overlapped information can comprise the sequential read of each memory block breath of winning the confidence in one embodiment, promptly from the sequencing of each memory block reading images information.In the specific implementation, whether the particular color information in this color switch comparison circuit comparison desktop picture information and the particular color information of signal receiving processor is consistent, when the particular color information of comparative result and signal receiving processor is consistent, the address information of the memory block of this signal receiving processor of output gating, the address information of the memory block of output desktop processor when comparative result is inconsistent, this address strobe information and other clock, the address information that frame synchronization reads is combined into the address code information of reading of each memory block, reads address code information according to this and can read the image information that current needs are exported in each memory block.
First output circuit is used for choosing required image information and the laggard line output of string conversion according to described position overlapped information in described first memory.
Consider monochrome information according to described video image, color switch comparison circuit obtains the video image of described desktop processor and the position overlapped information of video image on the desktop processor of signal receiving processor from described desktop picture information, the time-delay that this process need is certain, for synchronous output image information, described stack selects circuit can also comprise delay circuit, be connected between described color switch comparison circuit and described first output circuit, as Fig. 8, be used to set delay time, described first output circuit is chosen required image information and the laggard line output of string conversion according to described position overlapped information in described memory after this delay time.The image information that can guarantee the output of first output circuit is synchronous.
Wherein cut apart output circuit and can comprise in one embodiment, as Fig. 9, receiving circuit, second memory, storage control unit, cutting unit, synchronous and the clock signal adjustment unit and second output circuit.
Described receiving circuit is used for receiving the video image after overlap-add procedure is exported, synchronous and clock signal from described superposing control circuit; Described second memory receives and stores described video image under the control of described storage control unit, described cutting unit reads video image and the video image that is read is divided into several image blocks from described second memory, and the number of described image block equals the number of described second output circuit that is connected with described second memory; Described clock signal adjustment unit is used for adjusting the synchronous and clock signal of image block in described cutting unit segmented video image; Described second output circuit of every cover is connected with a display unit, be used for according to adjusted synchronously and clock signal the image block of correspondence is flowed to the display unit of correspondence.
Preferably: described receiving circuit can comprise the image input interface and second serial-parallel conversion circuit of serial connection, described image input interface is used to receive the serial video image that circuit output is selected in described stack, and described first serial-parallel conversion circuit is used for described serial video image transitions is become the parallel video image; Described second output circuit comprises the parallel-to-serial converter and the image output interface of serial connection, and described parallel-to-serial converter is used for converting described image block to serial image data; Described image output interface is used to connect described display unit; The attendant advantages of this preferred version is, comprises serial-parallel conversion circuit and parallel-to-serial converter, guaranteed the compatibility with existing display card, display unit; Simultaneously, the parallel image data are easier to be cut apart, and has reduced the complexity of partitioning circuitry.
Preferably, the described output circuit of cutting apart can also comprise the refresh rate adjustment unit, and as Figure 10, described refresh rate adjustment unit is connected with described cutting unit, is used to improve or reduce the refresh rate of the image block of described cutting unit output.In this preferred version, by improving or reducing refresh rate, can effectively utilize the bandwidth of various coffrets, be implemented in the high relatively resolution of output in the limited bandwidth.
Alternatively, the described output circuit of cutting apart also comprises the resolution adjustment unit, as Figure 11, described resolution adjustment unit is connected with described cutting unit, the resolution that is used for described cutting unit is cut apart each image block that obtains is amplified, and perhaps reduces the described resolution of each image block that module segmentation obtains of cutting apart with downscaled images.In this preferred version, can be by resolution adjustment unit each image block that zooms in or out.
Embodiment two
As Fig. 3, in this embodiment, tiled display parallel processing system (PPS) of the present invention comprises that 4 cut apart output circuit, 4 stack selection circuit and 3 signal receiving processors, 1 desktop processor.The desktop processor also is equivalent to a processor, the output of desktop processor selects circuit to be connected with 4 stacks respectively, the output of each signal receiving processor selects circuit to be connected with 4 stacks respectively, and 4 stack selection circuit are cut apart output circuit and are connected one by one with 4.
Each signal receiving processor and desktop processor can be installed rgb signal input Acquisition Circuit or video input Acquisition Circuit.Each signal receiving processor and desktop processor can be inserted with 2 video cards, and each video card all has 2 Dual DVI (dual link DVI) to show output, add up to 16 to show output.Select the video image of circuit synchronous in order to make four processors output to stack, also include 4 frame synchronization control circuits in this embodiment, each frame synchronization control circuit is connected corresponding stack and selects circuit and desktop processor, between the signal receiving processor, be used to detect the frame synchronizing signal of the video image that described signal receiving processor and described desktop processor export separately, control described signal receiving processor and desktop processor output video image according to this frame synchronizing signal output control signal that detects, so that four processor output video image displayed frame synchronization or relative frame synchronization, wherein each Dual DVI output resolution ratio is 2048X1536X60hz, and output frequency arrives 245M pixel/s.4 of every processor show that output is crossed as 4 groups of video display signals and delivers to 4 stack selection circuit.Wherein each processor to be exported video image displayed and be divided into four parts by image display area, image display area can be divided intowindow 101,window 102,window 103,window 104, the video image ofwindow 101 parts of each processor is all delivered to stack and is selected circuit 1, the video image ofwindow 102 parts of each processor is all delivered to stack and is selected circuit 2, the video image ofwindow 201 parts of each processor is all delivered to stack and is selected circuit 3, and the video image ofwindow 202 parts of each processor is all delivered to stack and selected circuit 4.Each stack selects circuit to superpose and select to handle importing 4 tunnel video images that carry out frame synchronization control through the frame synchronization control circuits, and this image overlay method is identical with embodiment one, does not give unnecessary details at this.
Video image after the overlap-add procedure of stack selection circuit output outputs to each self-corresponding output circuit of cutting apart.During specific embodiment, cut apart the shows signal (1024X768X60hz) that output circuit can be divided into 4 road low resolutions to the shows signal of 1 tunnel high-resolution (2048x1536X60hz), the display unit of delivering to then on the corresponding spliced display wall shows.The division processing method of cutting apart output circuit is identical with embodiment one, does not give unnecessary details at this.
Present embodiment is except can handling outside incoming video signal, can also on above 4 processors, dispose 2 gigabit network interfaces respectively, can the fan-in network shows signal (comprising computer desktop shows signal and IP vision signal in the network service scope), can carry out convergent-divergent to these signals equally and handle, any one display unit or a plurality of display unit delivered on the spliced display wall show.
Embodiment three
This embodiment is the further improvement to embodiment two, Fig. 4 shows the adjustment scheme of this embodiment to embodiment two, in this embodiment, tiled display parallel processing system (PPS) of the present invention also comprises video capture circuit 1 and video capture circuit 2, wherein the output of video capture circuit 1 is connected with the input of signal receiving processor 3 with signal receiving processor 4 respectively, and the output of video capture circuit 2 is connected with the input of signal receiving processor 3 with signal receiving processor 4 respectively; Described video capture circuit input is used to gather video image, and the video image of described collection is divided into two parts, part video image outputs to one of them signal receiving processor, a part of in addition video image outputs to the another one signal receiving processor, and signal receiving processor carries out convergent-divergent to the video image that receives respectively to be handled.Four outputs of desktop processor and signal receiving processor 1 still select circuit to be connected with four stacks respectively, the output of different is signal processor 3 selects circuit 1 and stack to select circuit 2 to be connected with stack respectively, and the output of signal processor 4 selects circuit 3 with stack respectively and the selection circuit 4 that superposes is connected.
Select each stack among the embodiment two circuit will receive 4 road video images like this and carry out overlap-add procedure, be improved to each stack now and select circuit only need receive 3 road video images to carry out overlap-add procedure.The advantage that this shows this embodiment is to reduce the processing burden that circuit is selected in stack, can reduce by 2 video cards, thereby also reduce tiled display parallel processing system (PPS) cost of the present invention.And this embodiment can not need the matrix switching device just can realize that any inputted video image signal is delivered to the optional position that shows wall to be shown.
Embodiment four
This embodiment is the further improvement to implementing three, as Fig. 5, in this embodiment, tiled display parallel processing system (PPS) of the present invention also comprises the video exchange matrix circuit, the output of described video matrix switched circuit is connected with the input of video capture circuit 1, the input of video capture circuit 2 respectively, the output of described video capture circuit 1 is connected with signal receiving processor 3, and the output of video capture circuit 2 is connected with signal receiving processor 4; All the other connected modes are identical with embodiment three.
Described video matrix switched circuit is used for video image is divided into two parts, and a part of video image outputs to one of them video capture circuit, and a part of in addition video image outputs to the another one video capture circuit.
Can select each stack among the embodiment two circuit will receive 4 road video images to carry out overlap-add procedure equally like this, be improved to each stack now and select circuit only need receive 3 road video images to carry out overlap-add procedure.The advantage that this shows this embodiment also is to reduce the processing burden that circuit is selected in stack, can reduce by 2 video cards, thereby also reduce tiled display parallel processing system (PPS) cost of the present invention.
Embodiment five
Fig. 6 shows the scheme of further optimizing and revising of the present invention, the difference of this embodiment and embodiment four is to reduce by a signal receiving processor, utilize video capture circuit 1 and video capture circuit 2 can gather 8 road rgb signals and 32 tunnel vision signals simultaneously, the output of video capture circuit 1 is connected with the input of signal receiving processor 1 with signal receiving processor 2 respectively, the output of video capture circuit 2 is connected with the input of signal receiving processor 1 with signal receiving processor 2 respectively, four outputs of desktop processor select circuit to be connected respectively with four stacks, the output of signal receiving processor 1 selects circuit 1 and stack to select circuit 2 to be connected with stack respectively, and the output of signal receiving processor 2 selects circuit 3 and stack to select circuit 4 to be connected with stack respectively.2 signal receiving processors are delivered to a video card (every 2 of video card shows output) to the inputted video image that is cross-linked through video capture circuit and are carried out the convergent-divergent processing.
This shows that this embodiment selects circuit will receive 3 road video images to carry out overlap-add procedure to each stack among the embodiment four, be improved to each stack now and select circuit only need receive 2 road video images to carry out overlap-add procedure.The advantage that this shows this embodiment is that the processing burden that further having reduced superposes selects circuit can reduce by 2 video cards, thereby also further reduce tiled display parallel processing system (PPS) cost of the present invention.
Embodiment six
When tiled display parallel processing system (PPS) of the present invention is used at the simple video image of processing, can also save the desktop processor, in this embodiment, tiled display parallel processing system (PPS) of the present invention comprises at least two signal receiving processors and at least one stack selection circuit, and the output of at least two signal receiving processors selects the input of circuit to be connected with one of them stack; Described signal receiving processor is used to receive the video image of input, shows that outputing to corresponding described stack after the processing selects circuit; Described signal receiving processor of while also sends the position overlapped information to described stack selection circuit; Described stack is selected circuit according to described position overlapped information the described video image that receives to be carried out outputing to corresponding display unit after the overlap-add procedure to show.
Tiled display parallel processing system (PPS) among this embodiment comprises that also at least one cuts apart output circuit further, is connected described stack and selects between the output and corresponding display unit of circuit; The described number of cutting apart output circuit selects the number of circuit to equate with described stack; The described video image of cutting apart after output circuit receives described overlap-add procedure is divided into the video image that receives and outputs to corresponding described display unit at least after two image blocks and show.
In sum, tiled display parallel processing system (PPS) of the present invention, show that with the receiver, video image of traditional tiled display processor and to video image the function of processing (comprise window, convergent-divergent handle and partial stack) mainly finished by signal receiving processor, the function that traditional tiled display processor is produced desktop picture information is finished by the desktop processor, when needed, the desktop processor can also be taken the task to the part inputted video image is windowed, convergent-divergent is handled; Traditional tiled display processor being carried out the partial function of overlap-add procedure selects circuit to realize image by the stack among the present invention; The present invention is divided into various piece with the processing capacity of traditional tiled display processor and finishes jointly like this, various piece does not take nervous computer resource mutually, desktop processor, signal receiving processor, stack selection circuit disposal ability have separately fully been guaranteed, can make tiled display parallel processing system (PPS) of the present invention efficiently to move, processing speed than very fast, refresh rate than higher; And the stack of forming this tiled display parallel processing system (PPS) selects circuit, signal receiving processor can be designed to special circuit or chip as required separately; Can develop, safeguard and update various piece, thereby can reduce the cost of development cost, maintenance cost and update.
The above, be elaborating to several specific embodiments of tiled display parallel processor system of the present invention, in actual applications, signal receiving processor, cut apart output circuit, stack selects the number of circuit to set as required, cut apart output circuit and also can as required stack be selected the superimposed image of circuit input to cut apart how many pieces, the every display unit of delivering to respectively on the corresponding combination shows.
Above-described embodiment of the present invention does not constitute the qualification to protection range of the present invention.Any modification of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection range of the present invention.
Claims (10)
1. a tiled display parallel processing system (PPS) is characterized in that, comprising: circuit and at least one frame synchronization control circuit are selected in desktop processor, at least one signal receiving processor and at least one stack; The output of described desktop processor selects the input of circuit to be connected with each stack, and the output of each signal receiving processor selects the input of circuit to be connected with each stack respectively; One end of described frame synchronization control circuit is connected respectively with described desktop processor with described signal receiving processor, and the other end selects circuit to be connected with described stack;
Described desktop processor produces desktop picture information, outputs to corresponding described stack and selects circuit; Described signal receiving processor is used to receive the video image of input, show processing after, output to corresponding described stack and select circuit;
Described stack selects circuit to receive the desktop picture information that described desktop processor sends, and therefrom extracts the position overlapped information and according to this position overlapped information the described video image that receives is carried out outputing to corresponding display unit after the overlap-add procedure to show;
Described frame synchronization control circuit is used to detect the frame synchronizing signal of the video image that described signal receiving processor and described desktop processor export separately, and the video image of controlling described signal receiving processor and the output of desktop processor according to this frame synchronizing signal output control signal is synchronous.
2. tiled display parallel processing system (PPS) according to claim 1 is characterized in that: comprise that also at least one cuts apart output circuit, be connected described stack and select between the output and corresponding display unit of circuit; The described number of cutting apart output circuit selects the number of circuit to equate with described stack;
The described video image of cutting apart after output circuit receives described overlap-add procedure is divided into the video image that receives and outputs to corresponding described display unit at least after two image blocks and show.
3. tiled display parallel processing system (PPS) according to claim 1 and 2 is characterized in that: described desktop processor also is used to receive the video image of input, show processing after, output to corresponding described stack and select circuit.
4. tiled display parallel processing system (PPS) according to claim 1, it is characterized in that: when described signal receiving processor during at least two, described tiled display parallel processing system (PPS) also comprises two video capture circuits, the output of one of them video capture circuit is connected with the input of two signal receiving processors wherein respectively, and the input of these two signal receiving processors also is connected with the output of another one video capture circuit respectively; And the output of a signal receiving processor in these two signal receiving processors selects the input of circuit to be connected with at least one stack, and the output of another one signal receiving processor selects the input of circuit to be connected with remaining stack.
5. tiled display parallel processing system (PPS) according to claim 1, it is characterized in that: when described signal receiving processor during at least two, described tiled display parallel processing system (PPS) also comprises two video capture circuits and video exchange matrix circuit, the output of described video matrix switched circuit is connected with the input of two video capture circuits respectively, and the output of these two video capture circuits is connected with the input of two signal receiving processors of correspondence; And the output of a signal receiving processor in these two signal receiving processors selects the input of circuit to be connected with at least one stack, and the output of another one signal receiving processor selects the input of circuit to be connected with remaining stack.
6. tiled display parallel processing system (PPS) according to claim 1 is characterized in that: described stack selects circuit to comprise place in circuit, first memory, color switch comparison circuit and first output circuit; One end of described place in circuit is connected with described first output circuit by described first memory, and an end of described color switch comparison circuit is connected with described first output circuit, and the other end is connected with described place in circuit; The other end of place in circuit is connected with the output of described desktop processor and at least one signal receiving processor respectively;
Place in circuit is used to receive the desktop picture information of described desktop processor and the video image of described signal receiving processor output; And the video image that receives and described desktop picture information gone here and there and change after output to described first memory and store; Described desktop picture information comprises the video image of described desktop processor and the particular color information of video image on described desktop processor of described signal receiving processor output;
Color switch comparison circuit, be used for extracting the position overlapped information on the desktop processor described in the video image of the video image of described desktop processor output and the output of described signal receiving processor from described desktop picture information, and output to described first output circuit according to described particular color information;
First output circuit is chosen required image information and the laggard line output of string conversion according to described position overlapped information in described first memory.
7. tiled display parallel processing system (PPS) according to claim 6, it is characterized in that: described stack selects circuit also to comprise delay circuit, be connected between described color switch comparison circuit and described first output circuit, be used to preestablish delay time, described first output circuit is chosen required image information and the laggard line output of string conversion according to described position overlapped information in described first memory after this predefined delay time.
8. tiled display parallel processing system (PPS) according to claim 1 is characterized in that: the described output circuit of cutting apart comprises receiving circuit, second memory, storage control unit, cutting unit, synchronous and the clock signal adjustment unit and second output circuit;
Described receiving circuit is used for receiving the video image after overlap-add procedure is exported, synchronous and clock signal from described superposing control circuit;
Described second memory receives and stores described video image under the control of described storage control unit, described cutting unit reads video image and the video image that is read is divided into several image blocks from described second memory, and the number of described image block equals the number of described second output circuit that is connected with described second memory;
Described clock signal adjustment unit is used for adjusting the synchronous and clock signal of image block in described cutting unit segmented video image; Described second output circuit of every cover is connected with a display unit, be used for according to adjusted synchronously and clock signal the image block of correspondence is flowed to the display unit of correspondence.
9. tiled display parallel processing system (PPS) according to claim 8, it is characterized in that: described receiving circuit comprises the image input interface and second serial-parallel conversion circuit of serial connection, described image input interface is used to receive the serial video image of described superposing control circuit output, and described second serial-parallel conversion circuit is used for described serial video image transitions is become the parallel video image;
Described second output circuit comprises the parallel-to-serial converter and the image output interface of serial connection, and described parallel-to-serial converter is used for converting described image block to the serial video image; Described image output interface is used to connect described display unit.
10. tiled display parallel processing system (PPS) according to claim 9, it is characterized in that: described output circuit also comprises refresh rate adjustment unit or resolution adjustment unit, described refresh rate adjustment unit is connected with described cutting unit, is used to improve or reduce the refresh rate of the image block of described cutting unit output;
Described resolution adjustment unit is connected with described cutting unit, is used to increase resolution that described cutting unit cuts apart each image block that obtains with enlarged image, perhaps reduces described cutting unit and cuts apart the resolution of each image block that obtains with downscaled images.
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| CN101937325B (en)* | 2010-08-26 | 2012-07-11 | 广东威创视讯科技股份有限公司 | Control method of splicing wall and control system of splicing wall |
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